2022-04-12 08:55:54 +00:00
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.include "macros.inc"
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2022-04-18 04:19:18 +00:00
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.section .data
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2022-08-10 23:08:58 +00:00
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.balign 8
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2022-04-18 04:19:18 +00:00
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.global lbl_803DA098
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lbl_803DA098:
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# ROM: 0x3D7098
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.4byte 0
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.4byte 0
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.4byte __dt__28CArchMsgParmControllerStatusFv
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.4byte 0
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2022-04-12 08:55:54 +00:00
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.section .text, "ax"
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.global __dt__28CArchMsgParmControllerStatusFv
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__dt__28CArchMsgParmControllerStatusFv:
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/* 8005A090 00056FF0 94 21 FF F0 */ stwu r1, -0x10(r1)
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/* 8005A094 00056FF4 7C 08 02 A6 */ mflr r0
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/* 8005A098 00056FF8 90 01 00 14 */ stw r0, 0x14(r1)
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/* 8005A09C 00056FFC 93 E1 00 0C */ stw r31, 0xc(r1)
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/* 8005A0A0 00057000 7C 7F 1B 79 */ or. r31, r3, r3
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/* 8005A0A4 00057004 41 82 00 30 */ beq lbl_8005A0D4
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/* 8005A0A8 00057008 3C 60 80 3E */ lis r3, lbl_803DA098@ha
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/* 8005A0AC 0005700C 38 03 A0 98 */ addi r0, r3, lbl_803DA098@l
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/* 8005A0B0 00057010 90 1F 00 00 */ stw r0, 0(r31)
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/* 8005A0B4 00057014 41 82 00 10 */ beq lbl_8005A0C4
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/* 8005A0B8 00057018 3C 60 80 3E */ lis r3, __vt__24IArchitectureMessageParm@ha
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/* 8005A0BC 0005701C 38 03 8E 9C */ addi r0, r3, __vt__24IArchitectureMessageParm@l
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/* 8005A0C0 00057020 90 1F 00 00 */ stw r0, 0(r31)
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lbl_8005A0C4:
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/* 8005A0C4 00057024 7C 80 07 35 */ extsh. r0, r4
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/* 8005A0C8 00057028 40 81 00 0C */ ble lbl_8005A0D4
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/* 8005A0CC 0005702C 7F E3 FB 78 */ mr r3, r31
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/* 8005A0D0 00057030 48 2B B8 61 */ bl Free__7CMemoryFPCv
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lbl_8005A0D4:
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/* 8005A0D4 00057034 80 01 00 14 */ lwz r0, 0x14(r1)
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/* 8005A0D8 00057038 7F E3 FB 78 */ mr r3, r31
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/* 8005A0DC 0005703C 83 E1 00 0C */ lwz r31, 0xc(r1)
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/* 8005A0E0 00057040 7C 08 03 A6 */ mtlr r0
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/* 8005A0E4 00057044 38 21 00 10 */ addi r1, r1, 0x10
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/* 8005A0E8 00057048 4E 80 00 20 */ blr
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.global __ct__28CArchMsgParmControllerStatusFsb
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__ct__28CArchMsgParmControllerStatusFsb:
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/* 8005A0EC 0005704C 3C E0 80 3E */ lis r7, __vt__24IArchitectureMessageParm@ha
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/* 8005A0F0 00057050 3C C0 80 3E */ lis r6, lbl_803DA098@ha
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/* 8005A0F4 00057054 38 E7 8E 9C */ addi r7, r7, __vt__24IArchitectureMessageParm@l
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/* 8005A0F8 00057058 90 E3 00 00 */ stw r7, 0(r3)
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/* 8005A0FC 0005705C 38 06 A0 98 */ addi r0, r6, lbl_803DA098@l
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/* 8005A100 00057060 90 03 00 00 */ stw r0, 0(r3)
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/* 8005A104 00057064 B0 83 00 04 */ sth r4, 4(r3)
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/* 8005A108 00057068 98 A3 00 06 */ stb r5, 6(r3)
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/* 8005A10C 0005706C 4E 80 00 20 */ blr
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