.include "macros.inc"

.section .sbss
.balign 4
.global lbl_805A99D8
lbl_805A99D8:
	.skip 0x8

.section .text, "ax"

.global __close_console
__close_console:
/* 80391274 0038E1D4  38 60 00 00 */	li r3, 0
/* 80391278 0038E1D8  4E 80 00 20 */	blr 

.global __write_console
__write_console:
/* 8039127C 0038E1DC  94 21 FF E0 */	stwu r1, -0x20(r1)
/* 80391280 0038E1E0  7C 08 02 A6 */	mflr r0
/* 80391284 0038E1E4  90 01 00 24 */	stw r0, 0x24(r1)
/* 80391288 0038E1E8  93 E1 00 1C */	stw r31, 0x1c(r1)
/* 8039128C 0038E1EC  7C DF 33 78 */	mr r31, r6
/* 80391290 0038E1F0  93 C1 00 18 */	stw r30, 0x18(r1)
/* 80391294 0038E1F4  7C BE 2B 78 */	mr r30, r5
/* 80391298 0038E1F8  93 A1 00 14 */	stw r29, 0x14(r1)
/* 8039129C 0038E1FC  7C 9D 23 78 */	mr r29, r4
/* 803912A0 0038E200  93 81 00 10 */	stw r28, 0x10(r1)
/* 803912A4 0038E204  7C 7C 1B 78 */	mr r28, r3
/* 803912A8 0038E208  38 60 00 00 */	li r3, 0
/* 803912AC 0038E20C  80 0D AE 18 */	lwz r0, lbl_805A99D8@sda21(r13)
/* 803912B0 0038E210  2C 00 00 00 */	cmpwi r0, 0
/* 803912B4 0038E214  40 82 00 20 */	bne lbl_803912D4
/* 803912B8 0038E218  3C 60 00 01 */	lis r3, 0x0000E100@ha
/* 803912BC 0038E21C  38 63 E1 00 */	addi r3, r3, 0x0000E100@l
/* 803912C0 0038E220  48 03 06 31 */	bl InitializeUART
/* 803912C4 0038E224  2C 03 00 00 */	cmpwi r3, 0
/* 803912C8 0038E228  40 82 00 0C */	bne lbl_803912D4
/* 803912CC 0038E22C  38 00 00 01 */	li r0, 1
/* 803912D0 0038E230  90 0D AE 18 */	stw r0, lbl_805A99D8@sda21(r13)
lbl_803912D4:
/* 803912D4 0038E234  2C 03 00 00 */	cmpwi r3, 0
/* 803912D8 0038E238  41 82 00 0C */	beq lbl_803912E4
/* 803912DC 0038E23C  38 60 00 01 */	li r3, 1
/* 803912E0 0038E240  48 00 00 40 */	b lbl_80391320
lbl_803912E4:
/* 803912E4 0038E244  80 9E 00 00 */	lwz r4, 0(r30)
/* 803912E8 0038E248  7F A3 EB 78 */	mr r3, r29
/* 803912EC 0038E24C  48 03 06 75 */	bl WriteUARTN
/* 803912F0 0038E250  2C 03 00 00 */	cmpwi r3, 0
/* 803912F4 0038E254  41 82 00 14 */	beq lbl_80391308
/* 803912F8 0038E258  38 00 00 00 */	li r0, 0
/* 803912FC 0038E25C  38 60 00 01 */	li r3, 1
/* 80391300 0038E260  90 1E 00 00 */	stw r0, 0(r30)
/* 80391304 0038E264  48 00 00 1C */	b lbl_80391320
lbl_80391308:
/* 80391308 0038E268  7F 83 E3 78 */	mr r3, r28
/* 8039130C 0038E26C  7F A4 EB 78 */	mr r4, r29
/* 80391310 0038E270  7F C5 F3 78 */	mr r5, r30
/* 80391314 0038E274  7F E6 FB 78 */	mr r6, r31
/* 80391318 0038E278  4B C7 23 39 */	bl __TRK_write_console
/* 8039131C 0038E27C  38 60 00 00 */	li r3, 0
lbl_80391320:
/* 80391320 0038E280  80 01 00 24 */	lwz r0, 0x24(r1)
/* 80391324 0038E284  83 E1 00 1C */	lwz r31, 0x1c(r1)
/* 80391328 0038E288  83 C1 00 18 */	lwz r30, 0x18(r1)
/* 8039132C 0038E28C  83 A1 00 14 */	lwz r29, 0x14(r1)
/* 80391330 0038E290  83 81 00 10 */	lwz r28, 0x10(r1)
/* 80391334 0038E294  7C 08 03 A6 */	mtlr r0
/* 80391338 0038E298  38 21 00 20 */	addi r1, r1, 0x20
/* 8039133C 0038E29C  4E 80 00 20 */	blr