.include "macros.inc" .section .text, "ax" # 0x80003640 - 0x803CB1C0 .global GetAllocatedAmount__15CCircularBufferCFv GetAllocatedAmount__15CCircularBufferCFv: /* 80315660 003125C0 80 A3 00 14 */ lwz r5, 0x14(r3) /* 80315664 003125C4 80 83 00 0C */ lwz r4, 0xc(r3) /* 80315668 003125C8 80 03 00 10 */ lwz r0, 0x10(r3) /* 8031566C 003125CC 2C 05 FF FF */ cmpwi r5, -1 /* 80315670 003125D0 7C 84 00 50 */ subf r4, r4, r0 /* 80315674 003125D4 41 82 00 10 */ beq lbl_80315684 /* 80315678 003125D8 80 03 00 08 */ lwz r0, 8(r3) /* 8031567C 003125DC 7C 05 00 50 */ subf r0, r5, r0 /* 80315680 003125E0 7C 84 02 14 */ add r4, r4, r0 lbl_80315684: /* 80315684 003125E4 7C 83 23 78 */ mr r3, r4 /* 80315688 003125E8 4E 80 00 20 */ blr .global Free__15CCircularBufferFPvi Free__15CCircularBufferFPvi: /* 8031568C 003125EC 80 C3 00 14 */ lwz r6, 0x14(r3) /* 80315690 003125F0 2C 06 FF FF */ cmpwi r6, -1 /* 80315694 003125F4 40 81 00 2C */ ble lbl_803156C0 /* 80315698 003125F8 80 03 00 04 */ lwz r0, 4(r3) /* 8031569C 003125FC 7C 04 00 40 */ cmplw r4, r0 /* 803156A0 00312600 40 82 00 14 */ bne lbl_803156B4 /* 803156A4 00312604 38 00 FF FF */ li r0, -1 /* 803156A8 00312608 90 03 00 14 */ stw r0, 0x14(r3) /* 803156AC 0031260C 90 A3 00 0C */ stw r5, 0xc(r3) /* 803156B0 00312610 48 00 00 1C */ b lbl_803156CC lbl_803156B4: /* 803156B4 00312614 7C 06 2A 14 */ add r0, r6, r5 /* 803156B8 00312618 90 03 00 14 */ stw r0, 0x14(r3) /* 803156BC 0031261C 48 00 00 10 */ b lbl_803156CC lbl_803156C0: /* 803156C0 00312620 80 03 00 0C */ lwz r0, 0xc(r3) /* 803156C4 00312624 7C 00 2A 14 */ add r0, r0, r5 /* 803156C8 00312628 90 03 00 0C */ stw r0, 0xc(r3) lbl_803156CC: /* 803156CC 0031262C 80 03 00 14 */ lwz r0, 0x14(r3) /* 803156D0 00312630 2C 00 FF FF */ cmpwi r0, -1 /* 803156D4 00312634 4C 82 00 20 */ bnelr /* 803156D8 00312638 80 83 00 0C */ lwz r4, 0xc(r3) /* 803156DC 0031263C 80 03 00 10 */ lwz r0, 0x10(r3) /* 803156E0 00312640 7C 04 00 00 */ cmpw r4, r0 /* 803156E4 00312644 4C 82 00 20 */ bnelr /* 803156E8 00312648 38 00 00 00 */ li r0, 0 /* 803156EC 0031264C 90 03 00 10 */ stw r0, 0x10(r3) /* 803156F0 00312650 90 03 00 0C */ stw r0, 0xc(r3) /* 803156F4 00312654 4E 80 00 20 */ blr .global Alloc__15CCircularBufferFi Alloc__15CCircularBufferFi: /* 803156F8 00312658 94 21 FF F0 */ stwu r1, -0x10(r1) /* 803156FC 0031265C 7C 08 02 A6 */ mflr r0 /* 80315700 00312660 90 01 00 14 */ stw r0, 0x14(r1) /* 80315704 00312664 93 E1 00 0C */ stw r31, 0xc(r1) /* 80315708 00312668 7C 9F 23 78 */ mr r31, r4 /* 8031570C 0031266C 93 C1 00 08 */ stw r30, 8(r1) /* 80315710 00312670 7C 7E 1B 78 */ mr r30, r3 /* 80315714 00312674 80 83 00 10 */ lwz r4, 0x10(r3) /* 80315718 00312678 80 03 00 08 */ lwz r0, 8(r3) /* 8031571C 0031267C 7C 04 00 50 */ subf r0, r4, r0 /* 80315720 00312680 7C 00 F8 00 */ cmpw r0, r31 /* 80315724 00312684 41 80 00 2C */ blt lbl_80315750 /* 80315728 00312688 7F E5 FB 78 */ mr r5, r31 /* 8031572C 0031268C 48 00 00 81 */ bl IsWrappedMemory__15CCircularBufferFii /* 80315730 00312690 54 60 06 3F */ clrlwi. r0, r3, 0x18 /* 80315734 00312694 40 82 00 1C */ bne lbl_80315750 /* 80315738 00312698 80 7E 00 10 */ lwz r3, 0x10(r30) /* 8031573C 0031269C 80 9E 00 04 */ lwz r4, 4(r30) /* 80315740 003126A0 7C 03 FA 14 */ add r0, r3, r31 /* 80315744 003126A4 90 1E 00 10 */ stw r0, 0x10(r30) /* 80315748 003126A8 7C 64 1A 14 */ add r3, r4, r3 /* 8031574C 003126AC 48 00 00 48 */ b lbl_80315794 lbl_80315750: /* 80315750 003126B0 80 1E 00 0C */ lwz r0, 0xc(r30) /* 80315754 003126B4 7C 00 F8 00 */ cmpw r0, r31 /* 80315758 003126B8 41 80 00 38 */ blt lbl_80315790 /* 8031575C 003126BC 7F C3 F3 78 */ mr r3, r30 /* 80315760 003126C0 7F E5 FB 78 */ mr r5, r31 /* 80315764 003126C4 38 80 00 00 */ li r4, 0 /* 80315768 003126C8 48 00 00 45 */ bl IsWrappedMemory__15CCircularBufferFii /* 8031576C 003126CC 54 60 06 3F */ clrlwi. r0, r3, 0x18 /* 80315770 003126D0 40 82 00 20 */ bne lbl_80315790 /* 80315774 003126D4 80 7E 00 0C */ lwz r3, 0xc(r30) /* 80315778 003126D8 38 00 00 00 */ li r0, 0 /* 8031577C 003126DC 90 1E 00 0C */ stw r0, 0xc(r30) /* 80315780 003126E0 93 FE 00 10 */ stw r31, 0x10(r30) /* 80315784 003126E4 90 7E 00 14 */ stw r3, 0x14(r30) /* 80315788 003126E8 80 7E 00 04 */ lwz r3, 4(r30) /* 8031578C 003126EC 48 00 00 08 */ b lbl_80315794 lbl_80315790: /* 80315790 003126F0 38 60 00 00 */ li r3, 0 lbl_80315794: /* 80315794 003126F4 80 01 00 14 */ lwz r0, 0x14(r1) /* 80315798 003126F8 83 E1 00 0C */ lwz r31, 0xc(r1) /* 8031579C 003126FC 83 C1 00 08 */ lwz r30, 8(r1) /* 803157A0 00312700 7C 08 03 A6 */ mtlr r0 /* 803157A4 00312704 38 21 00 10 */ addi r1, r1, 0x10 /* 803157A8 00312708 4E 80 00 20 */ blr .global IsWrappedMemory__15CCircularBufferFii IsWrappedMemory__15CCircularBufferFii: /* 803157AC 0031270C 80 63 00 14 */ lwz r3, 0x14(r3) /* 803157B0 00312710 2C 03 FF FF */ cmpwi r3, -1 /* 803157B4 00312714 40 81 00 20 */ ble lbl_803157D4 /* 803157B8 00312718 7C 03 20 00 */ cmpw r3, r4 /* 803157BC 0031271C 41 80 00 18 */ blt lbl_803157D4 /* 803157C0 00312720 7C 04 2A 14 */ add r0, r4, r5 /* 803157C4 00312724 7C 03 00 00 */ cmpw r3, r0 /* 803157C8 00312728 40 80 00 0C */ bge lbl_803157D4 /* 803157CC 0031272C 38 60 00 01 */ li r3, 1 /* 803157D0 00312730 4E 80 00 20 */ blr lbl_803157D4: /* 803157D4 00312734 38 60 00 00 */ li r3, 0 /* 803157D8 00312738 4E 80 00 20 */ blr .global __ct__15CCircularBufferFPviQ215CCircularBuffer10EOwnership __ct__15CCircularBufferFPviQ215CCircularBuffer10EOwnership: /* 803157DC 0031273C 7C 04 00 D0 */ neg r0, r4 /* 803157E0 00312740 38 E0 00 00 */ li r7, 0 /* 803157E4 00312744 7C 00 23 78 */ or r0, r0, r4 /* 803157E8 00312748 2C 06 00 01 */ cmpwi r6, 1 /* 803157EC 0031274C 54 00 0F FE */ srwi r0, r0, 0x1f /* 803157F0 00312750 98 03 00 00 */ stb r0, 0(r3) /* 803157F4 00312754 38 00 FF FF */ li r0, -1 /* 803157F8 00312758 90 83 00 04 */ stw r4, 4(r3) /* 803157FC 0031275C 90 A3 00 08 */ stw r5, 8(r3) /* 80315800 00312760 90 E3 00 0C */ stw r7, 0xc(r3) /* 80315804 00312764 90 E3 00 10 */ stw r7, 0x10(r3) /* 80315808 00312768 90 03 00 14 */ stw r0, 0x14(r3) /* 8031580C 0031276C 4C 82 00 20 */ bnelr /* 80315810 00312770 98 E3 00 00 */ stb r7, 0(r3) /* 80315814 00312774 4E 80 00 20 */ blr