mirror of https://git.wuffs.org/MWCC
651 lines
24 KiB
C
651 lines
24 KiB
C
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#include "compiler/Scheduler.h"
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#include "compiler/PCode.h"
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#include "compiler/PCodeInfo.h"
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// https://www.nxp.com/docs/en/reference-manual/MPC603EUM.pdf
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typedef enum Stage {
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BPU, // Branch Prediction Unit
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IU, // Integer Unit
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LSU1, // Load/Store Unit
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LSU2,
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FPU1, // Floating Point Unit
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FPU2,
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FPU3,
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SRU, // System Register Unit
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NumStages
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} Stage;
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static struct {
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// the instruction currently in this pipeline stage
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PCode *instr;
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// how many cycles are left for this instruction to finish
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int remaining;
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} pipeline[NumStages];
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enum {
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MaxEntries = 5
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};
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static struct {
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// how many entries remain unused in the queue
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unsigned int free;
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// how many entries are currently used in the queue
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unsigned int used;
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// the index of the next instruction that will be retired
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unsigned int nextToRetire;
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// the index of the next free slot that will be used when an instruction is dispatched
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unsigned int nextFreeSlot;
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// circular array of entries in the completion queue
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struct {
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PCode *instr;
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int completed;
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} entries[MaxEntries];
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} completionbuffers;
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static struct {
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// the initial stage for this instruction
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Stage stage;
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// the total amount of cycles required by this instruction
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char latency;
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// how long it takes to finish each stage
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char cycles[3];
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// does this instruction serialise?
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char serializes;
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} instruction_timing[OPCODE_MAX] = {
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BPU, 0, 0, 0, 0, 1, // PC_B
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BPU, 0, 0, 0, 0, 1, // PC_BL
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BPU, 0, 0, 0, 0, 1, // PC_BC
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BPU, 0, 0, 0, 0, 1, // PC_BCLR
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BPU, 0, 0, 0, 0, 1, // PC_BCCTR
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BPU, 0, 0, 0, 0, 1, // PC_BT
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BPU, 0, 0, 0, 0, 1, // PC_BTLR
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BPU, 0, 0, 0, 0, 1, // PC_BTCTR
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BPU, 0, 0, 0, 0, 1, // PC_BF
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BPU, 0, 0, 0, 0, 1, // PC_BFLR
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BPU, 0, 0, 0, 0, 1, // PC_BFCTR
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BPU, 0, 0, 0, 0, 1, // PC_BDNZ
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BPU, 0, 0, 0, 0, 1, // PC_BDNZT
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BPU, 0, 0, 0, 0, 1, // PC_BDNZF
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BPU, 0, 0, 0, 0, 1, // PC_BDZ
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BPU, 0, 0, 0, 0, 1, // PC_BDZT
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BPU, 0, 0, 0, 0, 1, // PC_BDZF
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BPU, 0, 0, 0, 0, 1, // PC_BLR
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BPU, 0, 0, 0, 0, 1, // PC_BCTR
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BPU, 0, 0, 0, 0, 1, // PC_BCTRL
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BPU, 0, 0, 0, 0, 1, // PC_BLRL
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LSU1, 2, 1, 1, 0, 0, // PC_LBZ
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LSU1, 2, 1, 1, 0, 0, // PC_LBZU
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LSU1, 2, 1, 1, 0, 0, // PC_LBZX
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LSU1, 2, 1, 1, 0, 0, // PC_LBZUX
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LSU1, 2, 1, 1, 0, 0, // PC_LHZ
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LSU1, 2, 1, 1, 0, 0, // PC_LHZU
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LSU1, 2, 1, 1, 0, 0, // PC_LHZX
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LSU1, 2, 1, 1, 0, 0, // PC_LHZUX
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LSU1, 2, 1, 1, 0, 0, // PC_LHA
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LSU1, 2, 1, 1, 0, 0, // PC_LHAU
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LSU1, 2, 1, 1, 0, 0, // PC_LHAX
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LSU1, 2, 1, 1, 0, 0, // PC_LHAUX
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LSU1, 2, 1, 1, 0, 0, // PC_LHBRX
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LSU1, 2, 1, 1, 0, 0, // PC_LWZ
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LSU1, 2, 1, 1, 0, 0, // PC_LWZU
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LSU1, 2, 1, 1, 0, 0, // PC_LWZX
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LSU1, 2, 1, 1, 0, 0, // PC_LWZUX
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LSU1, 2, 1, 1, 0, 0, // PC_LWBRX
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LSU1, 2, 1, 1, 0, 0, // PC_LMW
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LSU1, 2, 1, 1, 0, 0, // PC_STB
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LSU1, 2, 1, 1, 0, 0, // PC_STBU
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LSU1, 2, 1, 1, 0, 0, // PC_STBX
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LSU1, 2, 1, 1, 0, 0, // PC_STBUX
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LSU1, 2, 1, 1, 0, 0, // PC_STH
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LSU1, 2, 1, 1, 0, 0, // PC_STHU
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LSU1, 2, 1, 1, 0, 0, // PC_STHX
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LSU1, 2, 1, 1, 0, 0, // PC_STHUX
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LSU1, 2, 1, 1, 0, 0, // PC_STHBRX
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LSU1, 2, 1, 1, 0, 0, // PC_STW
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LSU1, 2, 1, 1, 0, 0, // PC_STWU
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LSU1, 2, 1, 1, 0, 0, // PC_STWX
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LSU1, 2, 1, 1, 0, 0, // PC_STWUX
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LSU1, 2, 1, 1, 0, 0, // PC_STWBRX
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LSU1, 2, 1, 1, 0, 0, // PC_STMW
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LSU1, 2, 1, 1, 0, 0, // PC_DCBF
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LSU1, 2, 1, 1, 0, 0, // PC_DCBST
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LSU1, 2, 1, 1, 0, 0, // PC_DCBT
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LSU1, 2, 1, 1, 0, 0, // PC_DCBTST
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LSU1, 2, 1, 1, 0, 0, // PC_DCBZ
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IU, 1, 1, 0, 0, 0, // PC_ADD
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IU, 1, 1, 0, 0, 0, // PC_ADDC
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IU, 1, 1, 0, 0, 0, // PC_ADDE
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IU, 1, 1, 0, 0, 0, // PC_ADDI
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IU, 1, 1, 0, 0, 0, // PC_ADDIC
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IU, 1, 1, 0, 0, 0, // PC_ADDICR
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IU, 1, 1, 0, 0, 0, // PC_ADDIS
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IU, 1, 1, 0, 0, 0, // PC_ADDME
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IU, 1, 1, 0, 0, 0, // PC_ADDZE
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IU, 37, 37, 0, 0, 0, // PC_DIVW
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IU, 37, 37, 0, 0, 0, // PC_DIVWU
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IU, 5, 5, 0, 0, 0, // PC_MULHW
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IU, 5, 5, 0, 0, 0, // PC_MULHWU
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IU, 3, 3, 0, 0, 0, // PC_MULLI
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IU, 5, 5, 0, 0, 0, // PC_MULLW
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IU, 1, 1, 0, 0, 0, // PC_NEG
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IU, 1, 1, 0, 0, 0, // PC_SUBF
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IU, 1, 1, 0, 0, 0, // PC_SUBFC
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IU, 1, 1, 0, 0, 0, // PC_SUBFE
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IU, 1, 1, 0, 0, 0, // PC_SUBFIC
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IU, 1, 1, 0, 0, 0, // PC_SUBFME
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IU, 1, 1, 0, 0, 0, // PC_SUBFZE
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IU, 3, 1, 0, 0, 0, // PC_CMPI
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IU, 3, 1, 0, 0, 0, // PC_CMP
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IU, 3, 1, 0, 0, 0, // PC_CMPLI
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IU, 3, 1, 0, 0, 0, // PC_CMPL
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IU, 1, 1, 0, 0, 0, // PC_ANDI
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IU, 1, 1, 0, 0, 0, // PC_ANDIS
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IU, 1, 1, 0, 0, 0, // PC_ORI
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IU, 1, 1, 0, 0, 0, // PC_ORIS
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IU, 1, 1, 0, 0, 0, // PC_XORI
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IU, 1, 1, 0, 0, 0, // PC_XORIS
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IU, 1, 1, 0, 0, 0, // PC_AND
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IU, 1, 1, 0, 0, 0, // PC_OR
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IU, 1, 1, 0, 0, 0, // PC_XOR
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IU, 1, 1, 0, 0, 0, // PC_NAND
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IU, 1, 1, 0, 0, 0, // PC_NOR
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IU, 1, 1, 0, 0, 0, // PC_EQV
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IU, 1, 1, 0, 0, 0, // PC_ANDC
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IU, 1, 1, 0, 0, 0, // PC_ORC
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IU, 1, 1, 0, 0, 0, // PC_EXTSB
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IU, 1, 1, 0, 0, 0, // PC_EXTSH
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IU, 1, 1, 0, 0, 0, // PC_CNTLZW
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IU, 1, 1, 0, 0, 0, // PC_RLWINM
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IU, 1, 1, 0, 0, 0, // PC_RLWNM
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IU, 1, 1, 0, 0, 0, // PC_RLWIMI
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IU, 1, 1, 0, 0, 0, // PC_SLW
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IU, 1, 1, 0, 0, 0, // PC_SRW
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IU, 1, 1, 0, 0, 0, // PC_SRAWI
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IU, 1, 1, 0, 0, 0, // PC_SRAW
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SRU, 1, 1, 0, 0, 0, // PC_CRAND
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SRU, 1, 1, 0, 0, 0, // PC_CRANDC
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SRU, 1, 1, 0, 0, 0, // PC_CREQV
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SRU, 1, 1, 0, 0, 0, // PC_CRNAND
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SRU, 1, 1, 0, 0, 0, // PC_CRNOR
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SRU, 1, 1, 0, 0, 0, // PC_CROR
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SRU, 1, 1, 0, 0, 0, // PC_CRORC
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SRU, 1, 1, 0, 0, 0, // PC_CRXOR
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SRU, 1, 1, 0, 0, 0, // PC_MCRF
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SRU, 2, 2, 0, 0, 0, // PC_MTXER
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SRU, 2, 2, 0, 0, 0, // PC_MTCTR
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SRU, 2, 2, 0, 0, 0, // PC_MTLR
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SRU, 1, 1, 0, 0, 0, // PC_MTCRF
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SRU, 1, 1, 0, 0, 1, // PC_MTMSR
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SRU, 1, 1, 0, 0, 1, // PC_MTSPR
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SRU, 1, 1, 0, 0, 1, // PC_MFMSR
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SRU, 1, 1, 0, 0, 1, // PC_MFSPR
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SRU, 1, 1, 0, 0, 0, // PC_MFXER
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SRU, 1, 1, 0, 0, 0, // PC_MFCTR
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SRU, 1, 1, 0, 0, 0, // PC_MFLR
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SRU, 1, 1, 0, 0, 0, // PC_MFCR
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FPU1, 3, 1, 1, 1, 0, // PC_MFFS
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FPU1, 3, 1, 1, 1, 0, // PC_MTFSF
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SRU, 1, 1, 0, 0, 1, // PC_EIEIO
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SRU, 1, 1, 0, 0, 1, // PC_ISYNC
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SRU, 1, 1, 0, 0, 1, // PC_SYNC
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SRU, 1, 1, 0, 0, 1, // PC_RFI
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IU, 1, 1, 0, 0, 0, // PC_LI
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IU, 1, 1, 0, 0, 0, // PC_LIS
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IU, 1, 1, 0, 0, 0, // PC_MR
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IU, 1, 1, 0, 0, 0, // PC_NOP
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IU, 1, 1, 0, 0, 0, // PC_NOT
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LSU1, 2, 1, 1, 0, 0, // PC_LFS
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LSU1, 2, 1, 1, 0, 0, // PC_LFSU
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LSU1, 2, 1, 1, 0, 0, // PC_LFSX
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LSU1, 2, 1, 1, 0, 0, // PC_LFSUX
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LSU1, 2, 1, 1, 0, 0, // PC_LFD
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LSU1, 2, 1, 1, 0, 0, // PC_LFDU
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LSU1, 2, 1, 1, 0, 0, // PC_LFDX
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LSU1, 2, 1, 1, 0, 0, // PC_LFDUX
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LSU1, 2, 1, 1, 0, 0, // PC_STFS
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LSU1, 2, 1, 1, 0, 0, // PC_STFSU
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LSU1, 2, 1, 1, 0, 0, // PC_STFSX
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LSU1, 2, 1, 1, 0, 0, // PC_STFSUX
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LSU1, 2, 1, 1, 0, 0, // PC_STFD
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LSU1, 2, 1, 1, 0, 0, // PC_STFDU
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LSU1, 2, 1, 1, 0, 0, // PC_STFDX
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LSU1, 2, 1, 1, 0, 0, // PC_STFDUX
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FPU1, 3, 1, 1, 1, 0, // PC_FMR
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FPU1, 3, 1, 1, 1, 0, // PC_FABS
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FPU1, 3, 1, 1, 1, 0, // PC_FNEG
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FPU1, 3, 1, 1, 1, 0, // PC_FNABS
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FPU1, 3, 1, 1, 1, 0, // PC_FADD
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FPU1, 3, 1, 1, 1, 0, // PC_FADDS
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FPU1, 3, 1, 1, 1, 0, // PC_FSUB
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FPU1, 3, 1, 1, 1, 0, // PC_FSUBS
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FPU1, 4, 2, 1, 1, 0, // PC_FMUL
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FPU1, 3, 1, 1, 1, 0, // PC_FMULS
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FPU1, 33, 33, 0, 0, 0, // PC_FDIV
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FPU1, 18, 18, 0, 0, 0, // PC_FDIVS
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FPU1, 4, 2, 1, 1, 0, // PC_FMADD
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FPU1, 3, 1, 1, 1, 0, // PC_FMADDS
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FPU1, 4, 2, 1, 1, 0, // PC_FMSUB
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FPU1, 3, 1, 1, 1, 0, // PC_FMSUBS
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FPU1, 4, 2, 1, 1, 0, // PC_FNMADD
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FPU1, 3, 1, 1, 1, 0, // PC_FNMADDS
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FPU1, 4, 2, 1, 1, 0, // PC_FNMSUB
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FPU1, 3, 1, 1, 1, 0, // PC_FNMSUBS
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FPU1, 18, 18, 0, 0, 0, // PC_FRES
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FPU1, 3, 1, 1, 1, 0, // PC_FRSQRTE
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FPU1, 3, 1, 1, 1, 0, // PC_FSEL
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FPU1, 3, 1, 1, 1, 0, // PC_FRSP
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FPU1, 3, 1, 1, 1, 0, // PC_FCTIW
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FPU1, 3, 1, 1, 1, 0, // PC_FCTIWZ
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FPU1, 5, 1, 1, 1, 0, // PC_FCMPU
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FPU1, 5, 1, 1, 1, 0, // PC_FCMPO
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LSU1, 1, 1, 0, 0, 0, // PC_LWARX
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LSU1, 1, 1, 0, 0, 0, // PC_LSWI
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LSU1, 1, 1, 0, 0, 0, // PC_LSWX
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LSU1, 1, 1, 0, 0, 0, // PC_STFIWX
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LSU1, 1, 1, 0, 0, 0, // PC_STSWI
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LSU1, 1, 1, 0, 0, 0, // PC_STSWX
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LSU1, 1, 1, 0, 0, 0, // PC_STWCX
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IU, 1, 1, 0, 0, 1, // PC_ECIWX
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IU, 1, 1, 0, 0, 1, // PC_ECOWX
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IU, 1, 1, 0, 0, 0, // PC_DCBI
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IU, 1, 1, 0, 0, 0, // PC_ICBI
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IU, 1, 1, 0, 0, 0, // PC_MCRFS
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IU, 1, 1, 0, 0, 0, // PC_MCRXR
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IU, 1, 1, 0, 0, 0, // PC_MFTB
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IU, 1, 1, 0, 0, 0, // PC_MFSR
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IU, 1, 1, 0, 0, 0, // PC_MTSR
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IU, 1, 1, 0, 0, 0, // PC_MFSRIN
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IU, 1, 1, 0, 0, 0, // PC_MTSRIN
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IU, 1, 1, 0, 0, 0, // PC_MTFSB0
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IU, 1, 1, 0, 0, 0, // PC_MTFSB1
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IU, 1, 1, 0, 0, 0, // PC_MTFSFI
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IU, 1, 1, 0, 0, 1, // PC_SC
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FPU1, 1, 1, 0, 0, 0, // PC_FSQRT
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FPU1, 1, 1, 0, 0, 0, // PC_FSQRTS
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IU, 1, 1, 0, 0, 0, // PC_TLBIA
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IU, 1, 1, 0, 0, 0, // PC_TLBIE
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IU, 1, 1, 0, 0, 0, // PC_TLBLD
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|
IU, 1, 1, 0, 0, 0, // PC_TLBLI
|
||
|
|
IU, 1, 1, 0, 0, 0, // PC_TLBSYNC
|
||
|
|
IU, 1, 1, 0, 0, 1, // PC_TW
|
||
|
|
IU, 1, 1, 0, 0, 1, // PC_TRAP
|
||
|
|
IU, 1, 1, 0, 0, 1, // PC_TWI
|
||
|
|
IU, 1, 1, 0, 0, 1, // PC_OPWORD
|
||
|
|
IU, 1, 1, 0, 0, 0, // PC_MFROM
|
||
|
|
IU, 1, 1, 0, 0, 1, // PC_DSA
|
||
|
|
IU, 1, 1, 0, 0, 1, // PC_ESA
|
||
|
|
IU, 0, 0, 0, 0, 0, // PC_DCCCI
|
||
|
|
IU, 0, 0, 0, 0, 0, // PC_DCREAD
|
||
|
|
IU, 0, 0, 0, 0, 0, // PC_ICBT
|
||
|
|
IU, 0, 0, 0, 0, 0, // PC_ICCCI
|
||
|
|
IU, 0, 0, 0, 0, 0, // PC_ICREAD
|
||
|
|
IU, 0, 0, 0, 0, 0, // PC_RFCI
|
||
|
|
IU, 0, 0, 0, 0, 0, // PC_TLBRE
|
||
|
|
IU, 0, 0, 0, 0, 0, // PC_TLBSX
|
||
|
|
IU, 0, 0, 0, 0, 0, // PC_TLBWE
|
||
|
|
IU, 0, 0, 0, 0, 0, // PC_WRTEE
|
||
|
|
IU, 0, 0, 0, 0, 0, // PC_WRTEEI
|
||
|
|
IU, 0, 0, 0, 0, 0, // PC_MFDCR
|
||
|
|
IU, 0, 0, 0, 0, 0, // PC_MTDCR
|
||
|
|
IU, 0, 0, 0, 0, 0, // PC_DCBA
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_DSS
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_DSSALL
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_DST
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_DSTT
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_DSTST
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_DSTSTT
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_LVEBX
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_LVEHX
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_LVEWX
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_LVSL
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_LVSR
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_LVX
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_LVXL
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_STVEBX
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_STVEHX
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_STVEWX
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_STVX
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_STVXL
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_MFVSCR
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_MTVSCR
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_VADDCUW
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_VADDFP
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_VADDSBS
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_VADDSHS
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_VADDSWS
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_VADDUBM
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_VADDUBS
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_VADDUHM
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_VADDUHS
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_VADDUWM
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_VADDUWS
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_VAND
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_VANDC
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_VAVGSB
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_VAVGSH
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_VAVGSW
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_VAVGUB
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_VAVGUH
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_VAVGUW
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_VCFSX
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_VCFUX
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_VCMPBFP
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_VCMPEQFP
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_VCMPEQUB
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_VCMPEQUH
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_VCMPEQUW
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_VCMPGEFP
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_VCMPGTFP
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_VCMPGTSB
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_VCMPGTSH
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_VCMPGTSW
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_VCMPGTUB
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_VCMPGTUH
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_VCMPGTUW
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_VCTSXS
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_VCTUXS
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_VEXPTEFP
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_VLOGEFP
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_VMAXFP
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_VMAXSB
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_VMAXSH
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_VMAXSW
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_VMAXUB
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_VMAXUH
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_VMAXUW
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_VMINFP
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_VMINSB
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_VMINSH
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_VMINSW
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_VMINUB
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_VMINUH
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_VMINUW
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_VMRGHB
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_VMRGHH
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_VMRGHW
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_VMRGLB
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_VMRGLH
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_VMRGLW
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_VMULESB
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_VMULESH
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_VMULEUB
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_VMULEUH
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_VMULOSB
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_VMULOSH
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_VMULOUB
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_VMULOUH
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_VNOR
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_VOR
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_VPKPX
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_VPKSHSS
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_VPKSHUS
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_VPKSWSS
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_VPKSWUS
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_VPKUHUM
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_VPKUHUS
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_VPKUWUM
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_VPKUWUS
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_VREFP
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_VRFIM
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_VRFIN
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_VRFIP
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_VRFIZ
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_VRLB
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_VRLH
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_VRLW
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_VRSQRTEFP
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_VSL
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_VSLB
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_VSLH
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_VSLO
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_VSLW
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_VSPLTB
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_VSPLTH
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_VSPLTW
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_VSPLTISB
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_VSPLTISH
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_VSPLTISW
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_VSR
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_VSRAB
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_VSRAH
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_VSRAW
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_VSRB
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_VSRH
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_VSRO
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_VSRW
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_VSUBCUW
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_VSUBFP
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_VSUBSBS
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_VSUBSHS
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_VSUBSWS
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_VSUBUBM
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_VSUBUBS
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_VSUBUHM
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_VSUBUHS
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_VSUBUWM
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_VSUBUWS
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_VSUMSWS
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_VSUM2SWS
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_VSUM4SBS
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_VSUM4SHS
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_VSUM4UBS
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_VUPKHPX
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_VUPKHSB
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_VUPKHSH
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_VUPKLPX
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_VUPKLSB
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_VUPKLSH
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_VXOR
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_VMADDFP
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_VMHADDSHS
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_VMHRADDSHS
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_VMLADDUHM
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_VMSUMMBM
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_VMSUMSHM
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_VMSUMSHS
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_VMSUMUBM
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_VMSUMUHM
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_VMSUMUHS
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_VNMSUBFP
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_VPERM
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_VSEL
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_VSLDOI
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_VMR
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_VMRP
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_SLE
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_SLEQ
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_SLIQ
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_SLLIQ
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_SLLQ
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_SLQ
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_SRAIQ
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_SRAQ
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_SRE
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_SREA
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_SREQ
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_SRIQ
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_SRLIQ
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_SRLQ
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_SRQ
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_MASKG
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_MASKIR
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_LSCBX
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_DIV
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_DIVS
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_DOZ
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_MUL
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_NABS
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_ABS
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_CLCS
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_DOZI
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_RLMI
|
||
|
|
BPU, 0, 0, 0, 0, 0, // PC_RRIB
|
||
|
|
};
|
||
|
|
|
||
|
|
static void advance(int firstStage, int oldStage, int newStage) {
|
||
|
|
PCode *instr = pipeline[oldStage].instr;
|
||
|
|
int cycles = instruction_timing[instr->op].cycles[newStage - firstStage];
|
||
|
|
pipeline[newStage].instr = instr;
|
||
|
|
pipeline[newStage].remaining = cycles;
|
||
|
|
pipeline[oldStage].instr = NULL;
|
||
|
|
}
|
||
|
|
|
||
|
|
static void assign_completion_buffer(PCode *instr) {
|
||
|
|
completionbuffers.used++;
|
||
|
|
completionbuffers.free--;
|
||
|
|
completionbuffers.entries[completionbuffers.nextFreeSlot].instr = instr;
|
||
|
|
completionbuffers.entries[completionbuffers.nextFreeSlot].completed = 0;
|
||
|
|
completionbuffers.nextFreeSlot = (completionbuffers.nextFreeSlot + 1) % MaxEntries;
|
||
|
|
}
|
||
|
|
|
||
|
|
static void complete_instruction(int stage) {
|
||
|
|
PCode *instr = pipeline[stage].instr;
|
||
|
|
int buf = 0;
|
||
|
|
while (buf < MaxEntries && completionbuffers.entries[buf].instr != instr)
|
||
|
|
buf++;
|
||
|
|
|
||
|
|
completionbuffers.entries[buf].completed = 1;
|
||
|
|
pipeline[stage].instr = NULL;
|
||
|
|
}
|
||
|
|
|
||
|
|
static void retire_instruction(void) {
|
||
|
|
completionbuffers.entries[completionbuffers.nextToRetire].instr = NULL;
|
||
|
|
completionbuffers.used--;
|
||
|
|
completionbuffers.free++;
|
||
|
|
completionbuffers.nextToRetire = (completionbuffers.nextToRetire + 1) % MaxEntries;
|
||
|
|
}
|
||
|
|
|
||
|
|
static int latency(PCode *instr) {
|
||
|
|
int cycles = instruction_timing[instr->op].latency;
|
||
|
|
if (PCODE_FLAG_SET_F(instr) & fRecordBit)
|
||
|
|
cycles += 2;
|
||
|
|
if (instr->op == PC_LMW || instr->op == PC_STMW)
|
||
|
|
cycles += instr->argCount - 2;
|
||
|
|
return cycles;
|
||
|
|
}
|
||
|
|
|
||
|
|
static void initialize(void) {
|
||
|
|
int stage;
|
||
|
|
int i;
|
||
|
|
|
||
|
|
for (stage = 0; stage < NumStages; stage++)
|
||
|
|
pipeline[stage].instr = NULL;
|
||
|
|
|
||
|
|
completionbuffers.free = MaxEntries;
|
||
|
|
completionbuffers.used = 0;
|
||
|
|
completionbuffers.nextToRetire = 0;
|
||
|
|
completionbuffers.nextFreeSlot = 0;
|
||
|
|
for (i = 0; i < MaxEntries; i++)
|
||
|
|
completionbuffers.entries[i].instr = NULL;
|
||
|
|
}
|
||
|
|
|
||
|
|
static int can_issue(PCode *instr) {
|
||
|
|
int stage;
|
||
|
|
|
||
|
|
if (completionbuffers.free == 0)
|
||
|
|
return 0;
|
||
|
|
|
||
|
|
stage = instruction_timing[instr->op].stage;
|
||
|
|
if (pipeline[stage].instr) {
|
||
|
|
if (stage == IU) {
|
||
|
|
switch (instr->op) {
|
||
|
|
case PC_ADD:
|
||
|
|
case PC_ADDC:
|
||
|
|
case PC_ADDI:
|
||
|
|
case PC_ADDIS:
|
||
|
|
case PC_CMPI:
|
||
|
|
case PC_CMP:
|
||
|
|
case PC_CMPLI:
|
||
|
|
case PC_CMPL:
|
||
|
|
if (is_dependent(instr, pipeline[IU].instr, RegClass_GPR))
|
||
|
|
return 0;
|
||
|
|
if (!pipeline[SRU].instr)
|
||
|
|
return 1;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
if ((instr->flags & fIsWrite) && pipeline[LSU2].instr && (pipeline[LSU2].instr->flags & fIsWrite))
|
||
|
|
return 0;
|
||
|
|
|
||
|
|
return 1;
|
||
|
|
}
|
||
|
|
|
||
|
|
static void issue(PCode *instr) {
|
||
|
|
int stage = instruction_timing[instr->op].stage;
|
||
|
|
int cycles = instruction_timing[instr->op].cycles[0];
|
||
|
|
if (stage == IU && pipeline[IU].instr)
|
||
|
|
stage = SRU;
|
||
|
|
assign_completion_buffer(instr);
|
||
|
|
pipeline[stage].instr = instr;
|
||
|
|
pipeline[stage].remaining = cycles;
|
||
|
|
}
|
||
|
|
|
||
|
|
static void advance_clock(void) {
|
||
|
|
int stage;
|
||
|
|
|
||
|
|
for (stage = 0; stage < NumStages; stage++) {
|
||
|
|
if (pipeline[stage].instr && pipeline[stage].remaining)
|
||
|
|
--pipeline[stage].remaining;
|
||
|
|
}
|
||
|
|
|
||
|
|
if (completionbuffers.used && completionbuffers.entries[completionbuffers.nextToRetire].completed) {
|
||
|
|
retire_instruction();
|
||
|
|
if (completionbuffers.used && completionbuffers.entries[completionbuffers.nextToRetire].completed) {
|
||
|
|
retire_instruction();
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
if (pipeline[IU].instr && pipeline[IU].remaining == 0)
|
||
|
|
complete_instruction(IU);
|
||
|
|
if (pipeline[LSU2].instr && pipeline[LSU2].remaining == 0)
|
||
|
|
complete_instruction(LSU2);
|
||
|
|
if (pipeline[FPU3].instr && pipeline[FPU3].remaining == 0)
|
||
|
|
complete_instruction(FPU3);
|
||
|
|
if (pipeline[SRU].instr && pipeline[SRU].remaining == 0)
|
||
|
|
complete_instruction(SRU);
|
||
|
|
if (pipeline[BPU].instr && pipeline[BPU].remaining == 0)
|
||
|
|
complete_instruction(BPU);
|
||
|
|
|
||
|
|
if (
|
||
|
|
pipeline[FPU1].instr &&
|
||
|
|
pipeline[FPU1].remaining == 0 &&
|
||
|
|
(pipeline[FPU1].instr->op == PC_FDIV || pipeline[FPU1].instr->op == PC_FDIVS)
|
||
|
|
)
|
||
|
|
complete_instruction(FPU1);
|
||
|
|
|
||
|
|
if (pipeline[FPU2].instr && pipeline[FPU2].remaining == 0 && !pipeline[FPU3].instr)
|
||
|
|
advance(FPU1, FPU2, FPU3);
|
||
|
|
if (pipeline[FPU1].instr && pipeline[FPU1].remaining == 0 && !pipeline[FPU2].instr)
|
||
|
|
advance(FPU1, FPU1, FPU2);
|
||
|
|
if (pipeline[LSU1].instr && pipeline[LSU1].remaining == 0 && !pipeline[LSU2].instr)
|
||
|
|
advance(LSU1, LSU1, LSU2);
|
||
|
|
}
|
||
|
|
|
||
|
|
static int serializes(PCode *instr) {
|
||
|
|
return instruction_timing[instr->op].serializes;
|
||
|
|
}
|
||
|
|
|
||
|
|
MachineInfo machine603e = {
|
||
|
|
2,
|
||
|
|
1,
|
||
|
|
0,
|
||
|
|
&latency,
|
||
|
|
&initialize,
|
||
|
|
&can_issue,
|
||
|
|
&issue,
|
||
|
|
&advance_clock,
|
||
|
|
&serializes,
|
||
|
|
&default_uses_vpermute_unit
|
||
|
|
};
|