2022-12-14 00:16:59 +00:00
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#include "compiler/SpillCode.h"
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#include "compiler/CError.h"
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#include "compiler/CMachine.h"
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#include "compiler/CParser.h"
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#include "compiler/CodeGen.h"
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#include "compiler/CompilerTools.h"
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#include "compiler/Coloring.h"
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#include "compiler/InterferenceGraph.h"
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#include "compiler/Operands.h"
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#include "compiler/PCode.h"
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#include "compiler/PCodeUtilities.h"
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#include "compiler/Registers.h"
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#include "compiler/RegisterInfo.h"
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#include "compiler/StackFrame.h"
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#include "compiler/objects.h"
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static int last_unused_vreg_before_spilling;
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static short rTEMP_for_VR_spill;
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void estimatespillcosts(void) {
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PCodeBlock *block;
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PCode *instr;
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IGNode *node;
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PCodeArg *op;
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int i;
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int weight;
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for (block = pcbasicblocks; block; block = block->nextBlock) {
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2023-01-15 12:14:05 +00:00
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if (copts.optimizesize)
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2022-12-14 00:16:59 +00:00
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weight = 1;
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else
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weight = block->loopWeight;
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for (instr = block->firstPCode; instr; instr = instr->nextPCode) {
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op = instr->args;
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i = instr->argCount;
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while (i--) {
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if (PC_OP_IS_READ_ANY_REGISTER(op, coloring_class)) {
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node = interferencegraph[op->data.reg.reg];
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2023-01-15 12:14:05 +00:00
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if (node->instr8 || copts.optimizesize)
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2022-12-14 00:16:59 +00:00
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node->spillCost += weight;
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else
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node->spillCost += weight * 2;
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}
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op++;
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}
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op = instr->args;
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i = instr->argCount;
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while (i--) {
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if (PC_OP_IS_WRITE_ANY_REGISTER(op, coloring_class)) {
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node = interferencegraph[op->data.reg.reg];
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2023-01-11 22:29:53 +00:00
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if (node->instr8 || (instr->flags & fIsArgInit))
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2022-12-14 00:16:59 +00:00
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node->spillCost -= weight;
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else
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node->spillCost += weight;
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}
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op++;
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}
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}
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}
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}
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static Object *makespilltemporary(Type *type) {
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Object *obj = lalloc(sizeof(Object));
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memclrw(obj, sizeof(Object));
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obj->otype = OT_OBJECT;
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obj->access = ACCESSPUBLIC;
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obj->datatype = DLOCAL;
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obj->type = type;
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obj->name = CParser_GetUniqueName();
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obj->u.var.info = CodeGen_GetNewVarInfo();
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obj->u.var.uid = 0;
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return obj;
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}
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static PCode *rematerialize_spilled_register(short reg, IGNode *node) {
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PCode *instr = copypcode(node->instr8);
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2022-12-29 12:32:55 +00:00
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CError_ASSERT(128, instr->args[0].kind == PCOp_REGISTER);
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2022-12-14 00:16:59 +00:00
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instr->args[0].data.reg.reg = reg;
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return instr;
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}
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static void insert_load_spilled_register(PCode *instr, short reg, IGNode *node) {
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Type *type;
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Opcode opcode;
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Object *object;
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PCode *newInstr;
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PCode *newInstr2;
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SInt32 offset;
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Operand operand;
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type = node->spillTemporary->type;
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switch (coloring_class) {
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case RegClass_CRFIELD:
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case RegClass_GPR:
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switch (type->size) {
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case 1:
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opcode = PC_LBZ;
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break;
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case 2:
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opcode = is_unsigned(type) ? PC_LHZ : PC_LHA;
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break;
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case 4:
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opcode = PC_LWZ;
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break;
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case 8:
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opcode = PC_LWZ;
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break;
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default:
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2022-12-29 12:32:55 +00:00
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CError_FATAL(187);
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2022-12-14 00:16:59 +00:00
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}
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memclrw(&operand, sizeof(Operand));
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operand.optype = OpndType_Symbol;
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operand.object = node->spillTemporary;
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2022-12-29 12:32:55 +00:00
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CError_ASSERT(222, node->spillTemporary->datatype == DLOCAL);
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2022-12-14 00:16:59 +00:00
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coerce_to_addressable(&operand);
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2022-12-29 12:32:55 +00:00
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CError_ASSERT(233, operand.optype == OpndType_GPR_ImmOffset);
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2022-12-14 00:16:59 +00:00
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2022-12-29 12:32:55 +00:00
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CError_ASSERT(237, node->spillTemporary->datatype == DLOCAL);
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2022-12-14 00:16:59 +00:00
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if (node->flags & fPairLow)
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offset = low_offset;
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else if (node->flags & fPairHigh)
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offset = high_offset;
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else
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offset = 0;
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insertpcodebefore(instr, makepcode(opcode, reg, operand.reg, operand.object, operand.immOffset + offset));
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break;
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case RegClass_FPR:
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2022-12-29 12:32:55 +00:00
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CError_ASSERT(253, node->spillTemporary->datatype == DLOCAL);
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2022-12-14 00:16:59 +00:00
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if (node->flags & fPairLow)
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offset = low_offset;
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else if (node->flags & fPairHigh)
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offset = high_offset;
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else
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offset = 0;
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object = node->spillTemporary;
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insertpcodebefore(
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instr,
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makepcode(
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(type->size == 8) ? PC_LFD : PC_LFS,
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reg,
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local_base_register(object),
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object,
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offset
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)
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);
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break;
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case RegClass_VR:
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2022-12-29 12:32:55 +00:00
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CError_ASSERT(320, node->spillTemporary->datatype == DLOCAL);
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2022-12-14 00:16:59 +00:00
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object = node->spillTemporary;
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newInstr = makepcode(PC_ADDI, rTEMP_for_VR_spill, local_base_register(object), object, 0);
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newInstr2 = makepcode(PC_LVX, reg, 0, rTEMP_for_VR_spill);
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insertpcodebefore(instr, newInstr);
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insertpcodeafter(newInstr, newInstr2);
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break;
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default:
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2022-12-29 12:32:55 +00:00
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CError_FATAL(333);
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2022-12-14 00:16:59 +00:00
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}
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}
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static void insert_store_spilled_register(PCode *instr, Boolean flag, short reg, IGNode *node) {
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Object *object; // r31
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Opcode opcode; // r30
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SInt32 offset; // r26
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PCode *newInstr2; // r26
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PCode *newInstr; // r25
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Type *type; // r25
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object = node->spillTemporary;
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type = object->type;
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switch (coloring_class) {
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case RegClass_CRFIELD:
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case RegClass_GPR:
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switch (type->size) {
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case 1:
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opcode = PC_STB;
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break;
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case 2:
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opcode = PC_STH;
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break;
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case 4:
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opcode = PC_STW;
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break;
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case 8:
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opcode = PC_STW;
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break;
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default:
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2022-12-29 12:32:55 +00:00
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CError_FATAL(391);
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2022-12-14 00:16:59 +00:00
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}
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if (node->flags & fPairLow)
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offset = low_offset;
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else if (node->flags & fPairHigh)
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offset = high_offset;
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else
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offset = 0;
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newInstr = makepcode(opcode, reg, local_base_register(object), object, offset);
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if (flag)
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insertpcodebefore(instr, newInstr);
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else
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insertpcodeafter(instr, newInstr);
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break;
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case RegClass_FPR:
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newInstr = makepcode((type->size == 8) ? PC_STFD : PC_STFS, reg, local_base_register(object), object, 0);
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if (flag)
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insertpcodebefore(instr, newInstr);
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else
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insertpcodeafter(instr, newInstr);
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break;
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case RegClass_VR:
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newInstr = makepcode(PC_ADDI, rTEMP_for_VR_spill, local_base_register(object), object, 0);
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newInstr2 = makepcode(PC_STVX, reg, 0, rTEMP_for_VR_spill);
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if (flag)
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insertpcodebefore(instr, newInstr);
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else
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insertpcodeafter(instr, newInstr);
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insertpcodeafter(newInstr, newInstr2);
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break;
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default:
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2022-12-29 12:32:55 +00:00
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CError_FATAL(527);
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2022-12-14 00:16:59 +00:00
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}
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}
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static void spillinstruction(PCodeBlock *block, PCode *instr) {
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int reg;
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int reg2;
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int regs;
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IGNode *node;
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PCodeArg *op;
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int i;
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PCodeArg *op2;
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int j;
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int readCounter;
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int writeCounter;
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Boolean flag;
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regs = used_virtual_registers[coloring_class];
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flag = 0;
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for (i = 0, op = instr->args; i < instr->argCount; i++, op++) {
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2022-12-29 12:32:55 +00:00
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CError_ASSERT(563, instr->block != NULL);
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2022-12-14 00:16:59 +00:00
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if (
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PC_OP_IS_ANY_REGISTER(op, coloring_class) &&
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(reg = op->data.reg.reg) < regs &&
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((node = interferencegraph[op->data.reg.reg])->flags & fSpilled)
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)
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{
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reg2 = used_virtual_registers[coloring_class]++;
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readCounter = 0;
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writeCounter = 0;
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for (j = i, op2 = op; j < instr->argCount; j++, op2++) {
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if (PC_OP_IS_REGISTER(op2, coloring_class, reg)) {
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if (op2->data.reg.effect & EffectRead)
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readCounter++;
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if (op2->data.reg.effect & EffectWrite)
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writeCounter++;
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op2->data.reg.reg = reg2;
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op2->data.reg.effect |= Effect40;
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}
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}
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if (readCounter) {
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if (node->instr8)
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insertpcodebefore(instr, rematerialize_spilled_register(reg2, node));
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else
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insert_load_spilled_register(instr, reg2, node);
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}
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if (writeCounter) {
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2023-01-11 22:29:53 +00:00
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if (node->instr8 || (instr->flags & fIsArgInit))
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2022-12-14 00:16:59 +00:00
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flag = 1;
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else
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insert_store_spilled_register(instr, 0, reg2, node);
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}
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}
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}
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if (flag)
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deletepcode(instr);
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}
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static void spillcopy(PCodeBlock *block, PCode *instr) {
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IGNode *node1;
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IGNode *node2;
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int reg;
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node1 = interferencegraph[instr->args[1].data.reg.reg];
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node2 = interferencegraph[instr->args[0].data.reg.reg];
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if (node1->flags & fSpilled) {
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if (node2->flags & fSpilled) {
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reg = used_virtual_registers[coloring_class]++;
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if (node1->instr8)
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insertpcodebefore(instr, rematerialize_spilled_register(reg, node1));
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else
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insert_load_spilled_register(instr, reg, node1);
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insert_store_spilled_register(instr, 1, reg, node2);
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} else {
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if (node1->instr8)
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insertpcodebefore(instr, rematerialize_spilled_register(instr->args[0].data.reg.reg, node1));
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else
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insert_load_spilled_register(instr, instr->args[0].data.reg.reg, node1);
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}
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} else {
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insert_store_spilled_register(instr, 1, instr->args[1].data.reg.reg, node2);
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}
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deletepcode(instr);
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}
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static void spillcall(PCodeBlock *block, PCode *instr) {
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PCodeArg *opSrc;
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PCodeArg *opDst;
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int opCount;
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int volatileCount;
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int i;
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opCount = instr->argCount;
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volatileCount = branch_count_volatiles();
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opDst = instr->args + volatileCount;
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opSrc = instr->args + volatileCount;
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for (i = volatileCount; i < opCount; i++) {
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if (
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PC_OP_IS_ANY_REGISTER(opSrc, coloring_class) &&
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opSrc->data.reg.reg >= n_real_registers[coloring_class] &&
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(interferencegraph[opSrc->data.reg.reg]->flags & fSpilled)
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)
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{
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instr->argCount--;
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} else {
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*opDst = *opSrc;
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opDst++;
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}
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opSrc++;
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}
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spillinstruction(block, instr);
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}
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static void assign_spill_locations(void) {
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UInt32 i;
|
|
|
|
IGNode *node;
|
|
|
|
Type *type;
|
|
|
|
|
|
|
|
last_unused_vreg_before_spilling = used_virtual_registers[coloring_class];
|
|
|
|
for (i = n_real_registers[coloring_class]; i < last_unused_vreg_before_spilling; i++) {
|
|
|
|
node = interferencegraph[i];
|
|
|
|
if (node->flags & fCoalesced)
|
|
|
|
continue;
|
|
|
|
if (!(node->flags & fSpilled))
|
|
|
|
continue;
|
|
|
|
|
|
|
|
if (!node->spillTemporary) {
|
|
|
|
switch (coloring_class) {
|
|
|
|
case RegClass_GPR:
|
|
|
|
type = TYPE(&stunsignedlong);
|
|
|
|
break;
|
|
|
|
case RegClass_CRFIELD:
|
|
|
|
type = TYPE(&stunsignedlong);
|
|
|
|
break;
|
|
|
|
case RegClass_FPR:
|
|
|
|
type = TYPE(&stunsignedlong);
|
|
|
|
break;
|
|
|
|
case RegClass_VR:
|
|
|
|
type = TYPE(&stvectorunsignedchar);
|
|
|
|
break;
|
|
|
|
default:
|
2022-12-29 12:32:55 +00:00
|
|
|
CError_FATAL(771);
|
2022-12-14 00:16:59 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
node->spillTemporary = makespilltemporary(type);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (node->spillTemporary->datatype == DLOCAL && !(node->spillTemporary->u.var.info->flags & VarInfoFlag1))
|
|
|
|
assign_local_memory(node->spillTemporary);
|
|
|
|
|
|
|
|
if (node->flags & fPairHigh)
|
|
|
|
Registers_GetVarInfo(node->spillTemporary)->regHi = Register0;
|
|
|
|
else
|
|
|
|
Registers_GetVarInfo(node->spillTemporary)->reg = Register0;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
void insertspillcode(void) {
|
|
|
|
PCodeBlock *block;
|
|
|
|
PCode *instr;
|
|
|
|
PCode *nextInstr;
|
|
|
|
PCodeArg *op;
|
|
|
|
UInt32 i;
|
|
|
|
int flag;
|
|
|
|
|
|
|
|
rTEMP_for_VR_spill = 0;
|
|
|
|
assign_spill_locations();
|
|
|
|
|
|
|
|
for (block = pcbasicblocks; block; block = block->nextBlock) {
|
|
|
|
for (instr = block->firstPCode; instr; instr = nextInstr) {
|
|
|
|
nextInstr = instr->nextPCode;
|
|
|
|
flag = 0;
|
|
|
|
op = instr->args;
|
|
|
|
i = instr->argCount;
|
|
|
|
while (i--) {
|
|
|
|
if (
|
|
|
|
PC_OP_IS_ANY_REGISTER(op, coloring_class) &&
|
|
|
|
op->data.reg.reg < last_unused_vreg_before_spilling &&
|
|
|
|
(interferencegraph[op->data.reg.reg]->flags & fSpilled)
|
|
|
|
)
|
|
|
|
{
|
|
|
|
flag = 1;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
op++;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (flag) {
|
|
|
|
if (coloring_class == RegClass_VR && rTEMP_for_VR_spill == 0)
|
|
|
|
rTEMP_for_VR_spill = used_virtual_registers[RegClass_GPR]++;
|
|
|
|
|
2023-01-11 22:29:53 +00:00
|
|
|
if (instr->flags & fIsMove)
|
2022-12-14 00:16:59 +00:00
|
|
|
spillcopy(block, instr);
|
2023-01-11 22:29:53 +00:00
|
|
|
else if (instr->flags & fIsCall)
|
2022-12-14 00:16:59 +00:00
|
|
|
spillcall(block, instr);
|
|
|
|
else
|
|
|
|
spillinstruction(block, instr);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|