mirror of https://git.wuffs.org/MWCC
643 lines
22 KiB
C
643 lines
22 KiB
C
#include "compiler/FunctionCalls.h"
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#include "compiler/CError.h"
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#include "compiler/CFunc.h"
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#include "compiler/CMachine.h"
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#include "compiler/CParser.h"
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#include "compiler/CodeGen.h"
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#include "compiler/CompilerTools.h"
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#include "compiler/InstrSelection.h"
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#include "compiler/Operands.h"
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#include "compiler/PCode.h"
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#include "compiler/PCodeUtilities.h"
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#include "compiler/Registers.h"
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#include "compiler/StackFrame.h"
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#include "compiler/StructMoves.h"
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#include "compiler/types.h"
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enum {
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AIF_PassInGPR = 1,
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AIF_PassInFPR = 2,
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AIF_PassOnStack = 4,
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AIF_ExtendTo32Bits = 8,
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AIF_ForceDoublePrecision = 0x10,
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AIF_PassInVR = 0x20,
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AIF_PassMask = AIF_PassInGPR | AIF_PassInFPR | AIF_PassOnStack | AIF_PassInVR
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};
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#ifdef __MWERKS__
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#pragma options align=mac68k
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#endif
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typedef struct ArgInfo {
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struct ArgInfo *next;
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ENode *expr;
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Operand opnd;
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SInt32 offset;
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short gpr;
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short gprHi;
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short fpr;
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short vr;
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short evaluated;
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short flags;
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} ArgInfo;
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#ifdef __MWERKS__
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#pragma options align=reset
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#endif
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// forward decls
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static void branch_subroutine_indirect_ctr(Operand *addrOpnd, UInt32 *used_regs);
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static ArgInfo *make_arginfo(ENode *expr) {
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ArgInfo *info = lalloc(sizeof(ArgInfo));
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memclrw(info, sizeof(ArgInfo));
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info->next = NULL;
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info->expr = expr;
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info->offset = -1;
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info->gpr = -1;
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info->gprHi = -1;
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info->fpr = -1;
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info->vr = -1;
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info->evaluated = 0;
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info->flags = 0;
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return info;
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}
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static ArgInfo *analyze_arguments(ENode *funcref, ENodeList *arg_expr, FuncArg *arg, UInt32 *used_regs, Boolean *resultHasFloats, char has_varargs) {
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ArgInfo *infos;
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ArgInfo *info;
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SInt32 displ;
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SInt32 arg_size;
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int gpr_counter;
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int fpr_counter;
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int vr_counter;
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Type *type;
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RegClass rclass;
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Boolean spilledVectorFlag;
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infos = NULL;
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displ = 0;
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gpr_counter = 3;
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fpr_counter = 1;
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vr_counter = 2;
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for (rclass = 0; rclass < RegClassMax; rclass++)
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used_regs[rclass] = 0;
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*resultHasFloats = 0;
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while (arg_expr) {
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if (arg_expr->node == funcref) {
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arg_expr = arg_expr->next;
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arg = arg->next;
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continue;
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}
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type = arg_expr->node->rtype;
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if (infos) {
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info->next = make_arginfo(arg_expr->node);
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info = info->next;
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} else {
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infos = info = make_arginfo(arg_expr->node);
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}
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arg_size = 0;
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if (IS_TYPE_VECTOR(type)) {
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if (arg == &elipsis) {
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spilledVectorFlag = 1;
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info->flags |= AIF_PassOnStack;
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} else {
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spilledVectorFlag = 0;
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if (vr_counter <= 13) {
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info->flags |= AIF_PassInVR;
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info->vr = vr_counter;
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used_regs[RegClass_VR] |= 1 << vr_counter;
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} else {
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spilledVectorFlag = 1;
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info->flags |= AIF_PassOnStack;
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}
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}
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if (has_varargs) {
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if (gpr_counter < 10) {
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gpr_counter = ((gpr_counter - 2) & ~3) + 5;
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if (arg == &elipsis && gpr_counter < 10) {
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info->flags |= AIF_PassInGPR;
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info->gpr = gpr_counter;
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used_regs[RegClass_GPR] |= (15 << gpr_counter) & 0x7E0;
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}
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gpr_counter += 4;
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}
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spilledVectorFlag = 1;
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}
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if (spilledVectorFlag)
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arg_size = 16;
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vr_counter++;
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} else if (IS_TYPE_FLOAT(type)) {
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*resultHasFloats = 1;
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if (!arg || arg == &oldstyle) {
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if (fpr_counter <= 13) {
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info->flags |= AIF_PassInFPR;
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info->fpr = fpr_counter;
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used_regs[RegClass_FPR] |= 1 << fpr_counter;
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} else {
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info->flags |= AIF_PassOnStack | AIF_ForceDoublePrecision;
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}
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arg_size = 8;
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fpr_counter++;
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gpr_counter += 2;
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} else if (arg == &elipsis) {
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if (gpr_counter < 10) {
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info->flags |= AIF_PassInGPR;
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info->gpr = gpr_counter;
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used_regs[RegClass_GPR] |= 3 << gpr_counter;
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} else if (gpr_counter == 10) {
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info->flags |= AIF_PassInGPR | AIF_PassOnStack | AIF_ForceDoublePrecision;
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info->gpr = gpr_counter;
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used_regs[RegClass_GPR] |= 3 << gpr_counter;
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} else {
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info->flags |= AIF_PassOnStack | AIF_ForceDoublePrecision;
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}
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arg_size = 8;
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fpr_counter++;
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gpr_counter += 2;
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} else {
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if (fpr_counter <= 13) {
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info->flags |= AIF_PassInFPR;
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info->fpr = fpr_counter;
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used_regs[RegClass_FPR] |= 1 << fpr_counter;
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} else {
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info->flags |= AIF_PassOnStack;
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}
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if (type->size == 4) {
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arg_size = 4;
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gpr_counter++;
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} else {
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arg_size = 8;
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gpr_counter += 2;
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}
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fpr_counter++;
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}
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} else if (TYPE_IS_8BYTES(type)) {
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if (gpr_counter <= 10) {
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info->flags |= AIF_PassInGPR;
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if (copts.littleendian) {
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info->gpr = gpr_counter;
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info->gprHi = gpr_counter + 1;
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} else {
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info->gpr = gpr_counter + 1;
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info->gprHi = gpr_counter;
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}
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used_regs[RegClass_GPR] |= 1 << gpr_counter;
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if ((gpr_counter + 1) <= 10)
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used_regs[RegClass_GPR] |= 1 << (gpr_counter + 1);
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} else {
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info->flags |= AIF_PassOnStack;
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}
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arg_size = 8;
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gpr_counter += 2;
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} else if (TYPE_FITS_IN_REGISTER(type)) {
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if ((!arg || arg == &elipsis || arg == &oldstyle) && type->size < 4)
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info->flags |= AIF_ExtendTo32Bits;
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if (gpr_counter <= 10) {
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info->flags |= AIF_PassInGPR;
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info->gpr = gpr_counter;
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used_regs[RegClass_GPR] |= 1 << gpr_counter;
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} else {
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info->flags |= AIF_PassOnStack;
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}
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arg_size = 4;
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gpr_counter++;
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} else if (IS_TYPE_ARRAY(type) || IS_TYPE_NONVECTOR_STRUCT(type) || IS_TYPE_CLASS(type) ||
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IS_TYPE_12BYTES_MEMBERPOINTER(type)) {
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SInt32 gprs_needed = (type->size >> 2) + ((type->size & 3) != 0);
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if (gpr_counter <= 10) {
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if ((gpr_counter + gprs_needed - 1) <= 10) {
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info->flags |= AIF_PassInGPR;
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info->gpr = gpr_counter;
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used_regs[RegClass_GPR] |= ((1 << gprs_needed) - 1) << gpr_counter;
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} else {
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info->flags |= AIF_PassInGPR | AIF_PassOnStack;
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info->gpr = gpr_counter;
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used_regs[RegClass_GPR] |= ((1 << (11 - gpr_counter)) - 1) << gpr_counter;
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}
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} else {
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info->flags |= AIF_PassOnStack;
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}
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gpr_counter += gprs_needed;
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arg_size = type->size;
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} else {
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CError_FATAL(421);
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}
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displ = set_out_param_displ(displ, type, info->flags & AIF_PassOnStack, &info->offset, arg_size);
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arg_expr = arg_expr->next;
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if (arg && arg != &elipsis && arg != &oldstyle)
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arg = arg->next;
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}
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update_out_param_size(displ);
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return infos;
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}
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static void pass_in_memory(ArgInfo *info) {
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Type *type;
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Operand opnd;
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type = info->expr->rtype;
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memclrw(&opnd, sizeof(Operand));
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if (TYPE_FITS_IN_REGISTER(type)) {
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if (TYPE_IS_8BYTES(type)) {
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if (!info->evaluated)
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GEN_NODE(info->expr, &info->opnd);
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coerce_to_register_pair(&info->opnd, type, 0, 0);
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load_store_register(
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PC_STW, info->opnd.reg, 1,
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NULL, low_offset + out_param_displ_to_offset(info->offset));
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load_store_register(
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PC_STW, info->opnd.regHi, 1,
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NULL, high_offset + out_param_displ_to_offset(info->offset));
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} else {
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if (!info->evaluated)
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GEN_NODE(info->expr, &info->opnd);
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if (info->flags & AIF_ExtendTo32Bits)
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extend32(&info->opnd, type, 0);
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ENSURE_GPR(&info->opnd, type, 0);
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load_store_register(
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PC_STW, info->opnd.reg, 1,
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NULL, out_param_displ_to_offset(info->offset));
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}
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} else if (IS_TYPE_FLOAT(type)) {
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if (!info->evaluated)
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GEN_NODE(info->expr, &info->opnd);
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ENSURE_FPR(&info->opnd, type, 0);
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if (type->size == 4 && !(info->flags & AIF_ForceDoublePrecision)) {
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load_store_register(
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PC_STFS, info->opnd.reg, 1,
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NULL, out_param_displ_to_offset(info->offset));
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} else {
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load_store_register(
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PC_STFD, info->opnd.reg, 1,
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NULL, out_param_displ_to_offset(info->offset));
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}
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} else if (IS_TYPE_VECTOR(type)) {
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if (!info->evaluated)
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GEN_NODE(info->expr, &info->opnd);
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ENSURE_VR(&info->opnd, type, 0);
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load_store_register(
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PC_STVX, info->opnd.reg, 1,
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NULL, out_param_displ_to_offset(info->offset));
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} else {
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opnd.optype = OpndType_IndirectGPR_ImmOffset;
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opnd.reg = 1;
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opnd.object = NULL;
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opnd.immOffset = out_param_displ_to_offset(info->offset);
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if (!info->evaluated)
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GEN_NODE(info->expr, &info->opnd);
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move_block(&opnd, &info->opnd, type->size, CMach_ArgumentAlignment(type));
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}
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}
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static void pass_in_register(ArgInfo *info) {
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Type *type;
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type = info->expr->rtype;
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if ((info->flags & AIF_PassMask) == AIF_PassInFPR) {
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if (!info->evaluated)
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GEN_NODE_TO_REG(info->expr, info->fpr, 0, &info->opnd);
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ENSURE_FPR(&info->opnd, type, info->fpr);
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if (info->opnd.reg != info->fpr)
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emitpcode(PC_FMR, info->fpr, info->opnd.reg);
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} else if ((info->flags & AIF_PassMask) == AIF_PassInVR) {
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if (!info->evaluated)
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GEN_NODE_TO_REG(info->expr, info->vr, 0, &info->opnd);
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ENSURE_VR(&info->opnd, type, info->vr);
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if (info->opnd.reg != info->vr)
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emitpcode(PC_VMR, info->vr, info->opnd.reg);
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} else if (TYPE_FITS_IN_REGISTER(type)) {
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if (TYPE_IS_8BYTES(type)) {
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if (!info->evaluated)
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GEN_NODE_TO_REG(info->expr, info->gpr, info->gprHi, &info->opnd);
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coerce_to_register_pair(&info->opnd, type, info->gpr, info->gprHi);
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if (copts.littleendian) {
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if (info->gprHi > 10) {
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load_store_register(
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PC_STW, info->opnd.regHi, 1,
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NULL, high_offset + out_param_displ_to_offset(info->offset));
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}
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} else {
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if (info->gpr > 10) {
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load_store_register(
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PC_STW, info->opnd.reg, 1,
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NULL, low_offset + out_param_displ_to_offset(info->offset));
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}
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}
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} else {
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if (!info->evaluated)
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GEN_NODE_TO_REG(info->expr, info->gpr, 0, &info->opnd);
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if (info->flags & AIF_ExtendTo32Bits)
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extend32(&info->opnd, type, info->gpr);
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ENSURE_GPR(&info->opnd, type, info->gpr);
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if (info->opnd.reg != info->gpr)
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emitpcode(PC_MR, info->gpr, info->opnd.reg);
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}
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} else if (IS_TYPE_FLOAT(type)) {
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if (!info->evaluated)
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GEN_NODE(info->expr, &info->opnd);
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if (type->size != 4 && info->opnd.optype == OpndType_IndirectGPR_ImmOffset) {
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load_store_register(
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PC_LWZ, info->gpr, info->opnd.reg,
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info->opnd.object, info->opnd.immOffset);
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load_store_register(
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PC_LWZ, info->gpr + 1, info->opnd.reg,
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info->opnd.object, info->opnd.immOffset + 4);
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} else {
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ENSURE_FPR(&info->opnd, type, 0);
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load_store_register(
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PC_STFD, info->opnd.reg, 1,
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NULL, out_param_displ_to_offset(info->offset));
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load_store_register(
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PC_LWZ, info->gpr, 1,
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NULL, out_param_displ_to_offset(info->offset));
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load_store_register(
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PC_LWZ, info->gpr + 1, 1,
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NULL, out_param_displ_to_offset(info->offset) + 4);
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}
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} else if (IS_TYPE_VECTOR(type)) {
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if (!info->evaluated)
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GEN_NODE(info->expr, &info->opnd);
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if (info->opnd.optype == OpndType_IndirectGPR_ImmOffset) {
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load_store_register(
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PC_LWZ, info->gpr, info->opnd.reg,
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info->opnd.object, info->opnd.immOffset);
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load_store_register(
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PC_LWZ, info->gpr + 1, info->opnd.reg,
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info->opnd.object, info->opnd.immOffset + 4);
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if ((info->gpr + 2) < 10) {
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load_store_register(
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PC_LWZ, info->gpr + 2, info->opnd.reg,
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info->opnd.object, info->opnd.immOffset + 8);
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load_store_register(
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PC_LWZ, info->gpr + 3, info->opnd.reg,
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info->opnd.object, info->opnd.immOffset + 12);
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}
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} else {
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ENSURE_VR(&info->opnd, type, 0);
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load_store_register(
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PC_STVX, info->opnd.reg, 1,
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NULL, out_param_displ_to_offset(info->offset));
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load_store_register(
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PC_LWZ, info->gpr, 1,
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NULL, out_param_displ_to_offset(info->offset));
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load_store_register(
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PC_LWZ, info->gpr + 1, 1,
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NULL, out_param_displ_to_offset(info->offset) + 4);
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if ((info->gpr + 2) < 10) {
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load_store_register(
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PC_LWZ, info->gpr + 2, 1,
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NULL, out_param_displ_to_offset(info->offset) + 8);
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load_store_register(
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PC_LWZ, info->gpr + 3, 1,
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NULL, out_param_displ_to_offset(info->offset) + 12);
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}
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}
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} else {
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if (!info->evaluated)
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GEN_NODE(info->expr, &info->opnd);
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if (type->size <= 4) {
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if (info->opnd.optype == OpndType_IndirectSymbol)
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coerce_to_addressable(&info->opnd);
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if (info->opnd.optype == OpndType_IndirectGPR_ImmOffset) {
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load_store_register(
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PC_LWZ, info->gpr, info->opnd.reg,
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info->opnd.object, info->opnd.immOffset);
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} else if (info->opnd.optype == OpndType_IndirectGPR_Indexed) {
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emitpcode(
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PC_LWZX, info->gpr, info->opnd.reg,
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info->opnd.regOffset);
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}
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} else {
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SInt32 gprs_needed = (type->size >> 2) + ((type->size & 3) != 0);
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SInt32 i;
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make_addressable(&info->opnd, gprs_needed * 4, 12);
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for (i = 0; i < gprs_needed; i++) {
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if (info->opnd.reg != (info->gpr + i)) {
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load_store_register(
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PC_LWZ, info->gpr + i, info->opnd.reg,
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info->opnd.object, info->opnd.immOffset + i * 4);
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}
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}
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if (info->opnd.reg >= info->gpr && info->opnd.reg < (info->gpr + gprs_needed)) {
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load_store_register(
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PC_LWZ, info->opnd.reg, info->opnd.reg,
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info->opnd.object, info->opnd.immOffset + (info->opnd.reg - info->gpr) * 4);
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}
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}
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}
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}
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static void pass_in_register_and_memory(ArgInfo *info) {
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Type *type;
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int gpr;
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SInt32 offset;
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type = info->expr->rtype;
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gpr = info->gpr;
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offset = 0;
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|
while (offset < type->size && gpr <= 10) {
|
|
load_store_register(
|
|
PC_LWZ, gpr, 1,
|
|
NULL, offset + out_param_displ_to_offset(info->offset));
|
|
gpr++;
|
|
offset += 4;
|
|
}
|
|
}
|
|
|
|
static Boolean needs_TOC_reload(Object *func) {
|
|
return 0;
|
|
}
|
|
|
|
static void load_virtual_function(TypeClass *tclass, SInt32 offset, int reg, Operand *opnd) {
|
|
if (tclass->flags & CLASS_FLAGS_1) {
|
|
load_store_register(PC_LWZ, 12, reg, NULL, 0);
|
|
load_store_register(PC_LWZ, 12, 12, NULL, tclass->vtable->offset);
|
|
} else {
|
|
load_store_register(PC_LWZ, 12, reg, NULL, tclass->vtable->offset);
|
|
}
|
|
load_store_register(PC_LWZ, 12, 12, NULL, offset);
|
|
opnd->optype = OpndType_GPR;
|
|
opnd->reg = 12;
|
|
}
|
|
|
|
static void branch_subroutine_indirect(Object *func, Operand *addrOpnd, UInt32 *used_regs) {
|
|
if (addrOpnd->reg != 12)
|
|
emitpcode(PC_MR, 12, addrOpnd->reg);
|
|
|
|
used_regs[RegClass_GPR] |= 1 << 12;
|
|
branch_subroutine(func, 1, used_regs);
|
|
}
|
|
|
|
static void evaluate_nested_function_calls(ArgInfo *info) {
|
|
ArgInfo *scan;
|
|
|
|
scan = info->next;
|
|
while (scan && !scan->expr->hascall)
|
|
scan = scan->next;
|
|
|
|
if (scan)
|
|
evaluate_nested_function_calls(scan);
|
|
|
|
if (info->expr->hascall) {
|
|
GEN_NODE(info->expr, &info->opnd);
|
|
info->evaluated = 1;
|
|
}
|
|
}
|
|
|
|
void call_function(ENode *expr, Operand *output) {
|
|
ArgInfo *infos; // r31
|
|
ENode *funcref = expr->data.funccall.funcref; // r27
|
|
Type *resultType = expr->data.funccall.functype->functype; // r26
|
|
ENode *node = NULL; // r25
|
|
char has_varargs; // r24
|
|
ArgInfo *info; // r22
|
|
Operand opnd;
|
|
UInt32 used_regs[RegClassMax] = {0};
|
|
Boolean has_floats;
|
|
FuncArg *arg;
|
|
|
|
memclrw(&opnd, sizeof(Operand));
|
|
|
|
has_varargs = 0;
|
|
for (arg = expr->data.funccall.functype->args; arg; arg = arg->next) {
|
|
if (arg == &elipsis) {
|
|
has_varargs = 1;
|
|
break;
|
|
}
|
|
}
|
|
|
|
if (expr->data.funccall.functype->flags & FUNC_FLAGS_80) {
|
|
if (CMach_PassResultInHiddenArg(resultType))
|
|
node = expr->data.funccall.args->next->node;
|
|
else
|
|
node = expr->data.funccall.args->node;
|
|
}
|
|
|
|
infos = analyze_arguments(
|
|
node,
|
|
expr->data.funccall.args,
|
|
expr->data.funccall.functype->args,
|
|
used_regs,
|
|
&has_floats,
|
|
has_varargs);
|
|
|
|
if (infos)
|
|
evaluate_nested_function_calls(infos);
|
|
|
|
if (funcref->hascall) {
|
|
GEN_NODE_TO_GPR(funcref, &opnd, TYPE(&void_ptr), 0);
|
|
} else if (node && node->hascall) {
|
|
GEN_NODE_TO_GPR(node, &opnd, TYPE(&void_ptr), 0);
|
|
}
|
|
|
|
for (info = infos; info; info = info->next) {
|
|
if (info->flags & AIF_PassOnStack)
|
|
pass_in_memory(info);
|
|
}
|
|
for (info = infos; info; info = info->next) {
|
|
if ((info->flags & AIF_PassMask) == (AIF_PassInGPR | AIF_PassOnStack))
|
|
pass_in_register_and_memory(info);
|
|
}
|
|
for (info = infos; info; info = info->next) {
|
|
int flag = info->flags & AIF_PassMask;
|
|
if (
|
|
flag == AIF_PassInGPR ||
|
|
flag == AIF_PassInFPR ||
|
|
flag == AIF_PassInVR
|
|
)
|
|
pass_in_register(info);
|
|
}
|
|
|
|
if (funcref->type == EOBJREF) {
|
|
TypeClass *tclass;
|
|
SInt32 vfOffset;
|
|
if (CParser_IsVirtualFunction(funcref->data.objref, &tclass, &vfOffset)) {
|
|
load_virtual_function(
|
|
tclass,
|
|
vfOffset,
|
|
CMach_PassResultInHiddenArg(resultType) ? Register4 : Register3,
|
|
&opnd
|
|
);
|
|
branch_subroutine_indirect_ctr(&opnd, used_regs);
|
|
} else if (node) {
|
|
if (!node->hascall) {
|
|
GEN_NODE_TO_REG(node, 12, 0, &opnd);
|
|
ENSURE_GPR(&opnd, TYPE(&void_ptr), 12);
|
|
}
|
|
branch_subroutine_indirect(funcref->data.objref, &opnd, used_regs);
|
|
} else {
|
|
branch_subroutine(funcref->data.objref, needs_TOC_reload(funcref->data.objref), used_regs);
|
|
}
|
|
} else {
|
|
if (!funcref->hascall)
|
|
GEN_NODE_TO_REG(funcref, 12, 0, &opnd);
|
|
ENSURE_GPR(&opnd, TYPE(&void_ptr), 12);
|
|
branch_subroutine_indirect_ctr(&opnd, used_regs);
|
|
}
|
|
|
|
if (IS_TYPE_FLOAT(resultType)) {
|
|
output->optype = OpndType_FPR;
|
|
output->reg = used_virtual_registers[RegClass_FPR]++;
|
|
emitpcode(PC_FMR, output->reg, 1);
|
|
} else if (IS_TYPE_VECTOR(resultType)) {
|
|
output->optype = OpndType_VR;
|
|
output->reg = used_virtual_registers[RegClass_VR]++;
|
|
emitpcode(PC_VMR, output->reg, 2);
|
|
} else if (TYPE_FITS_IN_REGISTER(resultType)) {
|
|
if (resultType->size > 4) {
|
|
output->optype = OpndType_GPRPair;
|
|
output->reg = used_virtual_registers[RegClass_GPR]++;
|
|
output->regHi = used_virtual_registers[RegClass_GPR]++;
|
|
emitpcode(PC_MR, output->reg, low_reg);
|
|
emitpcode(PC_MR, output->regHi, high_reg);
|
|
} else {
|
|
output->optype = OpndType_GPR;
|
|
output->reg = used_virtual_registers[RegClass_GPR]++;
|
|
emitpcode(PC_MR, output->reg, 3);
|
|
}
|
|
} else {
|
|
output->optype = OpndType_Absolute;
|
|
output->immediate = 0;
|
|
}
|
|
}
|
|
|
|
static void branch_subroutine_indirect_ctr(Operand *addrOpnd, UInt32 *used_regs) {
|
|
if (addrOpnd->reg != 12)
|
|
emitpcode(PC_MR, 12, addrOpnd->reg);
|
|
|
|
emitpcode(PC_MTCTR, 12);
|
|
used_regs[RegClass_GPR] |= 1 << 12;
|
|
branch_subroutine_ctr(used_regs);
|
|
}
|