From b5d518b68b9acdc61ce5d0ff9e0a531d451f8364 Mon Sep 17 00:00:00 2001
From: David Neto <dneto@google.com>
Date: Tue, 21 Apr 2020 17:44:44 +0000
Subject: [PATCH] [spirv-reader] Test block order dup cases

- branch-conditional where both targets are the same
- switch where the default target is the same as a case target

Bug: tint:3
Change-Id: If5a3e1fead43ae3d528341f3e54dcae959d9eb8c
Reviewed-on: https://dawn-review.googlesource.com/c/tint/+/20061
Reviewed-by: dan sinclair <dsinclair@google.com>
---
 src/reader/spirv/function_cfg_test.cc | 53 +++++++++++++++++++++++++++
 1 file changed, 53 insertions(+)

diff --git a/src/reader/spirv/function_cfg_test.cc b/src/reader/spirv/function_cfg_test.cc
index 255947aea3..10756a170b 100644
--- a/src/reader/spirv/function_cfg_test.cc
+++ b/src/reader/spirv/function_cfg_test.cc
@@ -145,6 +145,29 @@ TEST_F(SpvParserTest, ComputeBlockOrder_ReorderSequence) {
   EXPECT_THAT(fe.rspo(), ElementsAre(10, 20, 30));
 }
 
+TEST_F(SpvParserTest, ComputeBlockOrder_DupConditionalBranch) {
+  auto* p = parser(test::Assemble(CommonTypes() + R"(
+     %100 = OpFunction %void None %voidfn
+
+     %10 = OpLabel
+     OpSelectionMerge %99 None
+     OpBranchConditional %cond %20 %20
+
+     %99 = OpLabel
+     OpReturn
+
+     %20 = OpLabel
+     OpBranch %99
+
+     OpFunctionEnd
+  )"));
+  ASSERT_TRUE(p->BuildAndParseInternalModuleExceptFunctions()) << p->error();
+  FunctionEmitter fe(p, *spirv_function(100));
+  fe.ComputeBlockOrderAndPositions();
+
+  EXPECT_THAT(fe.rspo(), ElementsAre(10, 20, 99));
+}
+
 TEST_F(SpvParserTest, ComputeBlockOrder_RespectConditionalBranchOrder) {
   auto* p = parser(test::Assemble(CommonTypes() + R"(
      %100 = OpFunction %void None %voidfn
@@ -273,6 +296,36 @@ TEST_F(SpvParserTest,
   EXPECT_THAT(fe.rspo(), ElementsAre(10, 30, 20, 80, 99));
 }
 
+TEST_F(SpvParserTest,
+       ComputeBlockOrder_Switch_DefaultSameAsACase) {
+  auto* p = parser(test::Assemble(CommonTypes() + R"(
+     %100 = OpFunction %void None %voidfn
+
+     %10 = OpLabel
+     OpSelectionMerge %99 None
+     OpSwitch %selector %30 20 %20 30 %30 40 %40
+
+     %99 = OpLabel
+     OpReturn
+
+     %30 = OpLabel
+     OpBranch %99
+
+     %20 = OpLabel
+     OpBranch %99
+
+     %40 = OpLabel
+     OpBranch %99
+
+     OpFunctionEnd
+  )"));
+  ASSERT_TRUE(p->BuildAndParseInternalModuleExceptFunctions()) << p->error();
+  FunctionEmitter fe(p, *spirv_function(100));
+  fe.ComputeBlockOrderAndPositions();
+
+  EXPECT_THAT(fe.rspo(), ElementsAre(10, 40, 20, 30, 99));
+}
+
 TEST_F(SpvParserTest, ComputeBlockOrder_RespectSwitchCaseFallthrough) {
   auto assembly = CommonTypes() + R"(
      %100 = OpFunction %void None %voidfn