diff --git a/disasm-py/src/lib.rs b/disasm-py/src/lib.rs
index efcd9aa..a1ebb48 100644
--- a/disasm-py/src/lib.rs
+++ b/disasm-py/src/lib.rs
@@ -161,14 +161,22 @@ impl Ins {
         self.0.field_crm() as i64
     }
     #[getter]
-    fn ps_l(&self) -> i64 {
-        self.0.field_ps_l() as i64
+    fn ps_I(&self) -> i64 {
+        self.0.field_ps_I() as i64
+    }
+    #[getter]
+    fn ps_IX(&self) -> i64 {
+        self.0.field_ps_IX() as i64
     }
     #[getter]
     fn ps_W(&self) -> i64 {
         self.0.field_ps_W() as i64
     }
     #[getter]
+    fn ps_WX(&self) -> i64 {
+        self.0.field_ps_WX() as i64
+    }
+    #[getter]
     fn ps_NB(&self) -> i64 {
         self.0.field_NB() as i64
     }
diff --git a/disasm/src/generated.rs b/disasm/src/generated.rs
index 86cbc1c..5becd08 100644
--- a/disasm/src/generated.rs
+++ b/disasm/src/generated.rs
@@ -1133,6 +1133,7 @@ pub enum Field {
     ps_offset(Offset),
     BO(OpaqueU),
     BI(OpaqueU),
+    BH(OpaqueU),
     BD(BranchDest),
     LI(BranchDest),
     SH(OpaqueU),
@@ -1156,13 +1157,16 @@ pub enum Field {
     crfD(CRField),
     crfS(CRField),
     crm(OpaqueU),
-    ps_l(GQR),
+    ps_I(GQR),
+    ps_IX(GQR),
     ps_W(OpaqueU),
+    ps_WX(OpaqueU),
     NB(OpaqueU),
     tbr(OpaqueU),
     mtfsf_FM(OpaqueU),
     mtfsf_IMM(OpaqueU),
     TO(OpaqueU),
+    L(OpaqueU),
     xer,
     ctr,
     lr,
@@ -1176,6 +1180,7 @@ impl Field {
             Field::ps_offset(x) => Some(Argument::Offset(*x)),
             Field::BO(x) => Some(Argument::OpaqueU(*x)),
             Field::BI(x) => Some(Argument::OpaqueU(*x)),
+            Field::BH(x) => Some(Argument::OpaqueU(*x)),
             Field::BD(x) => Some(Argument::BranchDest(*x)),
             Field::LI(x) => Some(Argument::BranchDest(*x)),
             Field::SH(x) => Some(Argument::OpaqueU(*x)),
@@ -1199,13 +1204,16 @@ impl Field {
             Field::crfD(x) => Some(Argument::CRField(*x)),
             Field::crfS(x) => Some(Argument::CRField(*x)),
             Field::crm(x) => Some(Argument::OpaqueU(*x)),
-            Field::ps_l(x) => Some(Argument::GQR(*x)),
+            Field::ps_I(x) => Some(Argument::GQR(*x)),
+            Field::ps_IX(x) => Some(Argument::GQR(*x)),
             Field::ps_W(x) => Some(Argument::OpaqueU(*x)),
+            Field::ps_WX(x) => Some(Argument::OpaqueU(*x)),
             Field::NB(x) => Some(Argument::OpaqueU(*x)),
             Field::tbr(x) => Some(Argument::OpaqueU(*x)),
             Field::mtfsf_FM(x) => Some(Argument::OpaqueU(*x)),
             Field::mtfsf_IMM(x) => Some(Argument::OpaqueU(*x)),
             Field::TO(x) => Some(Argument::OpaqueU(*x)),
+            Field::L(x) => Some(Argument::OpaqueU(*x)),
             _ => None,
         }
     }
@@ -1217,6 +1225,7 @@ impl Field {
             Field::ps_offset(_) => "ps_offset",
             Field::BO(_) => "BO",
             Field::BI(_) => "BI",
+            Field::BH(_) => "BH",
             Field::BD(_) => "BD",
             Field::LI(_) => "LI",
             Field::SH(_) => "SH",
@@ -1240,13 +1249,16 @@ impl Field {
             Field::crfD(_) => "crfD",
             Field::crfS(_) => "crfS",
             Field::crm(_) => "crm",
-            Field::ps_l(_) => "ps_l",
+            Field::ps_I(_) => "ps_I",
+            Field::ps_IX(_) => "ps_IX",
             Field::ps_W(_) => "ps_W",
+            Field::ps_WX(_) => "ps_WX",
             Field::NB(_) => "NB",
             Field::tbr(_) => "tbr",
             Field::mtfsf_FM(_) => "mtfsf_FM",
             Field::mtfsf_IMM(_) => "mtfsf_IMM",
             Field::TO(_) => "TO",
+            Field::L(_) => "L",
             Field::xer => "xer",
             Field::ctr => "ctr",
             Field::lr => "lr",
@@ -1277,21 +1289,21 @@ impl Ins {
                 Field::rD(GPR(((self.code >> 21u8) & 0x1f) as _)),
                 Field::rA(GPR(((self.code >> 16u8) & 0x1f) as _)),
                 Field::simm(Simm(
-                    (((self.code & 0xffff) ^ 0x8000).wrapping_sub(0x8000)) as _,
+                    ((((self.code & 0xffff) ^ 0x8000).wrapping_sub(0x8000)) as i32) as _,
                 )),
             ],
             Opcode::Addic => vec![
                 Field::rD(GPR(((self.code >> 21u8) & 0x1f) as _)),
                 Field::rA(GPR(((self.code >> 16u8) & 0x1f) as _)),
                 Field::simm(Simm(
-                    (((self.code & 0xffff) ^ 0x8000).wrapping_sub(0x8000)) as _,
+                    ((((self.code & 0xffff) ^ 0x8000).wrapping_sub(0x8000)) as i32) as _,
                 )),
             ],
             Opcode::Addic_ => vec![
                 Field::rD(GPR(((self.code >> 21u8) & 0x1f) as _)),
                 Field::rA(GPR(((self.code >> 16u8) & 0x1f) as _)),
                 Field::simm(Simm(
-                    (((self.code & 0xffff) ^ 0x8000).wrapping_sub(0x8000)) as _,
+                    ((((self.code & 0xffff) ^ 0x8000).wrapping_sub(0x8000)) as i32) as _,
                 )),
             ],
             Opcode::Addis => vec![
@@ -1328,42 +1340,50 @@ impl Ins {
                 Field::uimm(Uimm((self.code & 0xffff) as _)),
             ],
             Opcode::B => vec![Field::LI(BranchDest(
-                (((((self.code >> 2u8) & 0xffffff) ^ 0x800000).wrapping_sub(0x800000)) << 2u8) as _,
+                ((((((self.code >> 2u8) & 0xffffff) ^ 0x800000).wrapping_sub(0x800000)) as i32)
+                    << 2u8) as _,
             ))],
             Opcode::Bc => vec![
                 Field::BO(OpaqueU(((self.code >> 21u8) & 0x1f) as _)),
                 Field::BI(OpaqueU(((self.code >> 16u8) & 0x1f) as _)),
                 Field::BD(BranchDest(
-                    (((((self.code >> 2u8) & 0x3fff) ^ 0x2000).wrapping_sub(0x2000)) << 2u8) as _,
+                    ((((((self.code >> 2u8) & 0x3fff) ^ 0x2000).wrapping_sub(0x2000)) as i32)
+                        << 2u8) as _,
                 )),
             ],
             Opcode::Bcctr => vec![
                 Field::BO(OpaqueU(((self.code >> 21u8) & 0x1f) as _)),
                 Field::BI(OpaqueU(((self.code >> 16u8) & 0x1f) as _)),
+                Field::BH(OpaqueU(((self.code >> 11u8) & 0x3) as _)),
             ],
             Opcode::Bclr => vec![
                 Field::BO(OpaqueU(((self.code >> 21u8) & 0x1f) as _)),
                 Field::BI(OpaqueU(((self.code >> 16u8) & 0x1f) as _)),
+                Field::BH(OpaqueU(((self.code >> 11u8) & 0x3) as _)),
             ],
             Opcode::Cmp => vec![
                 Field::crfD(CRField(((self.code >> 23u8) & 0x7) as _)),
+                Field::L(OpaqueU(((self.code >> 21u8) & 0x1) as _)),
                 Field::rA(GPR(((self.code >> 16u8) & 0x1f) as _)),
                 Field::rB(GPR(((self.code >> 11u8) & 0x1f) as _)),
             ],
             Opcode::Cmpi => vec![
                 Field::crfD(CRField(((self.code >> 23u8) & 0x7) as _)),
+                Field::L(OpaqueU(((self.code >> 21u8) & 0x1) as _)),
                 Field::rA(GPR(((self.code >> 16u8) & 0x1f) as _)),
                 Field::simm(Simm(
-                    (((self.code & 0xffff) ^ 0x8000).wrapping_sub(0x8000)) as _,
+                    ((((self.code & 0xffff) ^ 0x8000).wrapping_sub(0x8000)) as i32) as _,
                 )),
             ],
             Opcode::Cmpl => vec![
                 Field::crfD(CRField(((self.code >> 23u8) & 0x7) as _)),
+                Field::L(OpaqueU(((self.code >> 21u8) & 0x1) as _)),
                 Field::rA(GPR(((self.code >> 16u8) & 0x1f) as _)),
                 Field::rB(GPR(((self.code >> 11u8) & 0x1f) as _)),
             ],
             Opcode::Cmpli => vec![
                 Field::crfD(CRField(((self.code >> 23u8) & 0x7) as _)),
+                Field::L(OpaqueU(((self.code >> 21u8) & 0x1) as _)),
                 Field::rA(GPR(((self.code >> 16u8) & 0x1f) as _)),
                 Field::uimm(Uimm((self.code & 0xffff) as _)),
             ],
@@ -1621,14 +1641,14 @@ impl Ins {
             Opcode::Lbz => vec![
                 Field::rD(GPR(((self.code >> 21u8) & 0x1f) as _)),
                 Field::offset(Offset(
-                    (((self.code & 0xffff) ^ 0x8000).wrapping_sub(0x8000)) as _,
+                    ((((self.code & 0xffff) ^ 0x8000).wrapping_sub(0x8000)) as i32) as _,
                 )),
                 Field::rA(GPR(((self.code >> 16u8) & 0x1f) as _)),
             ],
             Opcode::Lbzu => vec![
                 Field::rD(GPR(((self.code >> 21u8) & 0x1f) as _)),
                 Field::offset(Offset(
-                    (((self.code & 0xffff) ^ 0x8000).wrapping_sub(0x8000)) as _,
+                    ((((self.code & 0xffff) ^ 0x8000).wrapping_sub(0x8000)) as i32) as _,
                 )),
                 Field::rA(GPR(((self.code >> 16u8) & 0x1f) as _)),
             ],
@@ -1645,14 +1665,14 @@ impl Ins {
             Opcode::Lfd => vec![
                 Field::frD(FPR(((self.code >> 21u8) & 0x1f) as _)),
                 Field::offset(Offset(
-                    (((self.code & 0xffff) ^ 0x8000).wrapping_sub(0x8000)) as _,
+                    ((((self.code & 0xffff) ^ 0x8000).wrapping_sub(0x8000)) as i32) as _,
                 )),
                 Field::rA(GPR(((self.code >> 16u8) & 0x1f) as _)),
             ],
             Opcode::Lfdu => vec![
                 Field::frD(FPR(((self.code >> 21u8) & 0x1f) as _)),
                 Field::offset(Offset(
-                    (((self.code & 0xffff) ^ 0x8000).wrapping_sub(0x8000)) as _,
+                    ((((self.code & 0xffff) ^ 0x8000).wrapping_sub(0x8000)) as i32) as _,
                 )),
                 Field::rA(GPR(((self.code >> 16u8) & 0x1f) as _)),
             ],
@@ -1669,14 +1689,14 @@ impl Ins {
             Opcode::Lfs => vec![
                 Field::frD(FPR(((self.code >> 21u8) & 0x1f) as _)),
                 Field::offset(Offset(
-                    (((self.code & 0xffff) ^ 0x8000).wrapping_sub(0x8000)) as _,
+                    ((((self.code & 0xffff) ^ 0x8000).wrapping_sub(0x8000)) as i32) as _,
                 )),
                 Field::rA(GPR(((self.code >> 16u8) & 0x1f) as _)),
             ],
             Opcode::Lfsu => vec![
                 Field::frD(FPR(((self.code >> 21u8) & 0x1f) as _)),
                 Field::offset(Offset(
-                    (((self.code & 0xffff) ^ 0x8000).wrapping_sub(0x8000)) as _,
+                    ((((self.code & 0xffff) ^ 0x8000).wrapping_sub(0x8000)) as i32) as _,
                 )),
                 Field::rA(GPR(((self.code >> 16u8) & 0x1f) as _)),
             ],
@@ -1693,14 +1713,14 @@ impl Ins {
             Opcode::Lha => vec![
                 Field::rD(GPR(((self.code >> 21u8) & 0x1f) as _)),
                 Field::offset(Offset(
-                    (((self.code & 0xffff) ^ 0x8000).wrapping_sub(0x8000)) as _,
+                    ((((self.code & 0xffff) ^ 0x8000).wrapping_sub(0x8000)) as i32) as _,
                 )),
                 Field::rA(GPR(((self.code >> 16u8) & 0x1f) as _)),
             ],
             Opcode::Lhau => vec![
                 Field::rD(GPR(((self.code >> 21u8) & 0x1f) as _)),
                 Field::offset(Offset(
-                    (((self.code & 0xffff) ^ 0x8000).wrapping_sub(0x8000)) as _,
+                    ((((self.code & 0xffff) ^ 0x8000).wrapping_sub(0x8000)) as i32) as _,
                 )),
                 Field::rA(GPR(((self.code >> 16u8) & 0x1f) as _)),
             ],
@@ -1722,14 +1742,14 @@ impl Ins {
             Opcode::Lhz => vec![
                 Field::rD(GPR(((self.code >> 21u8) & 0x1f) as _)),
                 Field::offset(Offset(
-                    (((self.code & 0xffff) ^ 0x8000).wrapping_sub(0x8000)) as _,
+                    ((((self.code & 0xffff) ^ 0x8000).wrapping_sub(0x8000)) as i32) as _,
                 )),
                 Field::rA(GPR(((self.code >> 16u8) & 0x1f) as _)),
             ],
             Opcode::Lhzu => vec![
                 Field::rD(GPR(((self.code >> 21u8) & 0x1f) as _)),
                 Field::offset(Offset(
-                    (((self.code & 0xffff) ^ 0x8000).wrapping_sub(0x8000)) as _,
+                    ((((self.code & 0xffff) ^ 0x8000).wrapping_sub(0x8000)) as i32) as _,
                 )),
                 Field::rA(GPR(((self.code >> 16u8) & 0x1f) as _)),
             ],
@@ -1746,7 +1766,7 @@ impl Ins {
             Opcode::Lmw => vec![
                 Field::rD(GPR(((self.code >> 21u8) & 0x1f) as _)),
                 Field::offset(Offset(
-                    (((self.code & 0xffff) ^ 0x8000).wrapping_sub(0x8000)) as _,
+                    ((((self.code & 0xffff) ^ 0x8000).wrapping_sub(0x8000)) as i32) as _,
                 )),
                 Field::rA(GPR(((self.code >> 16u8) & 0x1f) as _)),
             ],
@@ -1773,14 +1793,14 @@ impl Ins {
             Opcode::Lwz => vec![
                 Field::rD(GPR(((self.code >> 21u8) & 0x1f) as _)),
                 Field::offset(Offset(
-                    (((self.code & 0xffff) ^ 0x8000).wrapping_sub(0x8000)) as _,
+                    ((((self.code & 0xffff) ^ 0x8000).wrapping_sub(0x8000)) as i32) as _,
                 )),
                 Field::rA(GPR(((self.code >> 16u8) & 0x1f) as _)),
             ],
             Opcode::Lwzu => vec![
                 Field::rD(GPR(((self.code >> 21u8) & 0x1f) as _)),
                 Field::offset(Offset(
-                    (((self.code & 0xffff) ^ 0x8000).wrapping_sub(0x8000)) as _,
+                    ((((self.code & 0xffff) ^ 0x8000).wrapping_sub(0x8000)) as i32) as _,
                 )),
                 Field::rA(GPR(((self.code >> 16u8) & 0x1f) as _)),
             ],
@@ -1803,7 +1823,7 @@ impl Ins {
                 Field::crfS(CRField(((self.code >> 18u8) & 0x7) as _)),
             ],
             Opcode::Mcrxr => vec![Field::crfD(CRField(((self.code >> 23u8) & 0x7) as _))],
-            Opcode::Mfcr => vec![Field::crfD(CRField(((self.code >> 23u8) & 0x7) as _))],
+            Opcode::Mfcr => vec![Field::rD(GPR(((self.code >> 21u8) & 0x1f) as _))],
             Opcode::Mffs => vec![Field::frD(FPR(((self.code >> 21u8) & 0x1f) as _))],
             Opcode::Mfmsr => vec![Field::rD(GPR(((self.code >> 21u8) & 0x1f) as _))],
             Opcode::Mfspr => vec![
@@ -1875,7 +1895,7 @@ impl Ins {
                 Field::rD(GPR(((self.code >> 21u8) & 0x1f) as _)),
                 Field::rA(GPR(((self.code >> 16u8) & 0x1f) as _)),
                 Field::simm(Simm(
-                    (((self.code & 0xffff) ^ 0x8000).wrapping_sub(0x8000)) as _,
+                    ((((self.code & 0xffff) ^ 0x8000).wrapping_sub(0x8000)) as i32) as _,
                 )),
             ],
             Opcode::Mullw => vec![
@@ -1920,66 +1940,66 @@ impl Ins {
             Opcode::PsqL => vec![
                 Field::frD(FPR(((self.code >> 21u8) & 0x1f) as _)),
                 Field::ps_offset(Offset(
-                    (((self.code & 0xfff) ^ 0x800).wrapping_sub(0x800)) as _,
+                    ((((self.code & 0xfff) ^ 0x800).wrapping_sub(0x800)) as i32) as _,
                 )),
                 Field::rA(GPR(((self.code >> 16u8) & 0x1f) as _)),
                 Field::ps_W(OpaqueU(((self.code >> 15u8) & 0x1) as _)),
-                Field::ps_l(GQR(((self.code >> 12u8) & 0x7) as _)),
+                Field::ps_I(GQR(((self.code >> 12u8) & 0x7) as _)),
             ],
             Opcode::PsqLu => vec![
                 Field::frD(FPR(((self.code >> 21u8) & 0x1f) as _)),
                 Field::ps_offset(Offset(
-                    (((self.code & 0xfff) ^ 0x800).wrapping_sub(0x800)) as _,
+                    ((((self.code & 0xfff) ^ 0x800).wrapping_sub(0x800)) as i32) as _,
                 )),
                 Field::rA(GPR(((self.code >> 16u8) & 0x1f) as _)),
                 Field::ps_W(OpaqueU(((self.code >> 15u8) & 0x1) as _)),
-                Field::ps_l(GQR(((self.code >> 12u8) & 0x7) as _)),
+                Field::ps_I(GQR(((self.code >> 12u8) & 0x7) as _)),
             ],
             Opcode::PsqLux => vec![
                 Field::frD(FPR(((self.code >> 21u8) & 0x1f) as _)),
                 Field::rA(GPR(((self.code >> 16u8) & 0x1f) as _)),
                 Field::rB(GPR(((self.code >> 11u8) & 0x1f) as _)),
-                Field::ps_W(OpaqueU(((self.code >> 15u8) & 0x1) as _)),
-                Field::ps_l(GQR(((self.code >> 12u8) & 0x7) as _)),
+                Field::ps_WX(OpaqueU(((self.code >> 10u8) & 0x1) as _)),
+                Field::ps_IX(GQR(((self.code >> 7u8) & 0x7) as _)),
             ],
             Opcode::PsqLx => vec![
                 Field::frD(FPR(((self.code >> 21u8) & 0x1f) as _)),
                 Field::rA(GPR(((self.code >> 16u8) & 0x1f) as _)),
                 Field::rB(GPR(((self.code >> 11u8) & 0x1f) as _)),
-                Field::ps_W(OpaqueU(((self.code >> 15u8) & 0x1) as _)),
-                Field::ps_l(GQR(((self.code >> 12u8) & 0x7) as _)),
+                Field::ps_WX(OpaqueU(((self.code >> 10u8) & 0x1) as _)),
+                Field::ps_IX(GQR(((self.code >> 7u8) & 0x7) as _)),
             ],
             Opcode::PsqSt => vec![
                 Field::frS(FPR(((self.code >> 21u8) & 0x1f) as _)),
                 Field::ps_offset(Offset(
-                    (((self.code & 0xfff) ^ 0x800).wrapping_sub(0x800)) as _,
+                    ((((self.code & 0xfff) ^ 0x800).wrapping_sub(0x800)) as i32) as _,
                 )),
                 Field::rA(GPR(((self.code >> 16u8) & 0x1f) as _)),
                 Field::ps_W(OpaqueU(((self.code >> 15u8) & 0x1) as _)),
-                Field::ps_l(GQR(((self.code >> 12u8) & 0x7) as _)),
+                Field::ps_I(GQR(((self.code >> 12u8) & 0x7) as _)),
             ],
             Opcode::PsqStu => vec![
                 Field::frS(FPR(((self.code >> 21u8) & 0x1f) as _)),
                 Field::ps_offset(Offset(
-                    (((self.code & 0xfff) ^ 0x800).wrapping_sub(0x800)) as _,
+                    ((((self.code & 0xfff) ^ 0x800).wrapping_sub(0x800)) as i32) as _,
                 )),
                 Field::rA(GPR(((self.code >> 16u8) & 0x1f) as _)),
                 Field::ps_W(OpaqueU(((self.code >> 15u8) & 0x1) as _)),
-                Field::ps_l(GQR(((self.code >> 12u8) & 0x7) as _)),
+                Field::ps_I(GQR(((self.code >> 12u8) & 0x7) as _)),
             ],
             Opcode::PsqStux => vec![
                 Field::frS(FPR(((self.code >> 21u8) & 0x1f) as _)),
                 Field::rA(GPR(((self.code >> 16u8) & 0x1f) as _)),
                 Field::rB(GPR(((self.code >> 11u8) & 0x1f) as _)),
-                Field::ps_W(OpaqueU(((self.code >> 15u8) & 0x1) as _)),
-                Field::ps_l(GQR(((self.code >> 12u8) & 0x7) as _)),
+                Field::ps_WX(OpaqueU(((self.code >> 10u8) & 0x1) as _)),
+                Field::ps_IX(GQR(((self.code >> 7u8) & 0x7) as _)),
             ],
             Opcode::PsqStx => vec![
                 Field::frS(FPR(((self.code >> 21u8) & 0x1f) as _)),
                 Field::rA(GPR(((self.code >> 16u8) & 0x1f) as _)),
                 Field::rB(GPR(((self.code >> 11u8) & 0x1f) as _)),
-                Field::ps_W(OpaqueU(((self.code >> 15u8) & 0x1) as _)),
-                Field::ps_l(GQR(((self.code >> 12u8) & 0x7) as _)),
+                Field::ps_WX(OpaqueU(((self.code >> 10u8) & 0x1) as _)),
+                Field::ps_IX(GQR(((self.code >> 7u8) & 0x7) as _)),
             ],
             Opcode::PsAbs => vec![
                 Field::frD(FPR(((self.code >> 21u8) & 0x1f) as _)),
@@ -2055,7 +2075,6 @@ impl Ins {
             ],
             Opcode::PsMr => vec![
                 Field::frD(FPR(((self.code >> 21u8) & 0x1f) as _)),
-                Field::frA(FPR(((self.code >> 16u8) & 0x1f) as _)),
                 Field::frB(FPR(((self.code >> 11u8) & 0x1f) as _)),
             ],
             Opcode::PsMsub => vec![
@@ -2169,21 +2188,21 @@ impl Ins {
                 Field::SH(OpaqueU(((self.code >> 11u8) & 0x1f) as _)),
             ],
             Opcode::Srw => vec![
-                Field::rS(GPR(((self.code >> 21u8) & 0x1f) as _)),
                 Field::rA(GPR(((self.code >> 16u8) & 0x1f) as _)),
+                Field::rS(GPR(((self.code >> 21u8) & 0x1f) as _)),
                 Field::rB(GPR(((self.code >> 11u8) & 0x1f) as _)),
             ],
             Opcode::Stb => vec![
                 Field::rS(GPR(((self.code >> 21u8) & 0x1f) as _)),
                 Field::offset(Offset(
-                    (((self.code & 0xffff) ^ 0x8000).wrapping_sub(0x8000)) as _,
+                    ((((self.code & 0xffff) ^ 0x8000).wrapping_sub(0x8000)) as i32) as _,
                 )),
                 Field::rA(GPR(((self.code >> 16u8) & 0x1f) as _)),
             ],
             Opcode::Stbu => vec![
                 Field::rS(GPR(((self.code >> 21u8) & 0x1f) as _)),
                 Field::offset(Offset(
-                    (((self.code & 0xffff) ^ 0x8000).wrapping_sub(0x8000)) as _,
+                    ((((self.code & 0xffff) ^ 0x8000).wrapping_sub(0x8000)) as i32) as _,
                 )),
                 Field::rA(GPR(((self.code >> 16u8) & 0x1f) as _)),
             ],
@@ -2200,14 +2219,14 @@ impl Ins {
             Opcode::Stfd => vec![
                 Field::frS(FPR(((self.code >> 21u8) & 0x1f) as _)),
                 Field::offset(Offset(
-                    (((self.code & 0xffff) ^ 0x8000).wrapping_sub(0x8000)) as _,
+                    ((((self.code & 0xffff) ^ 0x8000).wrapping_sub(0x8000)) as i32) as _,
                 )),
                 Field::rA(GPR(((self.code >> 16u8) & 0x1f) as _)),
             ],
             Opcode::Stfdu => vec![
                 Field::frS(FPR(((self.code >> 21u8) & 0x1f) as _)),
                 Field::offset(Offset(
-                    (((self.code & 0xffff) ^ 0x8000).wrapping_sub(0x8000)) as _,
+                    ((((self.code & 0xffff) ^ 0x8000).wrapping_sub(0x8000)) as i32) as _,
                 )),
                 Field::rA(GPR(((self.code >> 16u8) & 0x1f) as _)),
             ],
@@ -2229,14 +2248,14 @@ impl Ins {
             Opcode::Stfs => vec![
                 Field::frS(FPR(((self.code >> 21u8) & 0x1f) as _)),
                 Field::offset(Offset(
-                    (((self.code & 0xffff) ^ 0x8000).wrapping_sub(0x8000)) as _,
+                    ((((self.code & 0xffff) ^ 0x8000).wrapping_sub(0x8000)) as i32) as _,
                 )),
                 Field::rA(GPR(((self.code >> 16u8) & 0x1f) as _)),
             ],
             Opcode::Stfsu => vec![
                 Field::frS(FPR(((self.code >> 21u8) & 0x1f) as _)),
                 Field::offset(Offset(
-                    (((self.code & 0xffff) ^ 0x8000).wrapping_sub(0x8000)) as _,
+                    ((((self.code & 0xffff) ^ 0x8000).wrapping_sub(0x8000)) as i32) as _,
                 )),
                 Field::rA(GPR(((self.code >> 16u8) & 0x1f) as _)),
             ],
@@ -2253,7 +2272,7 @@ impl Ins {
             Opcode::Sth => vec![
                 Field::rS(GPR(((self.code >> 21u8) & 0x1f) as _)),
                 Field::offset(Offset(
-                    (((self.code & 0xffff) ^ 0x8000).wrapping_sub(0x8000)) as _,
+                    ((((self.code & 0xffff) ^ 0x8000).wrapping_sub(0x8000)) as i32) as _,
                 )),
                 Field::rA(GPR(((self.code >> 16u8) & 0x1f) as _)),
             ],
@@ -2265,7 +2284,7 @@ impl Ins {
             Opcode::Sthu => vec![
                 Field::rS(GPR(((self.code >> 21u8) & 0x1f) as _)),
                 Field::offset(Offset(
-                    (((self.code & 0xffff) ^ 0x8000).wrapping_sub(0x8000)) as _,
+                    ((((self.code & 0xffff) ^ 0x8000).wrapping_sub(0x8000)) as i32) as _,
                 )),
                 Field::rA(GPR(((self.code >> 16u8) & 0x1f) as _)),
             ],
@@ -2282,7 +2301,7 @@ impl Ins {
             Opcode::Stmw => vec![
                 Field::rS(GPR(((self.code >> 21u8) & 0x1f) as _)),
                 Field::offset(Offset(
-                    (((self.code & 0xffff) ^ 0x8000).wrapping_sub(0x8000)) as _,
+                    ((((self.code & 0xffff) ^ 0x8000).wrapping_sub(0x8000)) as i32) as _,
                 )),
                 Field::rA(GPR(((self.code >> 16u8) & 0x1f) as _)),
             ],
@@ -2299,7 +2318,7 @@ impl Ins {
             Opcode::Stw => vec![
                 Field::rS(GPR(((self.code >> 21u8) & 0x1f) as _)),
                 Field::offset(Offset(
-                    (((self.code & 0xffff) ^ 0x8000).wrapping_sub(0x8000)) as _,
+                    ((((self.code & 0xffff) ^ 0x8000).wrapping_sub(0x8000)) as i32) as _,
                 )),
                 Field::rA(GPR(((self.code >> 16u8) & 0x1f) as _)),
             ],
@@ -2316,7 +2335,7 @@ impl Ins {
             Opcode::Stwu => vec![
                 Field::rS(GPR(((self.code >> 21u8) & 0x1f) as _)),
                 Field::offset(Offset(
-                    (((self.code & 0xffff) ^ 0x8000).wrapping_sub(0x8000)) as _,
+                    ((((self.code & 0xffff) ^ 0x8000).wrapping_sub(0x8000)) as i32) as _,
                 )),
                 Field::rA(GPR(((self.code >> 16u8) & 0x1f) as _)),
             ],
@@ -2349,7 +2368,7 @@ impl Ins {
                 Field::rD(GPR(((self.code >> 21u8) & 0x1f) as _)),
                 Field::rA(GPR(((self.code >> 16u8) & 0x1f) as _)),
                 Field::simm(Simm(
-                    (((self.code & 0xffff) ^ 0x8000).wrapping_sub(0x8000)) as _,
+                    ((((self.code & 0xffff) ^ 0x8000).wrapping_sub(0x8000)) as i32) as _,
                 )),
             ],
             Opcode::Subfme => vec![
@@ -2372,7 +2391,7 @@ impl Ins {
                 Field::TO(OpaqueU(((self.code >> 21u8) & 0x1f) as _)),
                 Field::rA(GPR(((self.code >> 16u8) & 0x1f) as _)),
                 Field::simm(Simm(
-                    (((self.code & 0xffff) ^ 0x8000).wrapping_sub(0x8000)) as _,
+                    ((((self.code & 0xffff) ^ 0x8000).wrapping_sub(0x8000)) as i32) as _,
                 )),
             ],
             Opcode::Xor => vec![
@@ -2542,7 +2561,7 @@ impl Ins {
                 Field::crfD(CRField(((self.code >> 23u8) & 0x7) as _)),
                 Field::xer,
             ],
-            Opcode::Mfcr => vec![Field::crfD(CRField(((self.code >> 23u8) & 0x7) as _))],
+            Opcode::Mfcr => vec![Field::rD(GPR(((self.code >> 21u8) & 0x1f) as _))],
             Opcode::Mffs => vec![Field::frD(FPR(((self.code >> 21u8) & 0x1f) as _))],
             Opcode::Mfmsr => vec![Field::rD(GPR(((self.code >> 21u8) & 0x1f) as _))],
             Opcode::Mfspr => vec![Field::rD(GPR(((self.code >> 21u8) & 0x1f) as _))],
@@ -3128,7 +3147,7 @@ impl Ins {
             }
             Opcode::Lbz => {
                 let mut uses = vec![Field::offset(Offset(
-                    (((self.code & 0xffff) ^ 0x8000).wrapping_sub(0x8000)) as _,
+                    ((((self.code & 0xffff) ^ 0x8000).wrapping_sub(0x8000)) as i32) as _,
                 ))];
                 if ((self.code >> 16u8) & 0x1f) != 0 {
                     uses.push(Field::rA(GPR(((self.code >> 16u8) & 0x1f) as _)));
@@ -3138,7 +3157,7 @@ impl Ins {
             Opcode::Lbzu => {
                 let mut uses = vec![
                     Field::offset(Offset(
-                        (((self.code & 0xffff) ^ 0x8000).wrapping_sub(0x8000)) as _,
+                        ((((self.code & 0xffff) ^ 0x8000).wrapping_sub(0x8000)) as i32) as _,
                     )),
                     Field::rA(GPR(((self.code >> 16u8) & 0x1f) as _)),
                 ];
@@ -3160,7 +3179,7 @@ impl Ins {
             }
             Opcode::Lfd => {
                 let mut uses = vec![Field::offset(Offset(
-                    (((self.code & 0xffff) ^ 0x8000).wrapping_sub(0x8000)) as _,
+                    ((((self.code & 0xffff) ^ 0x8000).wrapping_sub(0x8000)) as i32) as _,
                 ))];
                 if ((self.code >> 16u8) & 0x1f) != 0 {
                     uses.push(Field::rA(GPR(((self.code >> 16u8) & 0x1f) as _)));
@@ -3170,7 +3189,7 @@ impl Ins {
             Opcode::Lfdu => {
                 let mut uses = vec![
                     Field::offset(Offset(
-                        (((self.code & 0xffff) ^ 0x8000).wrapping_sub(0x8000)) as _,
+                        ((((self.code & 0xffff) ^ 0x8000).wrapping_sub(0x8000)) as i32) as _,
                     )),
                     Field::rA(GPR(((self.code >> 16u8) & 0x1f) as _)),
                 ];
@@ -3192,7 +3211,7 @@ impl Ins {
             }
             Opcode::Lfs => {
                 let mut uses = vec![Field::offset(Offset(
-                    (((self.code & 0xffff) ^ 0x8000).wrapping_sub(0x8000)) as _,
+                    ((((self.code & 0xffff) ^ 0x8000).wrapping_sub(0x8000)) as i32) as _,
                 ))];
                 if ((self.code >> 16u8) & 0x1f) != 0 {
                     uses.push(Field::rA(GPR(((self.code >> 16u8) & 0x1f) as _)));
@@ -3202,7 +3221,7 @@ impl Ins {
             Opcode::Lfsu => {
                 let mut uses = vec![
                     Field::offset(Offset(
-                        (((self.code & 0xffff) ^ 0x8000).wrapping_sub(0x8000)) as _,
+                        ((((self.code & 0xffff) ^ 0x8000).wrapping_sub(0x8000)) as i32) as _,
                     )),
                     Field::rA(GPR(((self.code >> 16u8) & 0x1f) as _)),
                 ];
@@ -3224,7 +3243,7 @@ impl Ins {
             }
             Opcode::Lha => {
                 let mut uses = vec![Field::offset(Offset(
-                    (((self.code & 0xffff) ^ 0x8000).wrapping_sub(0x8000)) as _,
+                    ((((self.code & 0xffff) ^ 0x8000).wrapping_sub(0x8000)) as i32) as _,
                 ))];
                 if ((self.code >> 16u8) & 0x1f) != 0 {
                     uses.push(Field::rA(GPR(((self.code >> 16u8) & 0x1f) as _)));
@@ -3234,7 +3253,7 @@ impl Ins {
             Opcode::Lhau => {
                 let mut uses = vec![
                     Field::offset(Offset(
-                        (((self.code & 0xffff) ^ 0x8000).wrapping_sub(0x8000)) as _,
+                        ((((self.code & 0xffff) ^ 0x8000).wrapping_sub(0x8000)) as i32) as _,
                     )),
                     Field::rA(GPR(((self.code >> 16u8) & 0x1f) as _)),
                 ];
@@ -3263,7 +3282,7 @@ impl Ins {
             }
             Opcode::Lhz => {
                 let mut uses = vec![Field::offset(Offset(
-                    (((self.code & 0xffff) ^ 0x8000).wrapping_sub(0x8000)) as _,
+                    ((((self.code & 0xffff) ^ 0x8000).wrapping_sub(0x8000)) as i32) as _,
                 ))];
                 if ((self.code >> 16u8) & 0x1f) != 0 {
                     uses.push(Field::rA(GPR(((self.code >> 16u8) & 0x1f) as _)));
@@ -3273,7 +3292,7 @@ impl Ins {
             Opcode::Lhzu => {
                 let mut uses = vec![
                     Field::offset(Offset(
-                        (((self.code & 0xffff) ^ 0x8000).wrapping_sub(0x8000)) as _,
+                        ((((self.code & 0xffff) ^ 0x8000).wrapping_sub(0x8000)) as i32) as _,
                     )),
                     Field::rA(GPR(((self.code >> 16u8) & 0x1f) as _)),
                 ];
@@ -3295,7 +3314,7 @@ impl Ins {
             }
             Opcode::Lmw => {
                 let mut uses = vec![Field::offset(Offset(
-                    (((self.code & 0xffff) ^ 0x8000).wrapping_sub(0x8000)) as _,
+                    ((((self.code & 0xffff) ^ 0x8000).wrapping_sub(0x8000)) as i32) as _,
                 ))];
                 if ((self.code >> 16u8) & 0x1f) != 0 {
                     uses.push(Field::rA(GPR(((self.code >> 16u8) & 0x1f) as _)));
@@ -3332,7 +3351,7 @@ impl Ins {
             }
             Opcode::Lwz => {
                 let mut uses = vec![Field::offset(Offset(
-                    (((self.code & 0xffff) ^ 0x8000).wrapping_sub(0x8000)) as _,
+                    ((((self.code & 0xffff) ^ 0x8000).wrapping_sub(0x8000)) as i32) as _,
                 ))];
                 if ((self.code >> 16u8) & 0x1f) != 0 {
                     uses.push(Field::rA(GPR(((self.code >> 16u8) & 0x1f) as _)));
@@ -3342,7 +3361,7 @@ impl Ins {
             Opcode::Lwzu => {
                 let mut uses = vec![
                     Field::offset(Offset(
-                        (((self.code & 0xffff) ^ 0x8000).wrapping_sub(0x8000)) as _,
+                        ((((self.code & 0xffff) ^ 0x8000).wrapping_sub(0x8000)) as i32) as _,
                     )),
                     Field::rA(GPR(((self.code >> 16u8) & 0x1f) as _)),
                 ];
@@ -4184,22 +4203,22 @@ impl Ins {
             Opcode::Andis_ => String::new(),
             Opcode::B => {
                 let mut s = String::with_capacity(4);
-                if self.bit(30usize) {
-                    s.push('a');
-                }
                 if self.bit(31usize) {
                     s.push('l');
                 }
+                if self.bit(30usize) {
+                    s.push('a');
+                }
                 s
             }
             Opcode::Bc => {
                 let mut s = String::with_capacity(4);
-                if self.bit(30usize) {
-                    s.push('a');
-                }
                 if self.bit(31usize) {
                     s.push('l');
                 }
+                if self.bit(30usize) {
+                    s.push('a');
+                }
                 s
             }
             Opcode::Bcctr => {
@@ -4512,13 +4531,7 @@ impl Ins {
             Opcode::Mcrfs => String::new(),
             Opcode::Mcrxr => String::new(),
             Opcode::Mfcr => String::new(),
-            Opcode::Mffs => {
-                let mut s = String::with_capacity(4);
-                if self.bit(31usize) {
-                    s.push('.');
-                }
-                s
-            }
+            Opcode::Mffs => String::new(),
             Opcode::Mfmsr => String::new(),
             Opcode::Mfspr => String::new(),
             Opcode::Mfsr => String::new(),
@@ -4571,13 +4584,7 @@ impl Ins {
                 }
                 s
             }
-            Opcode::Mulli => {
-                let mut s = String::with_capacity(4);
-                if self.bit(31usize) {
-                    s.push('.');
-                }
-                s
-            }
+            Opcode::Mulli => String::new(),
             Opcode::Mullw => {
                 let mut s = String::with_capacity(4);
                 if self.bit(21usize) {
@@ -4636,185 +4643,35 @@ impl Ins {
             Opcode::PsqStu => String::new(),
             Opcode::PsqStux => String::new(),
             Opcode::PsqStx => String::new(),
-            Opcode::PsAbs => {
-                let mut s = String::with_capacity(4);
-                if self.bit(31usize) {
-                    s.push('.');
-                }
-                s
-            }
-            Opcode::PsAdd => {
-                let mut s = String::with_capacity(4);
-                if self.bit(31usize) {
-                    s.push('.');
-                }
-                s
-            }
+            Opcode::PsAbs => String::new(),
+            Opcode::PsAdd => String::new(),
             Opcode::PsCmpo0 => String::new(),
             Opcode::PsCmpo1 => String::new(),
             Opcode::PsCmpu0 => String::new(),
             Opcode::PsCmpu1 => String::new(),
-            Opcode::PsDiv => {
-                let mut s = String::with_capacity(4);
-                if self.bit(31usize) {
-                    s.push('.');
-                }
-                s
-            }
-            Opcode::PsMadd => {
-                let mut s = String::with_capacity(4);
-                if self.bit(31usize) {
-                    s.push('.');
-                }
-                s
-            }
-            Opcode::PsMadds0 => {
-                let mut s = String::with_capacity(4);
-                if self.bit(31usize) {
-                    s.push('.');
-                }
-                s
-            }
-            Opcode::PsMadds1 => {
-                let mut s = String::with_capacity(4);
-                if self.bit(31usize) {
-                    s.push('.');
-                }
-                s
-            }
-            Opcode::PsMerge00 => {
-                let mut s = String::with_capacity(4);
-                if self.bit(31usize) {
-                    s.push('.');
-                }
-                s
-            }
-            Opcode::PsMerge01 => {
-                let mut s = String::with_capacity(4);
-                if self.bit(31usize) {
-                    s.push('.');
-                }
-                s
-            }
-            Opcode::PsMerge10 => {
-                let mut s = String::with_capacity(4);
-                if self.bit(31usize) {
-                    s.push('.');
-                }
-                s
-            }
-            Opcode::PsMerge11 => {
-                let mut s = String::with_capacity(4);
-                if self.bit(31usize) {
-                    s.push('.');
-                }
-                s
-            }
-            Opcode::PsMr => {
-                let mut s = String::with_capacity(4);
-                if self.bit(31usize) {
-                    s.push('.');
-                }
-                s
-            }
-            Opcode::PsMsub => {
-                let mut s = String::with_capacity(4);
-                if self.bit(31usize) {
-                    s.push('.');
-                }
-                s
-            }
-            Opcode::PsMul => {
-                let mut s = String::with_capacity(4);
-                if self.bit(31usize) {
-                    s.push('.');
-                }
-                s
-            }
-            Opcode::PsMuls0 => {
-                let mut s = String::with_capacity(4);
-                if self.bit(31usize) {
-                    s.push('.');
-                }
-                s
-            }
-            Opcode::PsMuls1 => {
-                let mut s = String::with_capacity(4);
-                if self.bit(31usize) {
-                    s.push('.');
-                }
-                s
-            }
-            Opcode::PsNabs => {
-                let mut s = String::with_capacity(4);
-                if self.bit(31usize) {
-                    s.push('.');
-                }
-                s
-            }
-            Opcode::PsNeg => {
-                let mut s = String::with_capacity(4);
-                if self.bit(31usize) {
-                    s.push('.');
-                }
-                s
-            }
-            Opcode::PsNmadd => {
-                let mut s = String::with_capacity(4);
-                if self.bit(31usize) {
-                    s.push('.');
-                }
-                s
-            }
-            Opcode::PsNmsub => {
-                let mut s = String::with_capacity(4);
-                if self.bit(31usize) {
-                    s.push('.');
-                }
-                s
-            }
-            Opcode::PsRes => {
-                let mut s = String::with_capacity(4);
-                if self.bit(31usize) {
-                    s.push('.');
-                }
-                s
-            }
-            Opcode::PsRsqrte => {
-                let mut s = String::with_capacity(4);
-                if self.bit(31usize) {
-                    s.push('.');
-                }
-                s
-            }
-            Opcode::PsSel => {
-                let mut s = String::with_capacity(4);
-                if self.bit(31usize) {
-                    s.push('.');
-                }
-                s
-            }
-            Opcode::PsSub => {
-                let mut s = String::with_capacity(4);
-                if self.bit(31usize) {
-                    s.push('.');
-                }
-                s
-            }
-            Opcode::PsSum0 => {
-                let mut s = String::with_capacity(4);
-                if self.bit(31usize) {
-                    s.push('.');
-                }
-                s
-            }
-            Opcode::PsSum1 => {
-                let mut s = String::with_capacity(4);
-                if self.bit(31usize) {
-                    s.push('.');
-                }
-                s
-            }
+            Opcode::PsDiv => String::new(),
+            Opcode::PsMadd => String::new(),
+            Opcode::PsMadds0 => String::new(),
+            Opcode::PsMadds1 => String::new(),
+            Opcode::PsMerge00 => String::new(),
+            Opcode::PsMerge01 => String::new(),
+            Opcode::PsMerge10 => String::new(),
+            Opcode::PsMerge11 => String::new(),
+            Opcode::PsMr => String::new(),
+            Opcode::PsMsub => String::new(),
+            Opcode::PsMul => String::new(),
+            Opcode::PsMuls0 => String::new(),
+            Opcode::PsMuls1 => String::new(),
+            Opcode::PsNabs => String::new(),
+            Opcode::PsNeg => String::new(),
+            Opcode::PsNmadd => String::new(),
+            Opcode::PsNmsub => String::new(),
+            Opcode::PsRes => String::new(),
+            Opcode::PsRsqrte => String::new(),
+            Opcode::PsSel => String::new(),
+            Opcode::PsSub => String::new(),
+            Opcode::PsSum0 => String::new(),
+            Opcode::PsSum1 => String::new(),
             Opcode::Rfi => String::new(),
             Opcode::Rlwimi => {
                 let mut s = String::with_capacity(4);
@@ -4949,7 +4806,13 @@ impl Ins {
             Opcode::Tlbsync => String::new(),
             Opcode::Tw => String::new(),
             Opcode::Twi => String::new(),
-            Opcode::Xor => String::new(),
+            Opcode::Xor => {
+                let mut s = String::with_capacity(4);
+                if self.bit(31usize) {
+                    s.push('.');
+                }
+                s
+            }
             Opcode::Xori => String::new(),
             Opcode::Xoris => String::new(),
         }
@@ -4963,7 +4826,8 @@ impl Ins {
                         args: vec![
                             Argument::GPR(GPR(((self.code >> 21u8) & 0x1f) as _)),
                             Argument::Simm(Simm(
-                                (((self.code & 0xffff) ^ 0x8000).wrapping_sub(0x8000)) as _,
+                                ((((self.code & 0xffff) ^ 0x8000).wrapping_sub(0x8000)) as i32)
+                                    as _,
                             )),
                         ],
                         ins: self,
@@ -4997,8 +4861,9 @@ impl Ins {
                     return SimplifiedIns {
                         mnemonic: "blt",
                         args: vec![Argument::BranchDest(BranchDest(
-                            (((((self.code >> 2u8) & 0x3fff) ^ 0x2000).wrapping_sub(0x2000)) << 2u8)
-                                as _,
+                            ((((((self.code >> 2u8) & 0x3fff) ^ 0x2000).wrapping_sub(0x2000))
+                                as i32)
+                                << 2u8) as _,
                         ))],
                         ins: self,
                     };
@@ -5010,7 +4875,8 @@ impl Ins {
                         args: vec![
                             Argument::CRField(CRField(((self.code >> 18u8) & 0x7) as _)),
                             Argument::BranchDest(BranchDest(
-                                (((((self.code >> 2u8) & 0x3fff) ^ 0x2000).wrapping_sub(0x2000))
+                                ((((((self.code >> 2u8) & 0x3fff) ^ 0x2000).wrapping_sub(0x2000))
+                                    as i32)
                                     << 2u8) as _,
                             )),
                         ],
@@ -5024,8 +4890,9 @@ impl Ins {
                     return SimplifiedIns {
                         mnemonic: "ble",
                         args: vec![Argument::BranchDest(BranchDest(
-                            (((((self.code >> 2u8) & 0x3fff) ^ 0x2000).wrapping_sub(0x2000)) << 2u8)
-                                as _,
+                            ((((((self.code >> 2u8) & 0x3fff) ^ 0x2000).wrapping_sub(0x2000))
+                                as i32)
+                                << 2u8) as _,
                         ))],
                         ins: self,
                     };
@@ -5037,7 +4904,8 @@ impl Ins {
                         args: vec![
                             Argument::CRField(CRField(((self.code >> 18u8) & 0x7) as _)),
                             Argument::BranchDest(BranchDest(
-                                (((((self.code >> 2u8) & 0x3fff) ^ 0x2000).wrapping_sub(0x2000))
+                                ((((((self.code >> 2u8) & 0x3fff) ^ 0x2000).wrapping_sub(0x2000))
+                                    as i32)
                                     << 2u8) as _,
                             )),
                         ],
@@ -5051,8 +4919,9 @@ impl Ins {
                     return SimplifiedIns {
                         mnemonic: "beq",
                         args: vec![Argument::BranchDest(BranchDest(
-                            (((((self.code >> 2u8) & 0x3fff) ^ 0x2000).wrapping_sub(0x2000)) << 2u8)
-                                as _,
+                            ((((((self.code >> 2u8) & 0x3fff) ^ 0x2000).wrapping_sub(0x2000))
+                                as i32)
+                                << 2u8) as _,
                         ))],
                         ins: self,
                     };
@@ -5064,7 +4933,8 @@ impl Ins {
                         args: vec![
                             Argument::CRField(CRField(((self.code >> 18u8) & 0x7) as _)),
                             Argument::BranchDest(BranchDest(
-                                (((((self.code >> 2u8) & 0x3fff) ^ 0x2000).wrapping_sub(0x2000))
+                                ((((((self.code >> 2u8) & 0x3fff) ^ 0x2000).wrapping_sub(0x2000))
+                                    as i32)
                                     << 2u8) as _,
                             )),
                         ],
@@ -5078,8 +4948,9 @@ impl Ins {
                     return SimplifiedIns {
                         mnemonic: "bge",
                         args: vec![Argument::BranchDest(BranchDest(
-                            (((((self.code >> 2u8) & 0x3fff) ^ 0x2000).wrapping_sub(0x2000)) << 2u8)
-                                as _,
+                            ((((((self.code >> 2u8) & 0x3fff) ^ 0x2000).wrapping_sub(0x2000))
+                                as i32)
+                                << 2u8) as _,
                         ))],
                         ins: self,
                     };
@@ -5091,7 +4962,8 @@ impl Ins {
                         args: vec![
                             Argument::CRField(CRField(((self.code >> 18u8) & 0x7) as _)),
                             Argument::BranchDest(BranchDest(
-                                (((((self.code >> 2u8) & 0x3fff) ^ 0x2000).wrapping_sub(0x2000))
+                                ((((((self.code >> 2u8) & 0x3fff) ^ 0x2000).wrapping_sub(0x2000))
+                                    as i32)
                                     << 2u8) as _,
                             )),
                         ],
@@ -5105,8 +4977,9 @@ impl Ins {
                     return SimplifiedIns {
                         mnemonic: "bgt",
                         args: vec![Argument::BranchDest(BranchDest(
-                            (((((self.code >> 2u8) & 0x3fff) ^ 0x2000).wrapping_sub(0x2000)) << 2u8)
-                                as _,
+                            ((((((self.code >> 2u8) & 0x3fff) ^ 0x2000).wrapping_sub(0x2000))
+                                as i32)
+                                << 2u8) as _,
                         ))],
                         ins: self,
                     };
@@ -5118,7 +4991,8 @@ impl Ins {
                         args: vec![
                             Argument::CRField(CRField(((self.code >> 18u8) & 0x7) as _)),
                             Argument::BranchDest(BranchDest(
-                                (((((self.code >> 2u8) & 0x3fff) ^ 0x2000).wrapping_sub(0x2000))
+                                ((((((self.code >> 2u8) & 0x3fff) ^ 0x2000).wrapping_sub(0x2000))
+                                    as i32)
                                     << 2u8) as _,
                             )),
                         ],
@@ -5132,8 +5006,9 @@ impl Ins {
                     return SimplifiedIns {
                         mnemonic: "bne",
                         args: vec![Argument::BranchDest(BranchDest(
-                            (((((self.code >> 2u8) & 0x3fff) ^ 0x2000).wrapping_sub(0x2000)) << 2u8)
-                                as _,
+                            ((((((self.code >> 2u8) & 0x3fff) ^ 0x2000).wrapping_sub(0x2000))
+                                as i32)
+                                << 2u8) as _,
                         ))],
                         ins: self,
                     };
@@ -5145,7 +5020,8 @@ impl Ins {
                         args: vec![
                             Argument::CRField(CRField(((self.code >> 18u8) & 0x7) as _)),
                             Argument::BranchDest(BranchDest(
-                                (((((self.code >> 2u8) & 0x3fff) ^ 0x2000).wrapping_sub(0x2000))
+                                ((((((self.code >> 2u8) & 0x3fff) ^ 0x2000).wrapping_sub(0x2000))
+                                    as i32)
                                     << 2u8) as _,
                             )),
                         ],
@@ -5159,8 +5035,9 @@ impl Ins {
                     return SimplifiedIns {
                         mnemonic: "bso",
                         args: vec![Argument::BranchDest(BranchDest(
-                            (((((self.code >> 2u8) & 0x3fff) ^ 0x2000).wrapping_sub(0x2000)) << 2u8)
-                                as _,
+                            ((((((self.code >> 2u8) & 0x3fff) ^ 0x2000).wrapping_sub(0x2000))
+                                as i32)
+                                << 2u8) as _,
                         ))],
                         ins: self,
                     };
@@ -5172,7 +5049,8 @@ impl Ins {
                         args: vec![
                             Argument::CRField(CRField(((self.code >> 18u8) & 0x7) as _)),
                             Argument::BranchDest(BranchDest(
-                                (((((self.code >> 2u8) & 0x3fff) ^ 0x2000).wrapping_sub(0x2000))
+                                ((((((self.code >> 2u8) & 0x3fff) ^ 0x2000).wrapping_sub(0x2000))
+                                    as i32)
                                     << 2u8) as _,
                             )),
                         ],
@@ -5186,8 +5064,9 @@ impl Ins {
                     return SimplifiedIns {
                         mnemonic: "bns",
                         args: vec![Argument::BranchDest(BranchDest(
-                            (((((self.code >> 2u8) & 0x3fff) ^ 0x2000).wrapping_sub(0x2000)) << 2u8)
-                                as _,
+                            ((((((self.code >> 2u8) & 0x3fff) ^ 0x2000).wrapping_sub(0x2000))
+                                as i32)
+                                << 2u8) as _,
                         ))],
                         ins: self,
                     };
@@ -5199,7 +5078,8 @@ impl Ins {
                         args: vec![
                             Argument::CRField(CRField(((self.code >> 18u8) & 0x7) as _)),
                             Argument::BranchDest(BranchDest(
-                                (((((self.code >> 2u8) & 0x3fff) ^ 0x2000).wrapping_sub(0x2000))
+                                ((((((self.code >> 2u8) & 0x3fff) ^ 0x2000).wrapping_sub(0x2000))
+                                    as i32)
                                     << 2u8) as _,
                             )),
                         ],
@@ -5210,8 +5090,9 @@ impl Ins {
                     return SimplifiedIns {
                         mnemonic: "bdnz",
                         args: vec![Argument::BranchDest(BranchDest(
-                            (((((self.code >> 2u8) & 0x3fff) ^ 0x2000).wrapping_sub(0x2000)) << 2u8)
-                                as _,
+                            ((((((self.code >> 2u8) & 0x3fff) ^ 0x2000).wrapping_sub(0x2000))
+                                as i32)
+                                << 2u8) as _,
                         ))],
                         ins: self,
                     };
@@ -5220,8 +5101,9 @@ impl Ins {
                     return SimplifiedIns {
                         mnemonic: "bdz",
                         args: vec![Argument::BranchDest(BranchDest(
-                            (((((self.code >> 2u8) & 0x3fff) ^ 0x2000).wrapping_sub(0x2000)) << 2u8)
-                                as _,
+                            ((((((self.code >> 2u8) & 0x3fff) ^ 0x2000).wrapping_sub(0x2000))
+                                as i32)
+                                << 2u8) as _,
                         ))],
                         ins: self,
                     };
@@ -5534,7 +5416,7 @@ impl Ins {
                 }
             }
             Opcode::Cmp => {
-                if ((self.code >> 23u8) & 0x7) == 0 {
+                if ((self.code >> 23u8) & 0x7) == 0 && ((self.code >> 21u8) & 0x1) == 0 {
                     return SimplifiedIns {
                         mnemonic: "cmpw",
                         args: vec![
@@ -5544,28 +5426,89 @@ impl Ins {
                         ins: self,
                     };
                 }
+                if ((self.code >> 21u8) & 0x1) == 0 {
+                    return SimplifiedIns {
+                        mnemonic: "cmpw",
+                        args: vec![
+                            Argument::CRField(CRField(((self.code >> 23u8) & 0x7) as _)),
+                            Argument::GPR(GPR(((self.code >> 16u8) & 0x1f) as _)),
+                            Argument::GPR(GPR(((self.code >> 11u8) & 0x1f) as _)),
+                        ],
+                        ins: self,
+                    };
+                }
+                if ((self.code >> 23u8) & 0x7) == 0 && ((self.code >> 21u8) & 0x1) == 1 {
+                    return SimplifiedIns {
+                        mnemonic: "cmpd",
+                        args: vec![
+                            Argument::GPR(GPR(((self.code >> 16u8) & 0x1f) as _)),
+                            Argument::GPR(GPR(((self.code >> 11u8) & 0x1f) as _)),
+                        ],
+                        ins: self,
+                    };
+                }
+                if ((self.code >> 21u8) & 0x1) == 1 {
+                    return SimplifiedIns {
+                        mnemonic: "cmpd",
+                        args: vec![
+                            Argument::CRField(CRField(((self.code >> 23u8) & 0x7) as _)),
+                            Argument::GPR(GPR(((self.code >> 16u8) & 0x1f) as _)),
+                            Argument::GPR(GPR(((self.code >> 11u8) & 0x1f) as _)),
+                        ],
+                        ins: self,
+                    };
+                }
             }
             Opcode::Cmpi => {
-                if ((self.code >> 23u8) & 0x7) == 0 {
+                if ((self.code >> 23u8) & 0x7) == 0 && ((self.code >> 21u8) & 0x1) == 0 {
                     return SimplifiedIns {
                         mnemonic: "cmpwi",
                         args: vec![
                             Argument::GPR(GPR(((self.code >> 16u8) & 0x1f) as _)),
                             Argument::Simm(Simm(
-                                (((self.code & 0xffff) ^ 0x8000).wrapping_sub(0x8000)) as _,
+                                ((((self.code & 0xffff) ^ 0x8000).wrapping_sub(0x8000)) as i32)
+                                    as _,
                             )),
                         ],
                         ins: self,
                     };
                 }
-                if ((self.code >> 23u8) & 0x7) == 0 {
+                if ((self.code >> 21u8) & 0x1) == 0 {
                     return SimplifiedIns {
                         mnemonic: "cmpwi",
                         args: vec![
                             Argument::CRField(CRField(((self.code >> 23u8) & 0x7) as _)),
                             Argument::GPR(GPR(((self.code >> 16u8) & 0x1f) as _)),
                             Argument::Simm(Simm(
-                                (((self.code & 0xffff) ^ 0x8000).wrapping_sub(0x8000)) as _,
+                                ((((self.code & 0xffff) ^ 0x8000).wrapping_sub(0x8000)) as i32)
+                                    as _,
+                            )),
+                        ],
+                        ins: self,
+                    };
+                }
+                if ((self.code >> 23u8) & 0x7) == 0 && ((self.code >> 21u8) & 0x1) == 1 {
+                    return SimplifiedIns {
+                        mnemonic: "cmpdi",
+                        args: vec![
+                            Argument::GPR(GPR(((self.code >> 16u8) & 0x1f) as _)),
+                            Argument::Simm(Simm(
+                                ((((self.code & 0xffff) ^ 0x8000).wrapping_sub(0x8000)) as i32)
+                                    as _,
+                            )),
+                        ],
+                        ins: self,
+                    };
+                }
+                if ((self.code >> 21u8) & 0x1) == 1 {
+                    return SimplifiedIns {
+                        mnemonic: "cmpdi",
+                        args: vec![
+                            Argument::CRField(CRField(((self.code >> 23u8) & 0x7) as _)),
+                            Argument::GPR(GPR(((self.code >> 16u8) & 0x1f) as _)),
+                            Argument::Simm(Simm(
+                                ((((self.code & 0xffff) ^ 0x8000).wrapping_sub(0x8000)) as i32)
+                                    as _,
                             )),
                         ],
                         ins: self,
@@ -5573,7 +5516,7 @@ impl Ins {
                 }
             }
             Opcode::Cmpl => {
-                if ((self.code >> 23u8) & 0x7) == 0 {
+                if ((self.code >> 23u8) & 0x7) == 0 && ((self.code >> 21u8) & 0x1) == 0 {
                     return SimplifiedIns {
                         mnemonic: "cmplw",
                         args: vec![
@@ -5583,9 +5526,41 @@ impl Ins {
                         ins: self,
                     };
                 }
+                if ((self.code >> 21u8) & 0x1) == 0 {
+                    return SimplifiedIns {
+                        mnemonic: "cmplw",
+                        args: vec![
+                            Argument::CRField(CRField(((self.code >> 23u8) & 0x7) as _)),
+                            Argument::GPR(GPR(((self.code >> 16u8) & 0x1f) as _)),
+                            Argument::GPR(GPR(((self.code >> 11u8) & 0x1f) as _)),
+                        ],
+                        ins: self,
+                    };
+                }
+                if ((self.code >> 23u8) & 0x7) == 0 && ((self.code >> 21u8) & 0x1) == 1 {
+                    return SimplifiedIns {
+                        mnemonic: "cmpld",
+                        args: vec![
+                            Argument::GPR(GPR(((self.code >> 16u8) & 0x1f) as _)),
+                            Argument::GPR(GPR(((self.code >> 11u8) & 0x1f) as _)),
+                        ],
+                        ins: self,
+                    };
+                }
+                if ((self.code >> 21u8) & 0x1) == 1 {
+                    return SimplifiedIns {
+                        mnemonic: "cmpld",
+                        args: vec![
+                            Argument::CRField(CRField(((self.code >> 23u8) & 0x7) as _)),
+                            Argument::GPR(GPR(((self.code >> 16u8) & 0x1f) as _)),
+                            Argument::GPR(GPR(((self.code >> 11u8) & 0x1f) as _)),
+                        ],
+                        ins: self,
+                    };
+                }
             }
             Opcode::Cmpli => {
-                if ((self.code >> 23u8) & 0x7) == 0 {
+                if ((self.code >> 23u8) & 0x7) == 0 && ((self.code >> 21u8) & 0x1) == 0 {
                     return SimplifiedIns {
                         mnemonic: "cmplwi",
                         args: vec![
@@ -5595,7 +5570,7 @@ impl Ins {
                         ins: self,
                     };
                 }
-                if ((self.code >> 23u8) & 0x7) == 0 {
+                if ((self.code >> 21u8) & 0x1) == 0 {
                     return SimplifiedIns {
                         mnemonic: "cmplwi",
                         args: vec![
@@ -5606,6 +5581,27 @@ impl Ins {
                         ins: self,
                     };
                 }
+                if ((self.code >> 23u8) & 0x7) == 0 && ((self.code >> 21u8) & 0x1) == 1 {
+                    return SimplifiedIns {
+                        mnemonic: "cmpldi",
+                        args: vec![
+                            Argument::GPR(GPR(((self.code >> 16u8) & 0x1f) as _)),
+                            Argument::Uimm(Uimm((self.code & 0xffff) as _)),
+                        ],
+                        ins: self,
+                    };
+                }
+                if ((self.code >> 21u8) & 0x1) == 1 {
+                    return SimplifiedIns {
+                        mnemonic: "cmpldi",
+                        args: vec![
+                            Argument::CRField(CRField(((self.code >> 23u8) & 0x7) as _)),
+                            Argument::GPR(GPR(((self.code >> 16u8) & 0x1f) as _)),
+                            Argument::Uimm(Uimm((self.code & 0xffff) as _)),
+                        ],
+                        ins: self,
+                    };
+                }
             }
             Opcode::Creqv => {
                 if ((self.code >> 21u8) & 0x1f) == ((self.code >> 16u8) & 0x1f)
@@ -5711,17 +5707,6 @@ impl Ins {
                         ins: self,
                     };
                 }
-                if (((((self.code >> 11u8) & 0x3ff) & 0b11111_00000u32) >> 5u32)
-                    | ((((self.code >> 11u8) & 0x3ff) & 0b00000_11111u32) << 5u32))
-                    as u32
-                    == 571
-                {
-                    return SimplifiedIns {
-                        mnemonic: "mftdu",
-                        args: vec![Argument::GPR(GPR(((self.code >> 21u8) & 0x1f) as _))],
-                        ins: self,
-                    };
-                }
             }
             Opcode::Mtspr => {
                 if (((((self.code >> 11u8) & 0x3ff) & 0b11111_00000u32) >> 5u32)
@@ -5779,17 +5764,6 @@ impl Ins {
                         ins: self,
                     };
                 }
-                if (((((self.code >> 11u8) & 0x3ff) & 0b11111_00000u32) >> 5u32)
-                    | ((((self.code >> 11u8) & 0x3ff) & 0b00000_11111u32) << 5u32))
-                    as u32
-                    == 571
-                {
-                    return SimplifiedIns {
-                        mnemonic: "mttdu",
-                        args: vec![Argument::GPR(GPR(((self.code >> 21u8) & 0x1f) as _))],
-                        ins: self,
-                    };
-                }
             }
             Opcode::Or => {
                 if ((self.code >> 21u8) & 0x1f) == ((self.code >> 11u8) & 0x1f) {
@@ -5846,7 +5820,7 @@ impl Ins {
                         args: vec![
                             Argument::GPR(GPR(((self.code >> 16u8) & 0x1f) as _)),
                             Argument::GPR(GPR(((self.code >> 21u8) & 0x1f) as _)),
-                            Argument::OpaqueU(OpaqueU(((self.code >> 1u8) & 0x1f) as _)),
+                            Argument::OpaqueU(OpaqueU(((self.code >> 11u8) & 0x1f) as _)),
                         ],
                         ins: self,
                     };
@@ -5872,7 +5846,8 @@ impl Ins {
                         args: vec![
                             Argument::GPR(GPR(((self.code >> 16u8) & 0x1f) as _)),
                             Argument::Simm(Simm(
-                                (((self.code & 0xffff) ^ 0x8000).wrapping_sub(0x8000)) as _,
+                                ((((self.code & 0xffff) ^ 0x8000).wrapping_sub(0x8000)) as i32)
+                                    as _,
                             )),
                         ],
                         ins: self,
@@ -5884,7 +5859,8 @@ impl Ins {
                         args: vec![
                             Argument::GPR(GPR(((self.code >> 16u8) & 0x1f) as _)),
                             Argument::Simm(Simm(
-                                (((self.code & 0xffff) ^ 0x8000).wrapping_sub(0x8000)) as _,
+                                ((((self.code & 0xffff) ^ 0x8000).wrapping_sub(0x8000)) as i32)
+                                    as _,
                             )),
                         ],
                         ins: self,
@@ -5900,7 +5876,7 @@ impl Ins {
 impl Ins {
     #[inline(always)]
     pub fn field_simm(&self) -> isize {
-        (((self.code & 0xffff) ^ 0x8000).wrapping_sub(0x8000)) as _
+        ((((self.code & 0xffff) ^ 0x8000).wrapping_sub(0x8000)) as i32) as _
     }
     #[inline(always)]
     pub fn field_uimm(&self) -> usize {
@@ -5908,11 +5884,11 @@ impl Ins {
     }
     #[inline(always)]
     pub fn field_offset(&self) -> isize {
-        (((self.code & 0xffff) ^ 0x8000).wrapping_sub(0x8000)) as _
+        ((((self.code & 0xffff) ^ 0x8000).wrapping_sub(0x8000)) as i32) as _
     }
     #[inline(always)]
     pub fn field_ps_offset(&self) -> isize {
-        (((self.code & 0xfff) ^ 0x800).wrapping_sub(0x800)) as _
+        ((((self.code & 0xfff) ^ 0x800).wrapping_sub(0x800)) as i32) as _
     }
     #[inline(always)]
     pub fn field_BO(&self) -> usize {
@@ -5923,12 +5899,16 @@ impl Ins {
         ((self.code >> 16u8) & 0x1f) as _
     }
     #[inline(always)]
+    pub fn field_BH(&self) -> usize {
+        ((self.code >> 11u8) & 0x3) as _
+    }
+    #[inline(always)]
     pub fn field_BD(&self) -> isize {
-        (((((self.code >> 2u8) & 0x3fff) ^ 0x2000).wrapping_sub(0x2000)) << 2u8) as _
+        ((((((self.code >> 2u8) & 0x3fff) ^ 0x2000).wrapping_sub(0x2000)) as i32) << 2u8) as _
     }
     #[inline(always)]
     pub fn field_LI(&self) -> isize {
-        (((((self.code >> 2u8) & 0xffffff) ^ 0x800000).wrapping_sub(0x800000)) << 2u8) as _
+        ((((((self.code >> 2u8) & 0xffffff) ^ 0x800000).wrapping_sub(0x800000)) as i32) << 2u8) as _
     }
     #[inline(always)]
     pub fn field_SH(&self) -> usize {
@@ -6016,14 +5996,22 @@ impl Ins {
         ((self.code >> 12u8) & 0xff) as _
     }
     #[inline(always)]
-    pub fn field_ps_l(&self) -> usize {
+    pub fn field_ps_I(&self) -> usize {
         ((self.code >> 12u8) & 0x7) as _
     }
     #[inline(always)]
+    pub fn field_ps_IX(&self) -> usize {
+        ((self.code >> 7u8) & 0x7) as _
+    }
+    #[inline(always)]
     pub fn field_ps_W(&self) -> usize {
         ((self.code >> 15u8) & 0x1) as _
     }
     #[inline(always)]
+    pub fn field_ps_WX(&self) -> usize {
+        ((self.code >> 10u8) & 0x1) as _
+    }
+    #[inline(always)]
     pub fn field_NB(&self) -> usize {
         ((self.code >> 11u8) & 0x1f) as _
     }
@@ -6045,6 +6033,10 @@ impl Ins {
         ((self.code >> 21u8) & 0x1f) as _
     }
     #[inline(always)]
+    pub fn field_L(&self) -> usize {
+        ((self.code >> 21u8) & 0x1) as _
+    }
+    #[inline(always)]
     pub fn field_OE(&self) -> bool {
         self.bit(21usize)
     }
diff --git a/disasm/src/lib.rs b/disasm/src/lib.rs
index 5ba3526..aa55169 100644
--- a/disasm/src/lib.rs
+++ b/disasm/src/lib.rs
@@ -229,6 +229,8 @@ pub struct Ins {
 }
 
 impl Ins {
+    const BLR: u32 = 0x4e800020;
+
     /// Constructs an instruction from the given machine code and address.
     pub fn new(code: u32, addr: u32) -> Self {
         Self {
@@ -283,19 +285,24 @@ impl Ins {
 
     pub fn branch_dest(&self) -> Option<u32> {
         self.branch_offset().and_then(|offset| {
-            if offset < 0 {
-                self.addr.checked_sub((-offset) as u32)
+            if self.field_AA() {
+                Some(offset as u32)
             } else {
-                self.addr.checked_add(offset as u32)
+                if offset < 0 {
+                    self.addr.checked_sub((-offset) as u32)
+                } else {
+                    self.addr.checked_add(offset as u32)
+                }
             }
         })
     }
 
     pub fn is_branch(&self) -> bool {
-        match self.op {
-            Opcode::B | Opcode::Bc | Opcode::Bcctr | Opcode::Bclr => true,
-            _ => false,
-        }
+        matches!(self.op, Opcode::B | Opcode::Bc | Opcode::Bcctr | Opcode::Bclr)
+    }
+
+    pub fn is_direct_branch(&self) -> bool {
+        matches!(self.op, Opcode::B | Opcode::Bc)
     }
 
     pub fn is_unconditional_branch(&self) -> bool {
@@ -312,9 +319,10 @@ impl Ins {
         self.is_branch() && !self.is_unconditional_branch()
     }
 
+    #[inline]
     pub fn is_blr(&self) -> bool {
         // self.op == Opcode::Bclr && self.is_unconditional_branch() && !self.field_LK()
-        self.code == 0x4e800020
+        self.code == Ins::BLR
     }
 }
 
diff --git a/disasm/tests/test_disasm.rs b/disasm/tests/test_disasm.rs
index 31291ea..e0df349 100644
--- a/disasm/tests/test_disasm.rs
+++ b/disasm/tests/test_disasm.rs
@@ -94,6 +94,7 @@ fn test_ins_b() {
     assert_asm!(0x4823B4D9, "bl 0x23b4d8");
     assert_asm!(0x4BE03C99, "bl -0x1fc368");
     assert_asm!(0x4BDC1A59, "bl -0x23e5a8");
+    assert_asm!(0x48000063, "bla 0x60");
 }
 
 #[test]
@@ -482,7 +483,7 @@ fn test_ins_lwzx() {
 
 #[test]
 fn test_ins_mfcr() {
-    assert_asm!(0x7C000026, "mfcr cr0");
+    assert_asm!(0x7C000026, "mfcr r0");
 }
 
 #[test]
@@ -622,8 +623,8 @@ fn test_ins_psq_lx() {
             frD(FPR(0)),
             rA(GPR(0)),
             rB(GPR(0)),
-            ps_W(OpaqueU(0)),
-            ps_l(GQR(0))
+            ps_WX(OpaqueU(0)),
+            ps_IX(GQR(0))
         ]
     );
     assert_eq!(ins.defs(), vec![frD(FPR(0))]);
@@ -708,6 +709,11 @@ fn test_ins_ps_merge11() {
     assert_asm!(0x10AA14E0, "ps_merge11 f5, f10, f2");
 }
 
+#[test]
+fn test_ins_ps_mr() {
+    assert_asm!(0x10200090, "ps_mr f1, f0");
+}
+
 #[test]
 fn test_ins_ps_msub() {
     assert_asm!(0x10A53778, "ps_msub f5, f5, f29, f6");
@@ -783,6 +789,9 @@ fn test_ins_rlwimi() {
 fn test_ins_rlwinm() {
     assert_asm!(0x54000423, "rlwinm. r0, r0, 0, 16, 17");
     assert_asm!(0x54000432, "rlwinm r0, r0, 0, 16, 25");
+
+    // mnemonics
+    assert_asm!(0x57E5103A, "slwi r5, r31, 2");
 }
 
 #[test]
@@ -815,6 +824,7 @@ fn test_ins_srawi() {
 #[test]
 fn test_ins_srw() {
     assert_asm!(0x7C001C30, "srw r0, r0, r3");
+    assert_asm!(0x7C600430, "srw r0, r3, r0");
 }
 
 #[test]
@@ -957,6 +967,7 @@ fn test_ins_sync() {
 #[test]
 fn test_ins_xor() {
     assert_asm!(0x7C052A78, "xor r5, r0, r5");
+    assert_asm!(0x7D275279, "xor. r7, r9, r10");
 }
 
 #[test]
diff --git a/genisa/src/main.rs b/genisa/src/main.rs
index aaf807f..c15abde 100644
--- a/genisa/src/main.rs
+++ b/genisa/src/main.rs
@@ -136,7 +136,7 @@ impl Field {
         if self.signed {
             let mask2 = 1u32 << (self.bits.0.len() - 1);
             let mask2 = LitInt::new(&format!("0x{:x}", mask2), Span::call_site());
-            val = quote!(((#val ^ #mask2).wrapping_sub(#mask2)))
+            val = quote!((((#val ^ #mask2).wrapping_sub(#mask2)) as i32))
         }
 
         let val_shift = self.shift_left;
diff --git a/isa.yaml b/isa.yaml
index b5680d5..c39f470 100644
--- a/isa.yaml
+++ b/isa.yaml
@@ -22,6 +22,9 @@ fields:
   - name: BI
     arg: OpaqueU
     bits: 11..16
+  - name: BH
+    arg: OpaqueU
+    bits: 19..21
   - name: BD
     arg: BranchDest
     bits: 16..30
@@ -109,12 +112,18 @@ fields:
     arg: OpaqueU
     bits: 12..20
   # Paired single fields
-  - name: ps_l
+  - name: ps_I
     arg: GQR
     bits: 17..20
+  - name: ps_IX
+    arg: GQR
+    bits: 22..25
   - name: ps_W
     arg: OpaqueU
     bits: 16..17
+  - name: ps_WX
+    arg: OpaqueU
+    bits: 21..22
   # Misc
   - name: NB
     arg: OpaqueU
@@ -136,6 +145,10 @@ fields:
     arg: OpaqueU
     desc: Bitset for tw and twi
     bits: 6..11
+  - name: L
+    arg: OpaqueU
+    desc: Bitset for cmp, cmpi, cmpl, cmpli
+    bits: 10..11
   - name: xer
   - name: ctr
   - name: lr
@@ -274,14 +287,14 @@ opcodes:
     desc: Branch
     bitmask: 0xfc000000
     pattern: 0x48000000
-    modifiers: [ AA, LK ]
+    modifiers: [ LK, AA ]
     args: [ LI ]
 
   - name: bc
     desc: Branch Conditional
     bitmask: 0xfc000000
     pattern: 0x40000000
-    modifiers: [ AA, LK ]
+    modifiers: [ LK, AA ]
     args: [ BO, BI, BD ]
 
   - name: bcctr
@@ -289,7 +302,7 @@ opcodes:
     bitmask: 0xfc007ffe
     pattern: 0x4c000420
     modifiers: [ LK ]
-    args: [ BO, BI ]
+    args: [ BO, BI, BH ]
     uses: [ ctr ]
 
   - name: bclr
@@ -297,14 +310,14 @@ opcodes:
     bitmask: 0xfc007ffe
     pattern: 0x4c000020
     modifiers: [ LK ]
-    args: [ BO, BI ]
+    args: [ BO, BI, BH ]
     uses: [ lr ]
 
   - name: cmp
     desc: Compare
     bitmask: 0xfc4007ff
     pattern: 0x7c000000
-    args: [ crfD, rA, rB ]
+    args: [ crfD, L, rA, rB ]
     defs: [ crfD ]
     uses: [ rA, rB ]
 
@@ -312,7 +325,7 @@ opcodes:
     desc: Compare Immediate
     bitmask: 0xfc400000
     pattern: 0x2c000000
-    args: [ crfD, rA, simm ]
+    args: [ crfD, L, rA, simm ]
     defs: [ crfD ]
     uses: [ rA ]
 
@@ -320,7 +333,7 @@ opcodes:
     desc: Compare Logical
     bitmask: 0xfc4007ff
     pattern: 0x7c000040
-    args: [ crfD, rA, rB ]
+    args: [ crfD, L, rA, rB ]
     defs: [ crfD ]
     uses: [ rA, rB ]
 
@@ -328,7 +341,7 @@ opcodes:
     desc: Compare Logical Immediate
     bitmask: 0xfc400000
     pattern: 0x28000000
-    args: [ crfD, rA, uimm ]
+    args: [ crfD, L, rA, uimm ]
     defs: [ crfD ]
     uses: [ rA ]
 
@@ -1050,14 +1063,13 @@ opcodes:
     desc: Move from Condition Register
     bitmask: 0xfc1fffff
     pattern: 0x7c000026
-    args: [ crfD ]
-    defs: [ crfD ]
+    args: [ rD ]
+    defs: [ rD ]
 
   - name: mffs
     desc: Move from FPSCR
     bitmask: 0xfc1ffffe
     pattern: 0xfc00048e
-    modifiers: [ Rc ]
     args: [ frD ]
     defs: [ frD ]
 
@@ -1186,7 +1198,6 @@ opcodes:
     desc: Multiply Low Immediate
     bitmask: 0xfc000000
     pattern: 0x1c000000
-    modifiers: [ Rc ]
     args: [ rD, rA, simm ]
     defs: [ rD ]
     uses: [ rA ]
@@ -1265,7 +1276,7 @@ opcodes:
     desc: Paired Single Quantized Load
     bitmask: 0xfc000000
     pattern: 0xe0000000
-    args: [ frD, ps_offset, rA, ps_W, ps_l ]
+    args: [ frD, ps_offset, rA, ps_W, ps_I ]
     defs: [ frD ]
     uses: [ rA.nz ]
 
@@ -1273,7 +1284,7 @@ opcodes:
     desc: Paired Single Quantized Load with Update
     bitmask: 0xfc000000
     pattern: 0xe4000000
-    args: [ frD, ps_offset, rA, ps_W, ps_l ]
+    args: [ frD, ps_offset, rA, ps_W, ps_I ]
     defs: [ frD, rA ]
     uses: [ rA ]
 
@@ -1281,7 +1292,7 @@ opcodes:
     desc: Paired Single Quantized Load with Update Indexed
     bitmask: 0xfc00007f
     pattern: 0x1000004c
-    args: [ frD, rA, rB, ps_W, ps_l ]
+    args: [ frD, rA, rB, ps_WX, ps_IX ]
     defs: [ frD, rA ]
     uses: [ rA, rB ]
 
@@ -1289,7 +1300,7 @@ opcodes:
     desc: Paired Single Quantized Load Indexed
     bitmask: 0xfc00007f
     pattern: 0x1000000c
-    args: [ frD, rA, rB, ps_W, ps_l ]
+    args: [ frD, rA, rB, ps_WX, ps_IX ]
     defs: [ frD ]
     uses: [ rA.nz, rB ]
 
@@ -1297,14 +1308,14 @@ opcodes:
     desc: Paired Single Quantized Store
     bitmask: 0xfc000000
     pattern: 0xf0000000
-    args: [ frS, ps_offset, rA, ps_W, ps_l ]
+    args: [ frS, ps_offset, rA, ps_W, ps_I ]
     uses: [ frS, rA.nz ]
 
   - name: psq_stu
     desc: Paired Single Quantized Store with Update
     bitmask: 0xfc000000
     pattern: 0xf4000000
-    args: [ frS, ps_offset, rA, ps_W, ps_l ]
+    args: [ frS, ps_offset, rA, ps_W, ps_I ]
     defs: [ rA ]
     uses: [ frS, rA ]
 
@@ -1312,7 +1323,7 @@ opcodes:
     desc: Paired Single Quantized Store with Update Indexed
     bitmask: 0xfc00007f
     pattern: 0x1000004e
-    args: [ frS, rA, rB, ps_W, ps_l ]
+    args: [ frS, rA, rB, ps_WX, ps_IX ]
     defs: [ rA ]
     uses: [ frS, rA, rB ]
 
@@ -1320,14 +1331,13 @@ opcodes:
     desc: Paired Single Quantized Store Indexed
     bitmask: 0xfc00007f
     pattern: 0x1000000e
-    args: [ frS, rA, rB, ps_W, ps_l ]
+    args: [ frS, rA, rB, ps_WX, ps_IX ]
     uses: [ frS, rA.nz, rB ]
 
   - name: ps_abs
     desc: Paired Single Absolute Value
     bitmask: 0xfc1f07fe
     pattern: 0x10000210
-    modifiers: [ Rc ]
     args: [ frD, frB ]
     defs: [ frD ]
     uses: [ frB ]
@@ -1336,7 +1346,6 @@ opcodes:
     desc: Paired Single Add
     bitmask: 0xfc0007fe
     pattern: 0x1000002a
-    modifiers: [ Rc ]
     args: [ frD, frA, frB ]
     defs: [ frD ]
     uses: [ frA, frB ]
@@ -1377,7 +1386,6 @@ opcodes:
     desc: Paired Single Divide
     bitmask: 0xfc0007fe
     pattern: 0x10000024
-    modifiers: [ Rc ]
     args: [ frD, frA, frB ]
     defs: [ frD ]
     uses: [ frA, frB ]
@@ -1386,7 +1394,6 @@ opcodes:
     desc: Paired Single Multiply-Add
     bitmask: 0xfc00003e
     pattern: 0x1000003a
-    modifiers: [ Rc ]
     args: [ frD, frA, frC, frB ]
     defs: [ frD ]
     uses: [ frA, frC, frB ]
@@ -1395,7 +1402,6 @@ opcodes:
     desc: Paired Single Multiply-Add Scalar high
     bitmask: 0xfc00003e
     pattern: 0x1000001c
-    modifiers: [ Rc ]
     args: [ frD, frA, frC, frB ]
     defs: [ frD ]
     uses: [ frA, frC, frB ]
@@ -1404,7 +1410,6 @@ opcodes:
     desc: Paired Single Multiply-Add Scalar low
     bitmask: 0xfc00003e
     pattern: 0x1000001e
-    modifiers: [ Rc ]
     args: [ frD, frA, frC, frB ]
     defs: [ frD ]
     uses: [ frA, frC, frB ]
@@ -1413,7 +1418,6 @@ opcodes:
     desc: Paired Single MERGE high
     bitmask: 0xfc0007fe
     pattern: 0x10000420
-    modifiers: [ Rc ]
     args: [ frD, frA, frB ]
     defs: [ frD ]
     uses: [ frA, frB ]
@@ -1422,7 +1426,6 @@ opcodes:
     desc: Paired Single MERGE direct
     bitmask: 0xfc0007fe
     pattern: 0x10000460
-    modifiers: [ Rc ]
     args: [ frD, frA, frB ]
     defs: [ frD ]
     uses: [ frA, frB ]
@@ -1431,7 +1434,6 @@ opcodes:
     desc: Paired Single MERGE swapped
     bitmask: 0xfc0007fe
     pattern: 0x100004a0
-    modifiers: [ Rc ]
     args: [ frD, frA, frB ]
     defs: [ frD ]
     uses: [ frA, frB ]
@@ -1440,7 +1442,6 @@ opcodes:
     desc: Paired Single MERGE low
     bitmask: 0xfc0007fe
     pattern: 0x100004e0
-    modifiers: [ Rc ]
     args: [ frD, frA, frB ]
     defs: [ frD ]
     uses: [ frA, frB ]
@@ -1449,8 +1450,7 @@ opcodes:
     desc: Paired Single Move Register
     bitmask: 0xfc1f07fe
     pattern: 0x10000090
-    modifiers: [ Rc ]
-    args: [ frD, frA, frB ]
+    args: [ frD, frB ]
     defs: [ frD ]
     uses: [ frB ]
 
@@ -1458,7 +1458,6 @@ opcodes:
     desc: Paired Single Multiply-Subtract
     bitmask: 0xfc00003e
     pattern: 0x10000038
-    modifiers: [ Rc ]
     args: [ frD, frA, frC, frB ]
     defs: [ frD ]
     uses: [ frA, frC, frB ]
@@ -1467,7 +1466,6 @@ opcodes:
     desc: Paired Single Multiply
     bitmask: 0xfc00f83e
     pattern: 0x10000032
-    modifiers: [ Rc ]
     args: [ frD, frA, frC ]
     defs: [ frD ]
     uses: [ frA, frC ]
@@ -1476,7 +1474,6 @@ opcodes:
     desc: Paired Single Multiply Scalar high
     bitmask: 0xfc00f83e
     pattern: 0x10000018
-    modifiers: [ Rc ]
     args: [ frD, frA, frC ]
     defs: [ frD ]
     uses: [ frA, frC ]
@@ -1485,7 +1482,6 @@ opcodes:
     desc: Paired Single Multiply Scalar low
     bitmask: 0xfc00f83e
     pattern: 0x1000001a
-    modifiers: [ Rc ]
     args: [ frD, frA, frC ]
     defs: [ frD ]
     uses: [ frA, frC ]
@@ -1494,7 +1490,6 @@ opcodes:
     desc: Paired Single Negative Absolute Value
     bitmask: 0xfc1f07fe
     pattern: 0x10000110
-    modifiers: [ Rc ]
     args: [ frD, frB ]
     defs: [ frD ]
     uses: [ frB ]
@@ -1503,7 +1498,6 @@ opcodes:
     desc: Paired Single Negate
     bitmask: 0xfc1f07fe
     pattern: 0x10000050
-    modifiers: [ Rc ]
     args: [ frD, frB ]
     defs: [ frD ]
     uses: [ frB ]
@@ -1512,7 +1506,6 @@ opcodes:
     desc: Paired Single Negative Multiply-Add
     bitmask: 0xfc00003e
     pattern: 0x1000003e
-    modifiers: [ Rc ]
     args: [ frD, frA, frC, frB ]
     defs: [ frD ]
     uses: [ frA, frC, frB ]
@@ -1521,7 +1514,6 @@ opcodes:
     desc: Paired Single Negative Multiply-Subtract
     bitmask: 0xfc00003e
     pattern: 0x1000003c
-    modifiers: [ Rc ]
     args: [ frD, frA, frC, frB ]
     defs: [ frD ]
     uses: [ frA, frC, frB ]
@@ -1530,7 +1522,6 @@ opcodes:
     desc: Paired Single Reciprocal Estimate
     bitmask: 0xfc1f07fe
     pattern: 0x10000030
-    modifiers: [ Rc ]
     args: [ frD, frB ]
     defs: [ frD ]
     uses: [ frB ]
@@ -1539,7 +1530,6 @@ opcodes:
     desc: Paired Single Reciprocal Square Root Estimate
     bitmask: 0xfc1f07fe
     pattern: 0x10000034
-    modifiers: [ Rc ]
     args: [ frD, frB ]
     defs: [ frD ]
     uses: [ frB ]
@@ -1548,7 +1538,6 @@ opcodes:
     desc: Paired Single Select
     bitmask: 0xfc00003e
     pattern: 0x1000002e
-    modifiers: [ Rc ]
     args: [ frD, frA, frC, frB ]
     defs: [ frD ]
     uses: [ frA, frC, frB ]
@@ -1557,7 +1546,6 @@ opcodes:
     desc: Paired Single Subtract
     bitmask: 0xfc0007fe
     pattern: 0x10000028
-    modifiers: [ Rc ]
     args: [ frD, frA, frB ]
     defs: [ frD ]
     uses: [ frA, frB ]
@@ -1566,7 +1554,6 @@ opcodes:
     desc: Paired Single vector SUM high
     bitmask: 0xfc00003e
     pattern: 0x10000014
-    modifiers: [ Rc ]
     args: [ frD, frA, frC, frB ]
     defs: [ frD ]
     uses: [ frA, frC, frB ]
@@ -1575,7 +1562,6 @@ opcodes:
     desc: Paired Single vector SUM low
     bitmask: 0xfc00003e
     pattern: 0x10000016
-    modifiers: [ Rc ]
     args: [ frD, frA, frC, frB ]
     defs: [ frD ]
     uses: [ frA, frC, frB ]
@@ -1649,7 +1635,7 @@ opcodes:
     bitmask: 0xfc0007fe
     pattern: 0x7c000430
     modifiers: [ Rc ]
-    args: [ rS, rA, rB ]
+    args: [ rA, rS, rB ]
     defs: [ rA ]
     uses: [ rA, rB ]
 
@@ -1940,6 +1926,7 @@ opcodes:
     desc: XOR
     bitmask: 0xfc0007fe
     pattern: 0x7c000278
+    modifiers: [ Rc ]
     args: [ rA, rS, rB ]
     defs: [ rA ]
     uses: [ rS, rB ]
@@ -1989,44 +1976,80 @@ mnemonics:
     condition: MB == 0 && ME == 31
   - name: slwi
     opcode: rlwinm
-    args: [ rA, rS, ME ]
+    args: [ rA, rS, SH ]
     condition: MB == 0 && 31 - SH == ME
   - name: srwi
     opcode: rlwinm
     args: [ rA, rS, MB ]
     condition: ME == 31 && 32 - MB == SH
 
-  # Compares
-  - name: cmpw
-    opcode: cmp
-    args: [ rA, rB ]
-    condition: crfD == 0
-  - name: cmpw
-    opcode: cmp
-    args: [ crfD, rA, rB ]
-  - name: cmplw
-    opcode: cmpl
-    args: [ rA, rB ]
-    condition: crfD == 0
-  - name: cmplw
-    opcode: cmpl
-    args: [ crfD, rA, rB ]
+  # Compares Word
   - name: cmpwi
     opcode: cmpi
     args: [ rA, simm ]
-    condition: crfD == 0
+    condition: crfD == 0 && L == 0
   - name: cmpwi
     opcode: cmpi
     args: [ crfD, rA, simm ]
-    condition: crfD == 0
+    condition: L == 0
+  - name: cmpw
+    opcode: cmp
+    args: [ rA, rB ]
+    condition: crfD == 0 && L == 0
+  - name: cmpw
+    opcode: cmp
+    args: [ crfD, rA, rB ]
+    condition: L == 0
   - name: cmplwi
     opcode: cmpli
     args: [ rA, uimm ]
-    condition: crfD == 0
+    condition: crfD == 0 && L == 0
   - name: cmplwi
     opcode: cmpli
     args: [ crfD, rA, uimm ]
-    condition: crfD == 0
+    condition: L == 0
+  - name: cmplw
+    opcode: cmpl
+    args: [ rA, rB ]
+    condition: crfD == 0 && L == 0
+  - name: cmplw
+    opcode: cmpl
+    args: [ crfD, rA, rB ]
+    condition: L == 0
+
+  # Compares Doubleword
+  - name: cmpdi
+    opcode: cmpi
+    args: [ rA, simm ]
+    condition: crfD == 0 && L == 1
+  - name: cmpdi
+    opcode: cmpi
+    args: [ crfD, rA, simm ]
+    condition: L == 1
+  - name: cmpd
+    opcode: cmp
+    args: [ rA, rB ]
+    condition: crfD == 0 && L == 1
+  - name: cmpd
+    opcode: cmp
+    args: [ crfD, rA, rB ]
+    condition: L == 1
+  - name: cmpldi
+    opcode: cmpli
+    args: [ rA, uimm ]
+    condition: crfD == 0 && L == 1
+  - name: cmpldi
+    opcode: cmpli
+    args: [ crfD, rA, uimm ]
+    condition: L == 1
+  - name: cmpld
+    opcode: cmpl
+    args: [ rA, rB ]
+    condition: crfD == 0 && L == 1
+  - name: cmpld
+    opcode: cmpl
+    args: [ crfD, rA, rB ]
+    condition: L == 1
 
   # Condition Register Logical
   - name: crset
@@ -2080,10 +2103,6 @@ mnemonics:
     opcode: mtspr
     args: [ rS ]
     condition: spr == 397
-  - name: mttdu
-    opcode: mtspr
-    args: [ rS ]
-    condition: spr == 571
 
   # Move from special-purpose register
   - name: mfxer
@@ -2106,114 +2125,110 @@ mnemonics:
     opcode: mfspr
     args: [ rD ]
     condition: spr == 397
-  - name: mftdu
-    opcode: mfspr
-    args: [ rD ]
-    condition: spr == 571
 
   # Branch Conditional
   # bc branch always
   - name: b
     opcode: bc
-    modifiers: [ AA, LK ]
+    modifiers: [ LK, AA ]
     condition: BO == 20 && BI == 0
   # bc branch if negative
   - name: blt
     opcode: bc
-    modifiers: [ AA, LK ]
+    modifiers: [ LK, AA ]
     args: [ BD ]
     condition: BO == 12 && BI & 0b11 == 0b00 && crfS == 0
   - name: blt
     opcode: bc
-    modifiers: [ AA, LK ]
+    modifiers: [ LK, AA ]
     args: [ crfS, BD ]
     condition: BO == 12 && BI & 0b11 == 0b00
   # bc branch if not positive
   - name: ble
     opcode: bc
-    modifiers: [ AA, LK ]
+    modifiers: [ LK, AA ]
     args: [ BD ]
     condition: BO == 4 && BI & 0b11 == 0b01 && crfS == 0
   - name: ble
     opcode: bc
-    modifiers: [ AA, LK ]
+    modifiers: [ LK, AA ]
     args: [ crfS, BD ]
     condition: BO == 4 && BI & 0b11 == 0b01
   # bc branch if zero
   - name: beq
     opcode: bc
-    modifiers: [ AA, LK ]
+    modifiers: [ LK, AA ]
     args: [ BD ]
     condition: BO == 12 && BI & 0b11 == 0b10 && crfS == 0
   - name: beq
     opcode: bc
-    modifiers: [ AA, LK ]
+    modifiers: [ LK, AA ]
     args: [ crfS, BD ]
     condition: BO == 12 && BI & 0b11 == 0b10
   # bc branch if not negative
   - name: bge
     opcode: bc
-    modifiers: [ AA, LK ]
+    modifiers: [ LK, AA ]
     args: [ BD ]
     condition: BO == 4 && BI & 0b11 == 0b00 && crfS == 0
   - name: bge
     opcode: bc
-    modifiers: [ AA, LK ]
+    modifiers: [ LK, AA ]
     args: [ crfS, BD ]
     condition: BO == 4 && BI & 0b11 == 0b00
   # bc branch if positive
   - name: bgt
     opcode: bc
-    modifiers: [ AA, LK ]
+    modifiers: [ LK, AA ]
     args: [ BD ]
     condition: BO == 12 && BI & 0b11 == 0b01 && crfS == 0
   - name: bgt
     opcode: bc
-    modifiers: [ AA, LK ]
+    modifiers: [ LK, AA ]
     args: [ crfS, BD ]
     condition: BO == 12 && BI & 0b11 == 0b01
   # bc branch if not zero
   - name: bne
     opcode: bc
-    modifiers: [ AA, LK ]
+    modifiers: [ LK, AA ]
     args: [ BD ]
     condition: BO == 4 && BI & 0b11 == 0b10 && crfS == 0
   - name: bne
     opcode: bc
-    modifiers: [ AA, LK ]
+    modifiers: [ LK, AA ]
     args: [ crfS, BD ]
     condition: BO == 4 && BI & 0b11 == 0b10
   # bc branch if summary overflow
   - name: bso
     opcode: bc
-    modifiers: [ AA, LK ]
+    modifiers: [ LK, AA ]
     args: [ BD ]
     condition: BO == 12 && BI & 0b11 == 0b11 && crfS == 0
   - name: bso
     opcode: bc
-    modifiers: [ AA, LK ]
+    modifiers: [ LK, AA ]
     args: [ crfS, BD ]
     condition: BO == 12 && BI & 0b11 == 0b11
   # bc branch if not summary overflow
   - name: bns
     opcode: bc
-    modifiers: [ AA, LK ]
+    modifiers: [ LK, AA ]
     args: [ BD ]
     condition: BO == 4 && BI & 0b11 == 0b11 && crfS == 0
   - name: bns
     opcode: bc
-    modifiers: [ AA, LK ]
+    modifiers: [ LK, AA ]
     args: [ crfS, BD ]
     condition: BO == 4 && BI & 0b11 == 0b11
 
   - name: bdnz
     opcode: bc
-    modifiers: [ AA, LK ]
+    modifiers: [ LK, AA ]
     args: [ BD ]
     condition: BO == 16 && BI == 0
   - name: bdz
     opcode: bc
-    modifiers: [ AA, LK ]
+    modifiers: [ LK, AA ]
     args: [ BD ]
     condition: BO == 18 && BI == 0
   # TODO support conditional bd...