From 7167807402a703ed9b7568acef4d7c249da57f87 Mon Sep 17 00:00:00 2001 From: InusualZ Date: Tue, 31 May 2022 19:17:42 -0400 Subject: [PATCH] isa: fix `mfcr` argument --- disasm/src/generated.rs | 4 ++-- disasm/tests/test_disasm.rs | 2 +- isa.yaml | 4 ++-- 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/disasm/src/generated.rs b/disasm/src/generated.rs index 828a060..24b5064 100644 --- a/disasm/src/generated.rs +++ b/disasm/src/generated.rs @@ -1823,7 +1823,7 @@ impl Ins { Field::crfS(CRField(((self.code >> 18u8) & 0x7) as _)), ], Opcode::Mcrxr => vec![Field::crfD(CRField(((self.code >> 23u8) & 0x7) as _))], - Opcode::Mfcr => vec![Field::crfD(CRField(((self.code >> 23u8) & 0x7) as _))], + Opcode::Mfcr => vec![Field::rD(GPR(((self.code >> 21u8) & 0x1f) as _))], Opcode::Mffs => vec![Field::frD(FPR(((self.code >> 21u8) & 0x1f) as _))], Opcode::Mfmsr => vec![Field::rD(GPR(((self.code >> 21u8) & 0x1f) as _))], Opcode::Mfspr => vec![ @@ -2562,7 +2562,7 @@ impl Ins { Field::crfD(CRField(((self.code >> 23u8) & 0x7) as _)), Field::xer, ], - Opcode::Mfcr => vec![Field::crfD(CRField(((self.code >> 23u8) & 0x7) as _))], + Opcode::Mfcr => vec![Field::rD(GPR(((self.code >> 21u8) & 0x1f) as _))], Opcode::Mffs => vec![Field::frD(FPR(((self.code >> 21u8) & 0x1f) as _))], Opcode::Mfmsr => vec![Field::rD(GPR(((self.code >> 21u8) & 0x1f) as _))], Opcode::Mfspr => vec![Field::rD(GPR(((self.code >> 21u8) & 0x1f) as _))], diff --git a/disasm/tests/test_disasm.rs b/disasm/tests/test_disasm.rs index 96bb7cc..95b5e92 100644 --- a/disasm/tests/test_disasm.rs +++ b/disasm/tests/test_disasm.rs @@ -483,7 +483,7 @@ fn test_ins_lwzx() { #[test] fn test_ins_mfcr() { - assert_asm!(0x7C000026, "mfcr cr0"); + assert_asm!(0x7C000026, "mfcr r0"); } #[test] diff --git a/isa.yaml b/isa.yaml index f2cac8b..37b067f 100644 --- a/isa.yaml +++ b/isa.yaml @@ -1063,8 +1063,8 @@ opcodes: desc: Move from Condition Register bitmask: 0xfc1fffff pattern: 0x7c000026 - args: [ crfD ] - defs: [ crfD ] + args: [ rD ] + defs: [ rD ] - name: mffs desc: Move from FPSCR