From 86e081fdb2095b28c106a3c25a88c15afae7a996 Mon Sep 17 00:00:00 2001
From: InusualZ <wesmoret98@gmail.com>
Date: Tue, 31 May 2022 19:44:21 -0400
Subject: [PATCH] isa: fix `rlwinm`'s mnemonic `slwi` using `ME` instead of
 `SH` as arg

---
 disasm/src/generated.rs     | 2 +-
 disasm/tests/test_disasm.rs | 3 +++
 isa.yaml                    | 2 +-
 3 files changed, 5 insertions(+), 2 deletions(-)

diff --git a/disasm/src/generated.rs b/disasm/src/generated.rs
index 40ab7ef..395afa6 100644
--- a/disasm/src/generated.rs
+++ b/disasm/src/generated.rs
@@ -5843,7 +5843,7 @@ impl Ins {
                         args: vec![
                             Argument::GPR(GPR(((self.code >> 16u8) & 0x1f) as _)),
                             Argument::GPR(GPR(((self.code >> 21u8) & 0x1f) as _)),
-                            Argument::OpaqueU(OpaqueU(((self.code >> 1u8) & 0x1f) as _)),
+                            Argument::OpaqueU(OpaqueU(((self.code >> 11u8) & 0x1f) as _)),
                         ],
                         ins: self,
                     };
diff --git a/disasm/tests/test_disasm.rs b/disasm/tests/test_disasm.rs
index 574be34..02dc22c 100644
--- a/disasm/tests/test_disasm.rs
+++ b/disasm/tests/test_disasm.rs
@@ -784,6 +784,9 @@ fn test_ins_rlwimi() {
 fn test_ins_rlwinm() {
     assert_asm!(0x54000423, "rlwinm. r0, r0, 0, 16, 17");
     assert_asm!(0x54000432, "rlwinm r0, r0, 0, 16, 25");
+
+    // mnemonics
+    assert_asm!(0x57E5103A, "slwi r5, r31, 2");
 }
 
 #[test]
diff --git a/isa.yaml b/isa.yaml
index 3866a18..c70de96 100644
--- a/isa.yaml
+++ b/isa.yaml
@@ -1976,7 +1976,7 @@ mnemonics:
     condition: MB == 0 && ME == 31
   - name: slwi
     opcode: rlwinm
-    args: [ rA, rS, ME ]
+    args: [ rA, rS, SH ]
     condition: MB == 0 && 31 - SH == ME
   - name: srwi
     opcode: rlwinm