From 88c6a478e21e08c4bf1e718ded31c0af6a330979 Mon Sep 17 00:00:00 2001 From: Richard Patel Date: Sat, 9 Apr 2022 16:30:48 +0200 Subject: [PATCH] disasm-py: support fields --- README.md | 5 +- disasm-py/src/lib.rs | 149 +++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 153 insertions(+), 1 deletion(-) diff --git a/README.md b/README.md index 9bb37e5..2fe13c9 100644 --- a/README.md +++ b/README.md @@ -25,8 +25,11 @@ Install module in dev env maturin develop -m ./disasm-py/Cargo.toml python >>> import ppc750cl ->>> str(ppc750cl.Ins(addr=0x80006969, code=0x10400420)) +>>> ins = ppc750cl.Ins(addr=0x80006969, code=0x10400420) +>>> str(ins) 'ps_merge00 f2, f0, f0' +>>> ins.frD +2 ``` ### Instruction Set diff --git a/disasm-py/src/lib.rs b/disasm-py/src/lib.rs index 51c6081..cbd1fa8 100644 --- a/disasm-py/src/lib.rs +++ b/disasm-py/src/lib.rs @@ -33,6 +33,155 @@ impl Ins { } } +#[allow(non_snake_case)] +#[pymethods] +impl Ins { + #[getter] + fn simm(&self) -> i64 { + self.0.field_simm() as i64 + } + #[getter] + fn uimm(&self) -> i64 { + self.0.field_uimm() as i64 + } + #[getter] + fn offset(&self) -> i64 { + self.0.field_offset() as i64 + } + #[getter] + fn ps_offset(&self) -> i64 { + self.0.field_ps_offset() as i64 + } + #[getter] + fn BO(&self) -> i64 { + self.0.field_BO() as i64 + } + #[getter] + fn BI(&self) -> i64 { + self.0.field_BI() as i64 + } + #[getter] + fn BD(&self) -> i64 { + self.0.field_BD() as i64 + } + #[getter] + fn LI(&self) -> i64 { + self.0.field_LI() as i64 + } + #[getter] + fn SH(&self) -> i64 { + self.0.field_SH() as i64 + } + #[getter] + fn MB(&self) -> i64 { + self.0.field_SH() as i64 + } + #[getter] + fn ME(&self) -> i64 { + self.0.field_SH() as i64 + } + #[getter] + fn rS(&self) -> i64 { + self.0.field_rS() as i64 + } + #[getter] + fn rD(&self) -> i64 { + self.0.field_rD() as i64 + } + #[getter] + fn rA(&self) -> i64 { + self.0.field_rA() as i64 + } + #[getter] + fn rB(&self) -> i64 { + self.0.field_rB() as i64 + } + #[getter] + fn rC(&self) -> i64 { + self.0.field_rC() as i64 + } + #[getter] + fn sr(&self) -> i64 { + self.0.field_sr() as i64 + } + #[getter] + fn spr(&self) -> i64 { + self.0.field_spr() as i64 + } + #[getter] + fn frS(&self) -> i64 { + self.0.field_frS() as i64 + } + #[getter] + fn frD(&self) -> i64 { + self.0.field_frD() as i64 + } + #[getter] + fn frA(&self) -> i64 { + self.0.field_frA() as i64 + } + #[getter] + fn frB(&self) -> i64 { + self.0.field_frB() as i64 + } + #[getter] + fn frC(&self) -> i64 { + self.0.field_frC() as i64 + } + #[getter] + fn crbD(&self) -> i64 { + self.0.field_crbD() as i64 + } + #[getter] + fn crbA(&self) -> i64 { + self.0.field_crbA() as i64 + } + #[getter] + fn crbB(&self) -> i64 { + self.0.field_crbB() as i64 + } + #[getter] + fn crfD(&self) -> i64 { + self.0.field_crfD() as i64 + } + #[getter] + fn crfS(&self) -> i64 { + self.0.field_crfS() as i64 + } + #[getter] + fn crm(&self) -> i64 { + self.0.field_crm() as i64 + } + #[getter] + fn ps_l(&self) -> i64 { + self.0.field_ps_l() as i64 + } + #[getter] + fn ps_W(&self) -> i64 { + self.0.field_ps_W() as i64 + } + #[getter] + fn ps_NB(&self) -> i64 { + self.0.field_NB() as i64 + } + #[getter] + fn tbr(&self) -> i64 { + self.0.field_tbr() as i64 + } + #[getter] + fn mtfsf_FM(&self) -> i64 { + self.0.field_mtfsf_FM() as i64 + } + #[getter] + fn mtfsf_IMM(&self) -> i64 { + self.0.field_mtfsf_IMM() as i64 + } + #[getter] + fn TO(&self) -> i64 { + self.0.field_TO() as i64 + } +} + impl From for Ins { fn from(ins: ppc750cl::Ins) -> Self { Self(ins)