From a9ae0cb8a151b99f0cbea61531201bd834f26fb6 Mon Sep 17 00:00:00 2001
From: InusualZ <wesmoret98@gmail.com>
Date: Tue, 31 May 2022 19:36:21 -0400
Subject: [PATCH] isa: add `RC` modifier to the `xor` instruction

---
 disasm/src/generated.rs     | 8 +++++++-
 disasm/tests/test_disasm.rs | 1 +
 isa.yaml                    | 1 +
 3 files changed, 9 insertions(+), 1 deletion(-)

diff --git a/disasm/src/generated.rs b/disasm/src/generated.rs
index 71fd1cb..40ab7ef 100644
--- a/disasm/src/generated.rs
+++ b/disasm/src/generated.rs
@@ -4807,7 +4807,13 @@ impl Ins {
             Opcode::Tlbsync => String::new(),
             Opcode::Tw => String::new(),
             Opcode::Twi => String::new(),
-            Opcode::Xor => String::new(),
+            Opcode::Xor => {
+                let mut s = String::with_capacity(4);
+                if self.bit(31usize) {
+                    s.push('.');
+                }
+                s
+            }
             Opcode::Xori => String::new(),
             Opcode::Xoris => String::new(),
         }
diff --git a/disasm/tests/test_disasm.rs b/disasm/tests/test_disasm.rs
index f19980a..574be34 100644
--- a/disasm/tests/test_disasm.rs
+++ b/disasm/tests/test_disasm.rs
@@ -959,6 +959,7 @@ fn test_ins_sync() {
 #[test]
 fn test_ins_xor() {
     assert_asm!(0x7C052A78, "xor r5, r0, r5");
+    assert_asm!(0x7D275279, "xor. r7, r9, r10");
 }
 
 #[test]
diff --git a/isa.yaml b/isa.yaml
index 49ba4f2..3866a18 100644
--- a/isa.yaml
+++ b/isa.yaml
@@ -1926,6 +1926,7 @@ opcodes:
     desc: XOR
     bitmask: 0xfc0007fe
     pattern: 0x7c000278
+    modifiers: [ Rc ]
     args: [ rA, rS, rB ]
     defs: [ rA ]
     uses: [ rS, rB ]