From aa631a33de7882c679afca89350898b87cb3ba3f Mon Sep 17 00:00:00 2001
From: Luke Street <luke.street@encounterpc.com>
Date: Sun, 16 Oct 2022 14:21:50 -0400
Subject: [PATCH] Fix clrlslwi decoding

---
 disasm/src/generated.rs     | 49 +++++++++++++++++++------------------
 disasm/tests/test_disasm.rs |  4 ++-
 isa.yaml                    |  8 +++---
 3 files changed, 32 insertions(+), 29 deletions(-)

diff --git a/disasm/src/generated.rs b/disasm/src/generated.rs
index 851f89d..c24c5be 100644
--- a/disasm/src/generated.rs
+++ b/disasm/src/generated.rs
@@ -7408,30 +7408,6 @@ impl Ins {
                         ins: self,
                     };
                 }
-                if ((self.code >> 11u8) & 0x1f) < 32
-                    && ((self.code >> 6u8) & 0x1f) >= ((self.code >> 11u8) & 0x1f)
-                    && ((self.code >> 1u8) & 0x1f) == 31 - ((self.code >> 11u8) & 0x1f)
-                {
-                    return SimplifiedIns {
-                        mnemonic: "clrlslwi",
-                        suffix: {
-                            {
-                                let mut s = String::with_capacity(4);
-                                if self.bit(31usize) {
-                                    s.push('.');
-                                }
-                                s
-                            }
-                        },
-                        args: vec![
-                            Argument::GPR(GPR(((self.code >> 16u8) & 0x1f) as _)),
-                            Argument::GPR(GPR(((self.code >> 21u8) & 0x1f) as _)),
-                            Argument::OpaqueU(OpaqueU((32 - ((self.code >> 11u8) & 0x1f)) as _)),
-                            Argument::OpaqueU(OpaqueU(((self.code >> 11u8) & 0x1f) as _)),
-                        ],
-                        ins: self,
-                    };
-                }
                 if ((self.code >> 6u8) & 0x1f) == 0
                     && ((self.code >> 1u8) & 0x1f) == 31
                     && ((self.code >> 11u8) & 0x1f) <= 16
@@ -7522,6 +7498,31 @@ impl Ins {
                         ins: self,
                     };
                 }
+                if ((self.code >> 11u8) & 0x1f) < 32
+                    && ((self.code >> 1u8) & 0x1f) == 31 - ((self.code >> 11u8) & 0x1f)
+                {
+                    return SimplifiedIns {
+                        mnemonic: "clrlslwi",
+                        suffix: {
+                            {
+                                let mut s = String::with_capacity(4);
+                                if self.bit(31usize) {
+                                    s.push('.');
+                                }
+                                s
+                            }
+                        },
+                        args: vec![
+                            Argument::GPR(GPR(((self.code >> 16u8) & 0x1f) as _)),
+                            Argument::GPR(GPR(((self.code >> 21u8) & 0x1f) as _)),
+                            Argument::OpaqueU(OpaqueU(
+                                (((self.code >> 6u8) & 0x1f) + ((self.code >> 11u8) & 0x1f)) as _,
+                            )),
+                            Argument::OpaqueU(OpaqueU(((self.code >> 11u8) & 0x1f) as _)),
+                        ],
+                        ins: self,
+                    };
+                }
                 if ((self.code >> 6u8) & 0x1f) == 0 {
                     return SimplifiedIns {
                         mnemonic: "extlwi",
diff --git a/disasm/tests/test_disasm.rs b/disasm/tests/test_disasm.rs
index c68c3d8..783f623 100644
--- a/disasm/tests/test_disasm.rs
+++ b/disasm/tests/test_disasm.rs
@@ -861,7 +861,9 @@ fn test_ins_rlwinm() {
     assert_asm!(0x5483E03E, "rotrwi r3, r4, 4");
     assert_asm!(0x5464043E, "clrlwi r4, r3, 16");
     assert_asm!(0x54830036, "clrrwi r3, r4, 4");
-    assert_asm!(0x54640fbc, "clrlslwi r4, r3, 31, 1");
+    assert_asm!(0x54640FBC, "clrlslwi r4, r3, 31, 1");
+    assert_asm!(0x54092DB4, "clrlslwi r9, r0, 27, 5");
+    assert_asm!(0x54096226, "clrlslwi r9, r0, 20, 12");
 }
 
 #[test]
diff --git a/isa.yaml b/isa.yaml
index 2c28fc6..93715ca 100644
--- a/isa.yaml
+++ b/isa.yaml
@@ -2002,10 +2002,6 @@ mnemonics:
     opcode: rlwinm
     args: [ rA, rS, MB ]
     condition: SH == 0 && ME == 31
-  - name: clrlslwi
-    opcode: rlwinm
-    args: [ rA, rS, MB=32-SH, SH ]
-    condition: SH < 32 && MB >= SH && ME == 31 - SH
   - name: rotlwi
     opcode: rlwinm
     args: [ rA, rS, SH ]
@@ -2022,6 +2018,10 @@ mnemonics:
     opcode: rlwinm
     args: [ rA, rS, MB ]
     condition: ME == 31 && 32 - MB == SH
+  - name: clrlslwi
+    opcode: rlwinm
+    args: [ rA, rS, MB=MB+SH, SH ]
+    condition: SH < 32 && ME == 31 - SH
   - name: extlwi
     opcode: rlwinm
     args: [ rA, rS, ME=ME+1, SH ]