diff --git a/asm/src/generated.rs b/asm/src/generated.rs
index 9c737eb..d6a7eea 100644
--- a/asm/src/generated.rs
+++ b/asm/src/generated.rs
@@ -3610,6 +3610,26 @@ fn gen_lvewx128(args: &Arguments, modifiers: u32) -> Result<u32, ArgumentError>
     }
     Ok(code)
 }
+fn gen_lvlx(args: &Arguments, modifiers: u32) -> Result<u32, ArgumentError> {
+    check_arg_count(args, 3)?;
+    let mut code = 0x7c00040e | modifiers;
+    // vD
+    {
+        let arg = parse_unsigned(args, 0, 0x0, 0x1f)?;
+        code |= (arg & 0x1f) << 21;
+    }
+    // rA
+    {
+        let arg = parse_unsigned(args, 1, 0x0, 0x1f)?;
+        code |= (arg & 0x1f) << 16;
+    }
+    // rB
+    {
+        let arg = parse_unsigned(args, 2, 0x0, 0x1f)?;
+        code |= (arg & 0x1f) << 11;
+    }
+    Ok(code)
+}
 fn gen_lvlx128(args: &Arguments, modifiers: u32) -> Result<u32, ArgumentError> {
     check_arg_count(args, 3)?;
     let mut code = 0x10000403 | modifiers;
@@ -3631,6 +3651,26 @@ fn gen_lvlx128(args: &Arguments, modifiers: u32) -> Result<u32, ArgumentError> {
     }
     Ok(code)
 }
+fn gen_lvlxl(args: &Arguments, modifiers: u32) -> Result<u32, ArgumentError> {
+    check_arg_count(args, 3)?;
+    let mut code = 0x7c00060e | modifiers;
+    // vD
+    {
+        let arg = parse_unsigned(args, 0, 0x0, 0x1f)?;
+        code |= (arg & 0x1f) << 21;
+    }
+    // rA
+    {
+        let arg = parse_unsigned(args, 1, 0x0, 0x1f)?;
+        code |= (arg & 0x1f) << 16;
+    }
+    // rB
+    {
+        let arg = parse_unsigned(args, 2, 0x0, 0x1f)?;
+        code |= (arg & 0x1f) << 11;
+    }
+    Ok(code)
+}
 fn gen_lvlxl128(args: &Arguments, modifiers: u32) -> Result<u32, ArgumentError> {
     check_arg_count(args, 3)?;
     let mut code = 0x10000603 | modifiers;
@@ -3652,6 +3692,26 @@ fn gen_lvlxl128(args: &Arguments, modifiers: u32) -> Result<u32, ArgumentError>
     }
     Ok(code)
 }
+fn gen_lvrx(args: &Arguments, modifiers: u32) -> Result<u32, ArgumentError> {
+    check_arg_count(args, 3)?;
+    let mut code = 0x7c00044e | modifiers;
+    // vD
+    {
+        let arg = parse_unsigned(args, 0, 0x0, 0x1f)?;
+        code |= (arg & 0x1f) << 21;
+    }
+    // rA
+    {
+        let arg = parse_unsigned(args, 1, 0x0, 0x1f)?;
+        code |= (arg & 0x1f) << 16;
+    }
+    // rB
+    {
+        let arg = parse_unsigned(args, 2, 0x0, 0x1f)?;
+        code |= (arg & 0x1f) << 11;
+    }
+    Ok(code)
+}
 fn gen_lvrx128(args: &Arguments, modifiers: u32) -> Result<u32, ArgumentError> {
     check_arg_count(args, 3)?;
     let mut code = 0x10000443 | modifiers;
@@ -3673,6 +3733,26 @@ fn gen_lvrx128(args: &Arguments, modifiers: u32) -> Result<u32, ArgumentError> {
     }
     Ok(code)
 }
+fn gen_lvrxl(args: &Arguments, modifiers: u32) -> Result<u32, ArgumentError> {
+    check_arg_count(args, 3)?;
+    let mut code = 0x7c00064e | modifiers;
+    // vD
+    {
+        let arg = parse_unsigned(args, 0, 0x0, 0x1f)?;
+        code |= (arg & 0x1f) << 21;
+    }
+    // rA
+    {
+        let arg = parse_unsigned(args, 1, 0x0, 0x1f)?;
+        code |= (arg & 0x1f) << 16;
+    }
+    // rB
+    {
+        let arg = parse_unsigned(args, 2, 0x0, 0x1f)?;
+        code |= (arg & 0x1f) << 11;
+    }
+    Ok(code)
+}
 fn gen_lvrxl128(args: &Arguments, modifiers: u32) -> Result<u32, ArgumentError> {
     check_arg_count(args, 3)?;
     let mut code = 0x10000643 | modifiers;
@@ -6189,7 +6269,7 @@ fn gen_stvewx(args: &Arguments, modifiers: u32) -> Result<u32, ArgumentError> {
 }
 fn gen_stvewx128(args: &Arguments, modifiers: u32) -> Result<u32, ArgumentError> {
     check_arg_count(args, 3)?;
-    let mut code = 0x10000303 | modifiers;
+    let mut code = 0x10000183 | modifiers;
     // VDS128
     {
         let arg = parse_unsigned(args, 0, 0x0, 0x7f)?;
@@ -6208,6 +6288,26 @@ fn gen_stvewx128(args: &Arguments, modifiers: u32) -> Result<u32, ArgumentError>
     }
     Ok(code)
 }
+fn gen_stvlx(args: &Arguments, modifiers: u32) -> Result<u32, ArgumentError> {
+    check_arg_count(args, 3)?;
+    let mut code = 0x7c00050e | modifiers;
+    // vS
+    {
+        let arg = parse_unsigned(args, 0, 0x0, 0x1f)?;
+        code |= (arg & 0x1f) << 21;
+    }
+    // rA
+    {
+        let arg = parse_unsigned(args, 1, 0x0, 0x1f)?;
+        code |= (arg & 0x1f) << 16;
+    }
+    // rB
+    {
+        let arg = parse_unsigned(args, 2, 0x0, 0x1f)?;
+        code |= (arg & 0x1f) << 11;
+    }
+    Ok(code)
+}
 fn gen_stvlx128(args: &Arguments, modifiers: u32) -> Result<u32, ArgumentError> {
     check_arg_count(args, 3)?;
     let mut code = 0x10000503 | modifiers;
@@ -6229,6 +6329,26 @@ fn gen_stvlx128(args: &Arguments, modifiers: u32) -> Result<u32, ArgumentError>
     }
     Ok(code)
 }
+fn gen_stvlxl(args: &Arguments, modifiers: u32) -> Result<u32, ArgumentError> {
+    check_arg_count(args, 3)?;
+    let mut code = 0x7c00070e | modifiers;
+    // vS
+    {
+        let arg = parse_unsigned(args, 0, 0x0, 0x1f)?;
+        code |= (arg & 0x1f) << 21;
+    }
+    // rA
+    {
+        let arg = parse_unsigned(args, 1, 0x0, 0x1f)?;
+        code |= (arg & 0x1f) << 16;
+    }
+    // rB
+    {
+        let arg = parse_unsigned(args, 2, 0x0, 0x1f)?;
+        code |= (arg & 0x1f) << 11;
+    }
+    Ok(code)
+}
 fn gen_stvlxl128(args: &Arguments, modifiers: u32) -> Result<u32, ArgumentError> {
     check_arg_count(args, 3)?;
     let mut code = 0x10000703 | modifiers;
@@ -6250,6 +6370,26 @@ fn gen_stvlxl128(args: &Arguments, modifiers: u32) -> Result<u32, ArgumentError>
     }
     Ok(code)
 }
+fn gen_stvrx(args: &Arguments, modifiers: u32) -> Result<u32, ArgumentError> {
+    check_arg_count(args, 3)?;
+    let mut code = 0x7c00054e | modifiers;
+    // vS
+    {
+        let arg = parse_unsigned(args, 0, 0x0, 0x1f)?;
+        code |= (arg & 0x1f) << 21;
+    }
+    // rA
+    {
+        let arg = parse_unsigned(args, 1, 0x0, 0x1f)?;
+        code |= (arg & 0x1f) << 16;
+    }
+    // rB
+    {
+        let arg = parse_unsigned(args, 2, 0x0, 0x1f)?;
+        code |= (arg & 0x1f) << 11;
+    }
+    Ok(code)
+}
 fn gen_stvrx128(args: &Arguments, modifiers: u32) -> Result<u32, ArgumentError> {
     check_arg_count(args, 3)?;
     let mut code = 0x10000543 | modifiers;
@@ -6271,6 +6411,26 @@ fn gen_stvrx128(args: &Arguments, modifiers: u32) -> Result<u32, ArgumentError>
     }
     Ok(code)
 }
+fn gen_stvrxl(args: &Arguments, modifiers: u32) -> Result<u32, ArgumentError> {
+    check_arg_count(args, 3)?;
+    let mut code = 0x7c00074e | modifiers;
+    // vS
+    {
+        let arg = parse_unsigned(args, 0, 0x0, 0x1f)?;
+        code |= (arg & 0x1f) << 21;
+    }
+    // rA
+    {
+        let arg = parse_unsigned(args, 1, 0x0, 0x1f)?;
+        code |= (arg & 0x1f) << 16;
+    }
+    // rB
+    {
+        let arg = parse_unsigned(args, 2, 0x0, 0x1f)?;
+        code |= (arg & 0x1f) << 11;
+    }
+    Ok(code)
+}
 fn gen_stvrxl128(args: &Arguments, modifiers: u32) -> Result<u32, ArgumentError> {
     check_arg_count(args, 3)?;
     let mut code = 0x10000743 | modifiers;
@@ -7252,7 +7412,7 @@ fn gen_vandc(args: &Arguments, modifiers: u32) -> Result<u32, ArgumentError> {
 }
 fn gen_vandc128(args: &Arguments, modifiers: u32) -> Result<u32, ArgumentError> {
     check_arg_count(args, 3)?;
-    let mut code = 0x14000290 | modifiers;
+    let mut code = 0x14000250 | modifiers;
     // VDS128
     {
         let arg = parse_unsigned(args, 0, 0x0, 0x7f)?;
@@ -9301,12 +9461,12 @@ fn gen_vpkd3d128(args: &Arguments, modifiers: u32) -> Result<u32, ArgumentError>
         code |= (arg & 0x1f) << 11;
         code |= (arg >> 5) & 0x3;
     }
-    // Ximm
+    // D3DType
     {
         let arg = parse_unsigned(args, 2, 0x0, 0x7)?;
         code |= (arg & 0x7) << 18;
     }
-    // Yimm
+    // VMASK
     {
         let arg = parse_unsigned(args, 3, 0x0, 0x3)?;
         code |= (arg & 0x3) << 16;
@@ -9939,7 +10099,7 @@ fn gen_vrlw(args: &Arguments, modifiers: u32) -> Result<u32, ArgumentError> {
 }
 fn gen_vrlw128(args: &Arguments, modifiers: u32) -> Result<u32, ArgumentError> {
     check_arg_count(args, 3)?;
-    let mut code = 0x14000050 | modifiers;
+    let mut code = 0x18000050 | modifiers;
     // VDS128
     {
         let arg = parse_unsigned(args, 0, 0x0, 0x7f)?;
@@ -10559,7 +10719,7 @@ fn gen_vsro(args: &Arguments, modifiers: u32) -> Result<u32, ArgumentError> {
 }
 fn gen_vsro128(args: &Arguments, modifiers: u32) -> Result<u32, ArgumentError> {
     check_arg_count(args, 3)?;
-    let mut code = 0x180003d0 | modifiers;
+    let mut code = 0x140003d0 | modifiers;
     // VDS128
     {
         let arg = parse_unsigned(args, 0, 0x0, 0x7f)?;
@@ -10978,17 +11138,17 @@ fn gen_vupkd3d128(args: &Arguments, modifiers: u32) -> Result<u32, ArgumentError
         code |= (arg & 0x1f) << 21;
         code |= (arg >> 3) & 0xc;
     }
-    // vuimm
-    {
-        let arg = parse_unsigned(args, 1, 0x0, 0x1f)?;
-        code |= (arg & 0x1f) << 16;
-    }
     // VB128
     {
-        let arg = parse_unsigned(args, 2, 0x0, 0x7f)?;
+        let arg = parse_unsigned(args, 1, 0x0, 0x7f)?;
         code |= (arg & 0x1f) << 11;
         code |= (arg >> 5) & 0x3;
     }
+    // vuimm
+    {
+        let arg = parse_unsigned(args, 2, 0x0, 0x1f)?;
+        code |= (arg & 0x1f) << 16;
+    }
     Ok(code)
 }
 fn gen_vupkhpx(args: &Arguments, modifiers: u32) -> Result<u32, ArgumentError> {
@@ -11223,1172 +11383,1182 @@ type MnemonicFn = fn(&Arguments, u32) -> Result<u32, ArgumentError>;
 static MNEMONIC_MAP: phf::Map<&'static str, (MnemonicFn, u32)> = ::phf::Map {
     key: 12913932095322966823,
     disps: &[
+        (0, 392),
         (0, 1),
-        (0, 61),
-        (0, 37),
-        (0, 950),
-        (0, 0),
-        (0, 130),
-        (0, 184),
-        (4, 0),
-        (0, 7),
-        (0, 25),
-        (0, 4),
-        (0, 306),
-        (0, 175),
-        (0, 1),
-        (0, 25),
-        (0, 200),
-        (0, 218),
-        (0, 339),
-        (0, 112),
-        (0, 1),
-        (0, 0),
-        (0, 185),
-        (0, 2),
-        (0, 226),
-        (0, 200),
-        (0, 50),
-        (0, 0),
-        (0, 77),
         (0, 5),
+        (0, 19),
         (0, 1),
-        (0, 111),
-        (0, 700),
-        (0, 12),
-        (0, 12),
-        (0, 296),
-        (0, 1),
-        (0, 32),
-        (0, 105),
-        (0, 174),
         (0, 14),
-        (0, 0),
-        (0, 4),
-        (0, 8),
-        (0, 324),
-        (0, 11),
-        (0, 11),
-        (0, 0),
-        (0, 0),
-        (0, 936),
-        (0, 37),
-        (0, 64),
-        (0, 6),
-        (0, 549),
-        (0, 7),
-        (0, 7),
-        (0, 712),
-        (1, 4),
-        (0, 319),
-        (0, 88),
-        (0, 5),
-        (0, 214),
+        (0, 26),
+        (0, 528),
         (0, 2),
-        (0, 834),
-        (1, 665),
-        (0, 7),
-        (0, 667),
-        (0, 36),
-        (0, 153),
-        (0, 4),
-        (0, 93),
-        (0, 954),
-        (0, 305),
-        (0, 8),
-        (0, 2),
-        (0, 14),
-        (0, 85),
         (0, 0),
-        (0, 213),
-        (0, 196),
-        (0, 10),
-        (0, 573),
-        (0, 596),
+        (0, 73),
+        (0, 12),
+        (0, 71),
         (0, 20),
-        (1, 350),
-        (0, 10),
-        (0, 303),
-        (0, 12),
-        (1, 818),
-        (0, 76),
-        (0, 1),
-        (2, 241),
-        (0, 189),
-        (0, 49),
+        (0, 535),
         (0, 0),
-        (0, 363),
-        (0, 3),
-        (2, 35),
-        (1, 24),
-        (1, 146),
-        (0, 170),
-        (0, 521),
-        (0, 214),
-        (0, 168),
+        (0, 42),
+        (0, 28),
+        (0, 2),
+        (0, 1),
+        (0, 493),
+        (0, 292),
+        (0, 2),
+        (0, 343),
+        (0, 11),
+        (0, 30),
+        (0, 1),
+        (0, 198),
+        (0, 831),
+        (0, 5),
+        (0, 697),
         (0, 24),
-        (0, 13),
-        (0, 20),
         (0, 0),
-        (0, 815),
+        (0, 214),
         (0, 10),
-        (0, 909),
-        (0, 2),
-        (0, 0),
-        (0, 873),
+        (0, 939),
         (0, 4),
-        (0, 508),
-        (0, 923),
-        (0, 4),
-        (0, 253),
-        (0, 74),
-        (0, 168),
-        (0, 13),
-        (0, 35),
-        (0, 571),
-        (0, 629),
-        (1, 201),
-        (1, 28),
+        (0, 14),
+        (0, 117),
+        (1, 299),
         (0, 1),
-        (0, 68),
-        (0, 215),
-        (0, 952),
-        (2, 527),
-        (0, 362),
-        (0, 244),
-        (2, 98),
-        (0, 107),
-        (0, 482),
-        (0, 47),
-        (4, 877),
-        (0, 149),
-        (0, 0),
-        (0, 43),
-        (2, 604),
-        (2, 644),
-        (5, 668),
-        (0, 276),
+        (0, 174),
         (0, 8),
-        (1, 225),
         (0, 1),
-        (0, 7),
-        (1, 826),
-        (6, 156),
-        (0, 55),
-        (0, 251),
-        (0, 321),
+        (0, 320),
         (0, 0),
-        (1, 211),
-        (0, 223),
-        (2, 486),
-        (23, 334),
-        (0, 929),
-        (3, 632),
-        (1, 926),
+        (0, 22),
         (0, 18),
-        (9, 965),
-        (0, 732),
-        (16, 209),
-        (0, 8),
-        (2, 681),
-        (0, 737),
-        (0, 455),
-        (0, 33),
-        (0, 33),
-        (0, 413),
-        (0, 389),
-        (0, 134),
+        (0, 45),
+        (0, 116),
+        (0, 84),
+        (0, 70),
         (0, 6),
-        (4, 24),
-        (0, 743),
-        (0, 344),
-        (0, 14),
-        (0, 140),
-        (4, 895),
-        (0, 31),
-        (0, 14),
-        (2, 36),
-        (0, 151),
-        (0, 710),
-        (1, 179),
-        (2, 321),
+        (0, 11),
+        (0, 45),
+        (0, 3),
+        (0, 10),
+        (0, 40),
         (0, 0),
-        (1, 440),
-        (0, 338),
-        (1, 489),
+        (0, 0),
+        (0, 10),
+        (0, 534),
+        (0, 616),
+        (0, 0),
+        (0, 44),
+        (0, 79),
+        (0, 1),
+        (0, 204),
+        (0, 14),
+        (0, 1),
+        (0, 33),
+        (0, 751),
+        (0, 70),
+        (0, 609),
+        (1, 433),
+        (0, 108),
+        (1, 189),
+        (0, 142),
+        (0, 359),
+        (0, 78),
+        (0, 171),
+        (0, 0),
+        (0, 9),
+        (1, 54),
+        (1, 27),
+        (0, 1),
+        (0, 99),
+        (0, 875),
+        (0, 201),
+        (0, 472),
         (0, 2),
+        (0, 0),
+        (0, 16),
+        (0, 10),
+        (0, 34),
+        (0, 265),
+        (0, 337),
+        (2, 477),
+        (0, 0),
+        (0, 179),
+        (0, 6),
+        (0, 230),
+        (0, 39),
+        (0, 86),
+        (0, 813),
+        (0, 92),
+        (0, 13),
+        (0, 506),
+        (0, 67),
+        (0, 4),
+        (13, 905),
+        (0, 2),
+        (0, 1),
+        (1, 48),
+        (0, 194),
+        (0, 309),
+        (4, 600),
+        (0, 119),
+        (0, 4),
+        (0, 610),
+        (0, 239),
+        (0, 18),
+        (0, 152),
+        (2, 603),
+        (0, 257),
+        (0, 223),
+        (0, 39),
+        (0, 97),
+        (0, 519),
+        (2, 953),
+        (0, 326),
+        (1, 646),
+        (0, 97),
+        (0, 12),
+        (0, 1),
+        (0, 60),
+        (0, 10),
+        (0, 29),
+        (1, 578),
+        (0, 735),
+        (1, 259),
+        (0, 347),
+        (4, 488),
+        (0, 3),
+        (0, 158),
+        (0, 76),
+        (0, 434),
+        (0, 90),
+        (0, 13),
+        (0, 69),
+        (0, 2),
+        (0, 7),
+        (0, 89),
+        (1, 643),
+        (0, 406),
+        (5, 454),
+        (3, 138),
+        (0, 209),
+        (5, 135),
+        (0, 3),
+        (3, 266),
+        (0, 65),
+        (1, 365),
+        (0, 384),
+        (0, 113),
+        (1, 47),
+        (0, 4),
+        (0, 475),
+        (0, 8),
+        (0, 839),
+        (0, 6),
+        (0, 117),
+        (2, 665),
+        (3, 398),
+        (1, 868),
+        (0, 83),
+        (0, 7),
+        (0, 0),
+        (0, 774),
+        (0, 754),
+        (10, 778),
+        (2, 272),
+        (1, 456),
+        (0, 140),
+        (0, 32),
+        (5, 299),
+        (7, 133),
+        (0, 392),
+        (9, 727),
+        (21, 79),
+        (1, 394),
+        (1, 333),
+        (0, 142),
+        (8, 823),
+        (0, 0),
+        (0, 677),
     ],
     entries: &[
-        ("vsubuws", (gen_vsubuws, 0x0)),
-        ("bgtl-", (gen_bgt, 0x200001)),
-        ("bdzl+", (gen_bdz, 0x200001)),
-        ("vcmpgtfp128", (gen_vcmpgtfp128, 0x0)),
-        ("frsp", (gen_frsp, 0x0)),
-        ("bdnzfa+", (gen_bdnzf, 0x200002)),
-        ("mullw.", (gen_mullw, 0x1)),
-        ("lbzux", (gen_lbzux, 0x0)),
-        ("mr.", (gen_mr, 0x1)),
-        ("lvsl128", (gen_lvsl128, 0x0)),
-        ("lvsl", (gen_lvsl, 0x0)),
-        ("subfco.", (gen_subfc, 0x401)),
-        ("stdux", (gen_stdux, 0x0)),
-        ("mtxer", (gen_mtxer, 0x0)),
-        ("twi", (gen_twi, 0x0)),
-        ("mtmsrd", (gen_mtmsrd, 0x0)),
-        ("bsoctr", (gen_bsoctr, 0x0)),
-        ("fabs.", (gen_fabs, 0x1)),
-        ("blelr+", (gen_blelr, 0x200000)),
-        ("stfdu", (gen_stfdu, 0x0)),
-        ("fsel.", (gen_fsel, 0x1)),
-        ("fnmadd", (gen_fnmadd, 0x0)),
-        ("vspltisw128", (gen_vspltisw128, 0x0)),
-        ("lswi", (gen_lswi, 0x0)),
-        ("bgela", (gen_bge, 0x3)),
-        ("subf", (gen_subf, 0x0)),
-        ("mfdec", (gen_mfdec, 0x0)),
-        ("bgela+", (gen_bge, 0x200003)),
-        ("vsumsws", (gen_vsumsws, 0x0)),
-        ("li", (gen_li, 0x0)),
-        ("dcbf", (gen_dcbf, 0x0)),
-        ("lhzu", (gen_lhzu, 0x0)),
-        ("rotrwi.", (gen_rotrwi, 0x1)),
-        ("vcmpgtsb", (gen_vcmpgtsb, 0x0)),
-        ("twlge", (gen_twlge, 0x0)),
-        ("crandc", (gen_crandc, 0x0)),
-        ("bcctrl", (gen_bcctr, 0x1)),
-        ("bdzflr", (gen_bdzflr, 0x0)),
-        ("bdztlr+", (gen_bdztlr, 0x200000)),
-        ("dss", (gen_dss, 0x0)),
-        ("bnslrl", (gen_bnslr, 0x1)),
-        ("bgt", (gen_bgt, 0x0)),
-        ("vexptefp", (gen_vexptefp, 0x0)),
-        ("rldic", (gen_rldic, 0x0)),
-        ("vsum4ubs", (gen_vsum4ubs, 0x0)),
-        ("bdzla+", (gen_bdz, 0x200003)),
-        ("mtsprg", (gen_mtsprg, 0x0)),
-        ("bdnztla+", (gen_bdnzt, 0x200003)),
-        ("extlwi", (gen_extlwi, 0x0)),
-        ("mfsr", (gen_mfsr, 0x0)),
-        ("rldicl.", (gen_rldicl, 0x1)),
-        ("lvlx128", (gen_lvlx128, 0x0)),
-        ("vrfiz128", (gen_vrfiz128, 0x0)),
-        ("bcl", (gen_bc, 0x1)),
-        ("vmulesh", (gen_vmulesh, 0x0)),
-        ("bltlrl+", (gen_bltlr, 0x200001)),
-        ("bdzfla+", (gen_bdzf, 0x200003)),
-        ("fmsubs.", (gen_fmsubs, 0x1)),
-        ("fctiwz.", (gen_fctiwz, 0x1)),
-        ("divwuo.", (gen_divwu, 0x401)),
-        ("vrlw128", (gen_vrlw128, 0x0)),
-        ("cmpdi", (gen_cmpdi, 0x0)),
-        ("lwzu", (gen_lwzu, 0x0)),
-        ("vnor128", (gen_vnor128, 0x0)),
-        ("bdnzflr", (gen_bdnzflr, 0x0)),
-        ("ldux", (gen_ldux, 0x0)),
-        ("bclr", (gen_bclr, 0x0)),
-        ("extlwi.", (gen_extlwi, 0x1)),
-        ("subfc.", (gen_subfc, 0x1)),
-        ("fmsub.", (gen_fmsub, 0x1)),
-        ("add", (gen_add, 0x0)),
-        ("stwux", (gen_stwux, 0x0)),
-        ("sthx", (gen_sthx, 0x0)),
-        ("bdnzl", (gen_bdnz, 0x1)),
-        ("mfsdr1", (gen_mfsdr1, 0x0)),
-        ("vaddsbs", (gen_vaddsbs, 0x0)),
-        ("subfe", (gen_subfe, 0x0)),
-        ("andc", (gen_andc, 0x0)),
-        ("bsoctr+", (gen_bsoctr, 0x200000)),
-        ("vrsqrtefp128", (gen_vrsqrtefp128, 0x0)),
-        ("bltla-", (gen_blt, 0x200003)),
-        ("vmaxub", (gen_vmaxub, 0x0)),
-        ("fctid", (gen_fctid, 0x0)),
-        ("rotrwi", (gen_rotrwi, 0x0)),
-        ("subfme.", (gen_subfme, 0x1)),
-        ("sraw.", (gen_sraw, 0x1)),
-        ("blel", (gen_ble, 0x1)),
-        ("vsubsbs", (gen_vsubsbs, 0x0)),
-        ("addis", (gen_addis, 0x0)),
-        ("beql-", (gen_beq, 0x200001)),
-        ("lwa", (gen_lwa, 0x0)),
-        ("bdnztl-", (gen_bdnzt, 0x200001)),
-        ("vlogefp", (gen_vlogefp, 0x0)),
-        ("bdnzl+", (gen_bdnz, 0x200001)),
-        ("cmpd", (gen_cmpd, 0x0)),
-        ("divwu.", (gen_divwu, 0x1)),
-        ("vrfiz", (gen_vrfiz, 0x0)),
-        ("bdzfla-", (gen_bdzf, 0x200003)),
-        ("xor", (gen_xor, 0x0)),
-        ("subic.", (gen_subic_, 0x0)),
-        ("bdztl+", (gen_bdzt, 0x200001)),
-        ("fabs", (gen_fabs, 0x0)),
-        ("fctid.", (gen_fctid, 0x1)),
-        ("nand.", (gen_nand, 0x1)),
-        ("twgti", (gen_twgti, 0x0)),
-        ("vcmpgtuh", (gen_vcmpgtuh, 0x0)),
-        ("bdzfl-", (gen_bdzf, 0x200001)),
-        ("rldimi", (gen_rldimi, 0x0)),
-        ("blta+", (gen_blt, 0x200002)),
-        ("adde", (gen_adde, 0x0)),
-        ("mfsprg", (gen_mfsprg, 0x0)),
-        ("bdnzt", (gen_bdnzt, 0x0)),
-        ("vslh", (gen_vslh, 0x0)),
-        ("frsqrte.", (gen_frsqrte, 0x1)),
-        ("bdnzl-", (gen_bdnz, 0x200001)),
-        ("bdnztlrl+", (gen_bdnztlr, 0x200001)),
-        ("vsraw128", (gen_vsraw128, 0x0)),
-        ("bnsl", (gen_bns, 0x1)),
-        ("blela+", (gen_ble, 0x200003)),
-        ("divw.", (gen_divw, 0x1)),
-        ("mtfsb0.", (gen_mtfsb0, 0x1)),
-        ("bgel+", (gen_bge, 0x200001)),
-        ("ble-", (gen_ble, 0x200000)),
-        ("addmeo", (gen_addme, 0x400)),
-        ("extsh", (gen_extsh, 0x0)),
-        ("dcbz", (gen_dcbz, 0x0)),
-        ("bltla", (gen_blt, 0x3)),
-        ("bgectrl", (gen_bgectr, 0x1)),
-        ("mtfsfi", (gen_mtfsfi, 0x0)),
-        ("clrlwi.", (gen_clrlwi, 0x1)),
-        ("bdnztl+", (gen_bdnzt, 0x200001)),
-        ("bsolrl", (gen_bsolr, 0x1)),
-        ("mtfsb1", (gen_mtfsb1, 0x0)),
-        ("vcsxwfp128", (gen_vcsxwfp128, 0x0)),
-        ("fsubs.", (gen_fsubs, 0x1)),
-        ("bdzfa", (gen_bdzf, 0x2)),
-        ("tlbie", (gen_tlbie, 0x0)),
-        ("ptesync", (gen_ptesync, 0x0)),
-        ("vmaxuh", (gen_vmaxuh, 0x0)),
-        ("vadduhs", (gen_vadduhs, 0x0)),
-        ("tdlnl", (gen_tdlnl, 0x0)),
-        ("bdza", (gen_bdz, 0x2)),
-        ("beqctrl", (gen_beqctr, 0x1)),
-        ("vcmpequw", (gen_vcmpequw, 0x0)),
-        ("lvx128", (gen_lvx128, 0x0)),
-        ("bcctr+", (gen_bcctr, 0x200000)),
-        ("vsum2sws", (gen_vsum2sws, 0x0)),
-        ("mfxer", (gen_mfxer, 0x0)),
-        ("vmaxuw", (gen_vmaxuw, 0x0)),
-        ("bca-", (gen_bc, 0x200002)),
-        ("fcmpo", (gen_fcmpo, 0x0)),
-        ("bdnzf+", (gen_bdnzf, 0x200000)),
-        ("vcmpbfp.", (gen_vcmpbfp, 0x400)),
-        ("sync", (gen_sync, 0x0)),
-        ("vmhaddshs", (gen_vmhaddshs, 0x0)),
-        ("mtmsr", (gen_mtmsr, 0x0)),
-        ("stbu", (gen_stbu, 0x0)),
-        ("blectr", (gen_blectr, 0x0)),
-        ("vminsh", (gen_vminsh, 0x0)),
-        ("beqctrl+", (gen_beqctr, 0x200001)),
-        ("bgtlr+", (gen_bgtlr, 0x200000)),
-        ("fmadds", (gen_fmadds, 0x0)),
-        ("mtsrin", (gen_mtsrin, 0x0)),
-        ("addco.", (gen_addc, 0x401)),
-        ("divwuo", (gen_divwu, 0x400)),
-        ("crmove", (gen_crmove, 0x0)),
-        ("twllei", (gen_twllei, 0x0)),
-        ("rldcr.", (gen_rldcr, 0x1)),
-        ("bnel+", (gen_bne, 0x200001)),
-        ("bnea+", (gen_bne, 0x200002)),
-        ("vsubfp", (gen_vsubfp, 0x0)),
-        ("bnectrl+", (gen_bnectr, 0x200001)),
-        ("mfdbatu", (gen_mfdbatu, 0x0)),
-        ("bdzt-", (gen_bdzt, 0x200000)),
-        ("vupklsh", (gen_vupklsh, 0x0)),
-        ("stbux", (gen_stbux, 0x0)),
-        ("vpkuhus128", (gen_vpkuhus128, 0x0)),
-        ("subfic", (gen_subfic, 0x0)),
-        ("subfeo", (gen_subfe, 0x400)),
-        ("bdnzfla+", (gen_bdnzf, 0x200003)),
-        ("bgtlr", (gen_bgtlr, 0x0)),
-        ("bdnztla", (gen_bdnzt, 0x3)),
-        ("beql+", (gen_beq, 0x200001)),
-        ("addzeo", (gen_addze, 0x400)),
-        ("bnelrl+", (gen_bnelr, 0x200001)),
-        ("clrlslwi.", (gen_clrlslwi, 0x1)),
-        ("mulhdu", (gen_mulhdu, 0x0)),
-        ("vspltw", (gen_vspltw, 0x0)),
-        ("bdnzla+", (gen_bdnz, 0x200003)),
-        ("vrfim128", (gen_vrfim128, 0x0)),
-        ("crorc", (gen_crorc, 0x0)),
-        ("subi", (gen_subi, 0x0)),
-        ("fnmsubs.", (gen_fnmsubs, 0x1)),
-        ("mttbl", (gen_mttbl, 0x0)),
-        ("vmrglh", (gen_vmrglh, 0x0)),
-        ("stbx", (gen_stbx, 0x0)),
-        ("rldicr.", (gen_rldicr, 0x1)),
-        ("vmrglw128", (gen_vmrglw128, 0x0)),
-        ("bgelrl", (gen_bgelr, 0x1)),
-        ("mfibatl", (gen_mfibatl, 0x0)),
-        ("trap", (gen_trap, 0x0)),
-        ("vminuh", (gen_vminuh, 0x0)),
-        ("vavguw", (gen_vavguw, 0x0)),
-        ("stwx", (gen_stwx, 0x0)),
-        ("mulhwu.", (gen_mulhwu, 0x1)),
-        ("extsb", (gen_extsb, 0x0)),
-        ("bsoa", (gen_bso, 0x2)),
-        ("subis", (gen_subis, 0x0)),
-        ("extsw.", (gen_extsw, 0x1)),
-        ("vpkuwus", (gen_vpkuwus, 0x0)),
-        ("vexptefp128", (gen_vexptefp128, 0x0)),
-        ("cmp", (gen_cmp, 0x0)),
-        ("srad.", (gen_srad, 0x1)),
-        ("divw", (gen_divw, 0x0)),
-        ("vmuleuh", (gen_vmuleuh, 0x0)),
-        ("vsel128", (gen_vsel128, 0x0)),
-        ("vcmpgtsh.", (gen_vcmpgtsh, 0x400)),
-        ("vslw", (gen_vslw, 0x0)),
-        ("ba", (gen_b, 0x2)),
-        ("rlwinm", (gen_rlwinm, 0x0)),
-        ("bgtctrl+", (gen_bgtctr, 0x200001)),
-        ("vcmpgefp128.", (gen_vcmpgefp128, 0x40)),
-        ("bgtl", (gen_bgt, 0x1)),
-        ("vmr", (gen_vmr, 0x0)),
-        ("vminsb", (gen_vminsb, 0x0)),
-        ("bgectr", (gen_bgectr, 0x0)),
-        ("bnsa-", (gen_bns, 0x200002)),
-        ("mtsr", (gen_mtsr, 0x0)),
         ("subfe.", (gen_subfe, 0x1)),
-        ("mtdar", (gen_mtdar, 0x0)),
-        ("bltlr+", (gen_bltlr, 0x200000)),
-        ("fmuls", (gen_fmuls, 0x0)),
-        ("stfs", (gen_stfs, 0x0)),
-        ("mffs", (gen_mffs, 0x0)),
-        ("vmladduhm", (gen_vmladduhm, 0x0)),
-        ("vminfp", (gen_vminfp, 0x0)),
-        ("vmsumuhs", (gen_vmsumuhs, 0x0)),
-        ("divd", (gen_divd, 0x0)),
-        ("blt+", (gen_blt, 0x200000)),
-        ("fnmadds.", (gen_fnmadds, 0x1)),
-        ("bnelrl", (gen_bnelr, 0x1)),
-        ("addi", (gen_addi, 0x0)),
-        ("vspltisb", (gen_vspltisb, 0x0)),
-        ("mtfsb0", (gen_mtfsb0, 0x0)),
-        ("bge", (gen_bge, 0x0)),
-        ("addic.", (gen_addic_, 0x0)),
-        ("isync", (gen_isync, 0x0)),
-        ("lwbrx", (gen_lwbrx, 0x0)),
-        ("stwbrx", (gen_stwbrx, 0x0)),
-        ("mr", (gen_mr, 0x0)),
-        ("bdnza+", (gen_bdnz, 0x200002)),
-        ("vmsumshm", (gen_vmsumshm, 0x0)),
-        ("mulhd.", (gen_mulhd, 0x1)),
-        ("bdzlr+", (gen_bdzlr, 0x200000)),
-        ("cntlzd", (gen_cntlzd, 0x0)),
-        ("blrl", (gen_blr, 0x1)),
-        ("vcmpgefp.", (gen_vcmpgefp, 0x400)),
-        ("subfco", (gen_subfc, 0x400)),
-        ("vsro128", (gen_vsro128, 0x0)),
-        ("bdnzla-", (gen_bdnz, 0x200003)),
-        ("vsubcuw", (gen_vsubcuw, 0x0)),
-        ("mtsrr0", (gen_mtsrr0, 0x0)),
-        ("vsrah", (gen_vsrah, 0x0)),
-        ("lfs", (gen_lfs, 0x0)),
-        ("bsola+", (gen_bso, 0x200003)),
-        ("vspltisw", (gen_vspltisw, 0x0)),
-        ("bdzfa-", (gen_bdzf, 0x200002)),
-        ("lvehx", (gen_lvehx, 0x0)),
-        ("bltlrl", (gen_bltlr, 0x1)),
-        ("bnsa+", (gen_bns, 0x200002)),
-        ("bdzl-", (gen_bdz, 0x200001)),
-        ("mcrfs", (gen_mcrfs, 0x0)),
-        ("mulhw.", (gen_mulhw, 0x1)),
-        ("clrrwi.", (gen_clrrwi, 0x1)),
-        ("nego", (gen_neg, 0x400)),
-        ("vctuxs", (gen_vctuxs, 0x0)),
-        ("addze", (gen_addze, 0x0)),
-        ("lfsux", (gen_lfsux, 0x0)),
-        ("bnslrl+", (gen_bnslr, 0x200001)),
-        ("vminuw", (gen_vminuw, 0x0)),
-        ("vsum4sbs", (gen_vsum4sbs, 0x0)),
-        ("extsw", (gen_extsw, 0x0)),
-        ("bso-", (gen_bso, 0x200000)),
-        ("dcbi", (gen_dcbi, 0x0)),
-        ("bltctr+", (gen_bltctr, 0x200000)),
-        ("vpkswss", (gen_vpkswss, 0x0)),
-        ("lfdu", (gen_lfdu, 0x0)),
-        ("stvewx128", (gen_stvewx128, 0x0)),
-        ("fnabs.", (gen_fnabs, 0x1)),
-        ("vpkswus128", (gen_vpkswus128, 0x0)),
-        ("nor.", (gen_nor, 0x1)),
-        ("vsububm", (gen_vsububm, 0x0)),
-        ("vnor", (gen_vnor, 0x0)),
-        ("srawi", (gen_srawi, 0x0)),
-        ("divduo", (gen_divdu, 0x400)),
-        ("bgea+", (gen_bge, 0x200002)),
-        ("bge+", (gen_bge, 0x200000)),
-        ("vadduws", (gen_vadduws, 0x0)),
-        ("vand128", (gen_vand128, 0x0)),
-        ("bne", (gen_bne, 0x0)),
-        ("stfsu", (gen_stfsu, 0x0)),
-        ("vcmpgtsw.", (gen_vcmpgtsw, 0x400)),
-        ("bdnztlrl", (gen_bdnztlr, 0x1)),
-        ("blelr", (gen_blelr, 0x0)),
-        ("mtdec", (gen_mtdec, 0x0)),
-        ("bltla+", (gen_blt, 0x200003)),
-        ("bgtctr+", (gen_bgtctr, 0x200000)),
-        ("vandc128", (gen_vandc128, 0x0)),
-        ("blea", (gen_ble, 0x2)),
-        ("subfmeo", (gen_subfme, 0x400)),
-        ("bdz-", (gen_bdz, 0x200000)),
-        ("bdnza", (gen_bdnz, 0x2)),
-        ("bgt+", (gen_bgt, 0x200000)),
-        ("vupkd3d128", (gen_vupkd3d128, 0x0)),
-        ("lbz", (gen_lbz, 0x0)),
-        ("fres.", (gen_fres, 0x1)),
-        ("vminub", (gen_vminub, 0x0)),
-        ("slwi.", (gen_slwi, 0x1)),
-        ("vnmsubfp", (gen_vnmsubfp, 0x0)),
-        ("adde.", (gen_adde, 0x1)),
-        ("bsola", (gen_bso, 0x3)),
-        ("vcmpequb.", (gen_vcmpequb, 0x400)),
-        ("icbi.", (gen_icbi, 0x1)),
-        ("dssall", (gen_dssall, 0x0)),
-        ("fdivs", (gen_fdivs, 0x0)),
-        ("lvrx128", (gen_lvrx128, 0x0)),
-        ("fnabs", (gen_fnabs, 0x0)),
-        ("vcmpequw128.", (gen_vcmpequw128, 0x40)),
-        ("stvlx128", (gen_stvlx128, 0x0)),
-        ("bdztlrl", (gen_bdztlr, 0x1)),
-        ("vcfpuxws128", (gen_vcfpuxws128, 0x0)),
-        ("beqla-", (gen_beq, 0x200003)),
-        ("slw.", (gen_slw, 0x1)),
-        ("cmpi", (gen_cmpi, 0x0)),
-        ("vsubuhs", (gen_vsubuhs, 0x0)),
-        ("addme.", (gen_addme, 0x1)),
-        ("bso", (gen_bso, 0x0)),
-        ("bdnzfl+", (gen_bdnzf, 0x200001)),
-        ("bclrl+", (gen_bclr, 0x200001)),
-        ("tdlti", (gen_tdlti, 0x0)),
-        ("mcrf", (gen_mcrf, 0x0)),
-        ("sc", (gen_sc, 0x0)),
-        ("bca+", (gen_bc, 0x200002)),
-        ("and.", (gen_and, 0x1)),
-        ("lhaux", (gen_lhaux, 0x0)),
-        ("fctidz.", (gen_fctidz, 0x1)),
-        ("lhau", (gen_lhau, 0x0)),
-        ("vmaxsw", (gen_vmaxsw, 0x0)),
-        ("vsraw", (gen_vsraw, 0x0)),
-        ("stswi", (gen_stswi, 0x0)),
-        ("mulld", (gen_mulld, 0x0)),
-        ("bdz+", (gen_bdz, 0x200000)),
-        ("bgtla", (gen_bgt, 0x3)),
-        ("fnmadds", (gen_fnmadds, 0x0)),
-        ("vpkd3d128", (gen_vpkd3d128, 0x0)),
-        ("bso+", (gen_bso, 0x200000)),
-        ("vcmpgtfp128.", (gen_vcmpgtfp128, 0x40)),
-        ("vmrghb", (gen_vmrghb, 0x0)),
-        ("vmuleub", (gen_vmuleub, 0x0)),
-        ("vcmpgtfp.", (gen_vcmpgtfp, 0x400)),
-        ("bgtctr", (gen_bgtctr, 0x0)),
-        ("vupklpx", (gen_vupklpx, 0x0)),
-        ("vmaxsb", (gen_vmaxsb, 0x0)),
-        ("mfsrr1", (gen_mfsrr1, 0x0)),
-        ("bnea", (gen_bne, 0x2)),
-        ("fnmsub.", (gen_fnmsub, 0x1)),
-        ("vmaddcfp128", (gen_vmaddcfp128, 0x0)),
-        ("vaddshs", (gen_vaddshs, 0x0)),
-        ("vslb", (gen_vslb, 0x0)),
-        ("blelrl+", (gen_blelr, 0x200001)),
-        ("xori", (gen_xori, 0x0)),
-        ("bsol+", (gen_bso, 0x200001)),
-        ("fdivs.", (gen_fdivs, 0x1)),
-        ("srd", (gen_srd, 0x0)),
-        ("vcmpgtfp", (gen_vcmpgtfp, 0x0)),
-        ("fsub", (gen_fsub, 0x0)),
-        ("bdnztlr", (gen_bdnztlr, 0x0)),
-        ("mtfsb1.", (gen_mtfsb1, 0x1)),
-        ("cmpldi", (gen_cmpldi, 0x0)),
-        ("bdnzf-", (gen_bdnzf, 0x200000)),
-        ("beqa+", (gen_beq, 0x200002)),
-        ("vcmpgtub", (gen_vcmpgtub, 0x0)),
-        ("mfsrin", (gen_mfsrin, 0x0)),
-        ("bdnzf", (gen_bdnzf, 0x0)),
-        ("fcmpu", (gen_fcmpu, 0x0)),
-        ("stvx", (gen_stvx, 0x0)),
-        ("xoris", (gen_xoris, 0x0)),
-        ("dcbt", (gen_dcbt, 0x0)),
-        ("td", (gen_td, 0x0)),
-        ("creqv", (gen_creqv, 0x0)),
-        ("fsub.", (gen_fsub, 0x1)),
-        ("ldarx", (gen_ldarx, 0x0)),
-        ("blectrl+", (gen_blectr, 0x200001)),
-        ("vsubuhm", (gen_vsubuhm, 0x0)),
-        ("fmadd", (gen_fmadd, 0x0)),
-        ("bgelrl+", (gen_bgelr, 0x200001)),
-        ("vpkpx", (gen_vpkpx, 0x0)),
-        ("subf.", (gen_subf, 0x1)),
-        ("add.", (gen_add, 0x1)),
-        ("bdnzta", (gen_bdnzt, 0x2)),
-        ("vavguh", (gen_vavguh, 0x0)),
-        ("mfibatu", (gen_mfibatu, 0x0)),
-        ("bnsla", (gen_bns, 0x3)),
-        ("bnea-", (gen_bne, 0x200002)),
-        ("lvsr", (gen_lvsr, 0x0)),
-        ("bdnzta-", (gen_bdnzt, 0x200002)),
-        ("stswx", (gen_stswx, 0x0)),
-        ("stvxl", (gen_stvxl, 0x0)),
-        ("dcbtst", (gen_dcbtst, 0x0)),
-        ("vand", (gen_vand, 0x0)),
-        ("vspltb", (gen_vspltb, 0x0)),
-        ("vperm128", (gen_vperm128, 0x0)),
-        ("stmw", (gen_stmw, 0x0)),
-        ("bdnztlr+", (gen_bdnztlr, 0x200000)),
-        ("bdztl-", (gen_bdzt, 0x200001)),
-        ("stvlxl128", (gen_stvlxl128, 0x0)),
-        ("cmpld", (gen_cmpld, 0x0)),
-        ("rldic.", (gen_rldic, 0x1)),
-        ("bdnzfla", (gen_bdnzf, 0x3)),
-        ("vavgsh", (gen_vavgsh, 0x0)),
-        ("vctsxs", (gen_vctsxs, 0x0)),
-        ("bgea", (gen_bge, 0x2)),
-        ("vupklsb128", (gen_vupklsb128, 0x0)),
-        ("vsubsws", (gen_vsubsws, 0x0)),
-        ("vrfip", (gen_vrfip, 0x0)),
-        ("divwu", (gen_divwu, 0x0)),
-        ("rldcr", (gen_rldcr, 0x0)),
-        ("fadd", (gen_fadd, 0x0)),
-        ("fadd.", (gen_fadd, 0x1)),
-        ("bgta", (gen_bgt, 0x2)),
-        ("vadduhm", (gen_vadduhm, 0x0)),
-        ("bdzfla", (gen_bdzf, 0x3)),
-        ("vpkuhum", (gen_vpkuhum, 0x0)),
-        ("addc.", (gen_addc, 0x1)),
-        ("fdiv", (gen_fdiv, 0x0)),
-        ("bdzf+", (gen_bdzf, 0x200000)),
-        ("mtfsf.", (gen_mtfsf, 0x1)),
-        ("bns", (gen_bns, 0x0)),
-        ("mulhw", (gen_mulhw, 0x0)),
-        ("sraw", (gen_sraw, 0x0)),
-        ("crand", (gen_crand, 0x0)),
-        ("vpkswss128", (gen_vpkswss128, 0x0)),
-        ("vrefp128", (gen_vrefp128, 0x0)),
-        ("bdzf", (gen_bdzf, 0x0)),
-        ("slw", (gen_slw, 0x0)),
-        ("neg.", (gen_neg, 0x1)),
-        ("vsel", (gen_vsel, 0x0)),
-        ("bsolrl+", (gen_bsolr, 0x200001)),
-        ("vslw128", (gen_vslw128, 0x0)),
-        ("vxor128", (gen_vxor128, 0x0)),
-        ("sld", (gen_sld, 0x0)),
-        ("crxor", (gen_crxor, 0x0)),
-        ("bdnzla", (gen_bdnz, 0x3)),
-        ("fctiw", (gen_fctiw, 0x0)),
-        ("vmaxsh", (gen_vmaxsh, 0x0)),
-        ("vsrab", (gen_vsrab, 0x0)),
-        ("bsoctrl", (gen_bsoctr, 0x1)),
-        ("srw", (gen_srw, 0x0)),
-        ("dststt", (gen_dstst, 0x2000000)),
-        ("rfid", (gen_rfid, 0x0)),
-        ("bcla-", (gen_bc, 0x200003)),
-        ("lmw", (gen_lmw, 0x0)),
-        ("tlbsync", (gen_tlbsync, 0x0)),
-        ("mfcr", (gen_mfcr, 0x0)),
-        ("bdnzfa-", (gen_bdnzf, 0x200002)),
-        ("fcfid.", (gen_fcfid, 0x1)),
-        ("bnslr+", (gen_bnslr, 0x200000)),
-        ("sthu", (gen_sthu, 0x0)),
-        ("addeo.", (gen_adde, 0x401)),
-        ("lhzx", (gen_lhzx, 0x0)),
-        ("bdnzt-", (gen_bdnzt, 0x200000)),
-        ("rotlw", (gen_rotlw, 0x0)),
-        ("beql", (gen_beq, 0x1)),
-        ("vsum4shs", (gen_vsum4shs, 0x0)),
-        ("bdnzlr", (gen_bdnzlr, 0x0)),
-        ("vrefp", (gen_vrefp, 0x0)),
-        ("bdzta-", (gen_bdzt, 0x200002)),
-        ("beqla+", (gen_beq, 0x200003)),
-        ("stdx", (gen_stdx, 0x0)),
-        ("fctiwz", (gen_fctiwz, 0x0)),
-        ("blelrl", (gen_blelr, 0x1)),
-        ("cmpw", (gen_cmpw, 0x0)),
-        ("rotlw.", (gen_rotlw, 0x1)),
-        ("bdzt+", (gen_bdzt, 0x200000)),
-        ("blectrl", (gen_blectr, 0x1)),
-        ("bnsl+", (gen_bns, 0x200001)),
-        ("fmsub", (gen_fmsub, 0x0)),
-        ("rldimi.", (gen_rldimi, 0x1)),
-        ("vrfip128", (gen_vrfip128, 0x0)),
-        ("vspltw128", (gen_vspltw128, 0x0)),
-        ("beqla", (gen_beq, 0x3)),
-        ("vcmpgtub.", (gen_vcmpgtub, 0x400)),
-        ("divdu.", (gen_divdu, 0x1)),
-        ("mulhdu.", (gen_mulhdu, 0x1)),
-        ("blel-", (gen_ble, 0x200001)),
-        ("bnsctr+", (gen_bnsctr, 0x200000)),
-        ("vpkswus", (gen_vpkswus, 0x0)),
-        ("xor.", (gen_xor, 0x1)),
-        ("vcmpgtuh.", (gen_vcmpgtuh, 0x400)),
-        ("stdcx.", (gen_stdcx_, 0x0)),
-        ("mulldo", (gen_mulld, 0x400)),
-        ("vsubuwm", (gen_vsubuwm, 0x0)),
-        ("subfeo.", (gen_subfe, 0x401)),
-        ("neg", (gen_neg, 0x0)),
-        ("lvewx128", (gen_lvewx128, 0x0)),
-        ("bdzfl", (gen_bdzf, 0x1)),
-        ("beqctr+", (gen_beqctr, 0x200000)),
-        ("mfsrr0", (gen_mfsrr0, 0x0)),
-        ("vslo128", (gen_vslo128, 0x0)),
-        ("lfdx", (gen_lfdx, 0x0)),
-        ("bgectrl+", (gen_bgectr, 0x200001)),
-        ("addeo", (gen_adde, 0x400)),
-        ("vsubfp128", (gen_vsubfp128, 0x0)),
-        ("bgtl+", (gen_bgt, 0x200001)),
-        ("vpkuwum", (gen_vpkuwum, 0x0)),
-        ("vcmpbfp", (gen_vcmpbfp, 0x0)),
-        ("rfi", (gen_rfi, 0x0)),
-        ("ori", (gen_ori, 0x0)),
-        ("lis", (gen_lis, 0x0)),
-        ("extrwi.", (gen_extrwi, 0x1)),
-        ("cror", (gen_cror, 0x0)),
-        ("bdz", (gen_bdz, 0x0)),
-        ("extrwi", (gen_extrwi, 0x0)),
-        ("nop", (gen_nop, 0x0)),
-        ("bgtla-", (gen_bgt, 0x200003)),
-        ("subfmeo.", (gen_subfme, 0x401)),
-        ("bnectrl", (gen_bnectr, 0x1)),
-        ("bdnza-", (gen_bdnz, 0x200002)),
-        ("lvsr128", (gen_lvsr128, 0x0)),
-        ("bgtla+", (gen_bgt, 0x200003)),
-        ("bgel", (gen_bge, 0x1)),
-        ("mftb", (gen_mftb, 0x0)),
-        ("vmhraddshs", (gen_vmhraddshs, 0x0)),
-        ("bnsla+", (gen_bns, 0x200003)),
-        ("vcfsx", (gen_vcfsx, 0x0)),
-        ("bdnzflrl", (gen_bdnzflr, 0x1)),
-        ("vavgub", (gen_vavgub, 0x0)),
-        ("beqa", (gen_beq, 0x2)),
-        ("crnor", (gen_crnor, 0x0)),
-        ("crnot", (gen_crnot, 0x0)),
-        ("vnmsubfp128", (gen_vnmsubfp128, 0x0)),
-        ("b", (gen_b, 0x0)),
-        ("mtdsisr", (gen_mtdsisr, 0x0)),
-        ("bdnzfl", (gen_bdnzf, 0x1)),
-        ("fctiw.", (gen_fctiw, 0x1)),
-        ("stdu", (gen_stdu, 0x0)),
-        ("mulhwu", (gen_mulhwu, 0x0)),
-        ("vupkhsh", (gen_vupkhsh, 0x0)),
-        ("slwi", (gen_slwi, 0x0)),
-        ("vmsum4fp128", (gen_vmsum4fp128, 0x0)),
-        ("subfc", (gen_subfc, 0x0)),
-        ("vsro", (gen_vsro, 0x0)),
-        ("extsb.", (gen_extsb, 0x1)),
-        ("bnsctrl+", (gen_bnsctr, 0x200001)),
-        ("bnslr", (gen_bnslr, 0x0)),
-        ("bltctrl", (gen_bltctr, 0x1)),
-        ("rlwimi.", (gen_rlwimi, 0x1)),
-        ("cmpl", (gen_cmpl, 0x0)),
-        ("mulldo.", (gen_mulld, 0x401)),
-        ("addco", (gen_addc, 0x400)),
-        ("lhbrx", (gen_lhbrx, 0x0)),
-        ("bdzlrl+", (gen_bdzlr, 0x200001)),
-        ("bl", (gen_b, 0x1)),
-        ("blt-", (gen_blt, 0x200000)),
-        ("ld", (gen_ld, 0x0)),
-        ("bdza+", (gen_bdz, 0x200002)),
-        ("lfsu", (gen_lfsu, 0x0)),
-        ("eqv", (gen_eqv, 0x0)),
-        ("blta", (gen_blt, 0x2)),
-        ("rldcl.", (gen_rldcl, 0x1)),
-        ("lwzux", (gen_lwzux, 0x0)),
-        ("bdzlrl", (gen_bdzlr, 0x1)),
-        ("fneg.", (gen_fneg, 0x1)),
-        ("mtspr", (gen_mtspr, 0x0)),
-        ("subfze", (gen_subfze, 0x0)),
-        ("divdo.", (gen_divd, 0x401)),
-        ("rlwimi", (gen_rlwimi, 0x0)),
-        ("bdzl", (gen_bdz, 0x1)),
-        ("lwsync", (gen_lwsync, 0x0)),
-        ("mulli", (gen_mulli, 0x0)),
-        ("bnectr+", (gen_bnectr, 0x200000)),
-        ("stw", (gen_stw, 0x0)),
-        ("vcmpgefp", (gen_vcmpgefp, 0x0)),
-        ("stfsx", (gen_stfsx, 0x0)),
-        ("mfspr", (gen_mfspr, 0x0)),
-        ("sld.", (gen_sld, 0x1)),
-        ("mtdbatl", (gen_mtdbatl, 0x0)),
-        ("blel+", (gen_ble, 0x200001)),
-        ("vor128", (gen_vor128, 0x0)),
-        ("tdge", (gen_tdge, 0x0)),
-        ("mtsrd", (gen_mtsrd, 0x0)),
-        ("fcfid", (gen_fcfid, 0x0)),
-        ("bdnz-", (gen_bdnz, 0x200000)),
-        ("vavgsw", (gen_vavgsw, 0x0)),
-        ("vmsumuhm", (gen_vmsumuhm, 0x0)),
-        ("fmr", (gen_fmr, 0x0)),
-        ("vcmpbfp128", (gen_vcmpbfp128, 0x0)),
-        ("lvxl128", (gen_lvxl128, 0x0)),
-        ("vmaxfp128", (gen_vmaxfp128, 0x0)),
-        ("bnela", (gen_bne, 0x3)),
-        ("bdzlr", (gen_bdzlr, 0x0)),
-        ("bltctr", (gen_bltctr, 0x0)),
-        ("bgtlrl+", (gen_bgtlr, 0x200001)),
-        ("fnmadd.", (gen_fnmadd, 0x1)),
-        ("subfzeo.", (gen_subfze, 0x401)),
-        ("vsubshs", (gen_vsubshs, 0x0)),
-        ("lwz", (gen_lwz, 0x0)),
-        ("bdztla+", (gen_bdzt, 0x200003)),
-        ("vmsumshs", (gen_vmsumshs, 0x0)),
-        ("twui", (gen_twui, 0x0)),
-        ("bdnzfl-", (gen_bdnzf, 0x200001)),
-        ("vcmpgtsw", (gen_vcmpgtsw, 0x0)),
-        ("bclrl", (gen_bclr, 0x1)),
-        ("vmulosh", (gen_vmulosh, 0x0)),
-        ("bnsctr", (gen_bnsctr, 0x0)),
-        ("bdnzfa", (gen_bdnzf, 0x2)),
-        ("vmulesb", (gen_vmulesb, 0x0)),
-        ("blela", (gen_ble, 0x3)),
-        ("bcctr", (gen_bcctr, 0x0)),
-        ("vsr", (gen_vsr, 0x0)),
-        ("dcbz_l", (gen_dcbz_l, 0x0)),
-        ("divwo.", (gen_divw, 0x401)),
-        ("bnsctrl", (gen_bnsctr, 0x1)),
-        ("vaddfp", (gen_vaddfp, 0x0)),
-        ("blela-", (gen_ble, 0x200003)),
-        ("bc", (gen_bc, 0x0)),
-        ("vpkshss128", (gen_vpkshss128, 0x0)),
-        ("bdnzlrl+", (gen_bdnzlr, 0x200001)),
-        ("lfd", (gen_lfd, 0x0)),
-        ("bsoa+", (gen_bso, 0x200002)),
-        ("beq-", (gen_beq, 0x200000)),
-        ("beqlr+", (gen_beqlr, 0x200000)),
-        ("lvlxl128", (gen_lvlxl128, 0x0)),
-        ("subfo", (gen_subf, 0x400)),
-        ("vcmpgtsh", (gen_vcmpgtsh, 0x0)),
-        ("vcmpeqfp", (gen_vcmpeqfp, 0x0)),
-        ("vsububs", (gen_vsububs, 0x0)),
-        ("divdu", (gen_divdu, 0x0)),
-        ("bgtlrl", (gen_bgtlr, 0x1)),
-        ("cntlzw.", (gen_cntlzw, 0x1)),
-        ("subic", (gen_subic, 0x0)),
-        ("mulhd", (gen_mulhd, 0x0)),
-        ("bns-", (gen_bns, 0x200000)),
-        ("fsel", (gen_fsel, 0x0)),
-        ("stfdx", (gen_stfdx, 0x0)),
-        ("fnmsubs", (gen_fnmsubs, 0x0)),
-        ("bdnzlr+", (gen_bdnzlr, 0x200000)),
-        ("mfctr", (gen_mfctr, 0x0)),
-        ("fsubs", (gen_fsubs, 0x0)),
-        ("mtsrdin", (gen_mtsrdin, 0x0)),
-        ("vcmpequb", (gen_vcmpequb, 0x0)),
-        ("mtcrf", (gen_mtcrf, 0x0)),
-        ("divwo", (gen_divw, 0x400)),
-        ("nor", (gen_nor, 0x0)),
-        ("mtsrr1", (gen_mtsrr1, 0x0)),
-        ("vupkhpx", (gen_vupkhpx, 0x0)),
-        ("vsl", (gen_vsl, 0x0)),
-        ("vcfux", (gen_vcfux, 0x0)),
-        ("nand", (gen_nand, 0x0)),
-        ("subfzeo", (gen_subfze, 0x400)),
-        ("bdztla-", (gen_bdzt, 0x200003)),
-        ("vcmpeqfp128", (gen_vcmpeqfp128, 0x0)),
-        ("addze.", (gen_addze, 0x1)),
-        ("vupkhsb128", (gen_vupkhsb128, 0x0)),
-        ("bctr", (gen_bctr, 0x0)),
-        ("addic", (gen_addic, 0x0)),
-        ("beq", (gen_beq, 0x0)),
-        ("bne-", (gen_bne, 0x200000)),
-        ("vcmpgtsb.", (gen_vcmpgtsb, 0x400)),
-        ("vrlh", (gen_vrlh, 0x0)),
-        ("bsola-", (gen_bso, 0x200003)),
-        ("bdnzlrl", (gen_bdnzlr, 0x1)),
-        ("vpermwi128", (gen_vpermwi128, 0x0)),
-        ("slbia", (gen_slbia, 0x0)),
-        ("vaddsws", (gen_vaddsws, 0x0)),
-        ("orc.", (gen_orc, 0x1)),
-        ("mtfsf", (gen_mtfsf, 0x0)),
-        ("bdzflrl+", (gen_bdzflr, 0x200001)),
-        ("beqa-", (gen_beq, 0x200002)),
-        ("lbzx", (gen_lbzx, 0x0)),
-        ("vsrw", (gen_vsrw, 0x0)),
-        ("vpkshss", (gen_vpkshss, 0x0)),
-        ("lvebx", (gen_lvebx, 0x0)),
-        ("bgtctrl", (gen_bgtctr, 0x1)),
-        ("or.", (gen_or, 0x1)),
-        ("bgectr+", (gen_bgectr, 0x200000)),
-        ("vrsqrtefp", (gen_vrsqrtefp, 0x0)),
-        ("blectr+", (gen_blectr, 0x200000)),
-        ("lswx", (gen_lswx, 0x0)),
-        ("bdnz", (gen_bdnz, 0x0)),
-        ("bdzflr+", (gen_bdzflr, 0x200000)),
-        ("vor", (gen_vor, 0x0)),
-        ("vandc", (gen_vandc, 0x0)),
-        ("lvx", (gen_lvx, 0x0)),
-        ("ecowx", (gen_ecowx, 0x0)),
-        ("bc+", (gen_bc, 0x200000)),
-        ("andis.", (gen_andis_, 0x0)),
-        ("vrfim", (gen_vrfim, 0x0)),
-        ("stfiwx", (gen_stfiwx, 0x0)),
-        ("bnelr", (gen_bnelr, 0x0)),
-        ("lhzux", (gen_lhzux, 0x0)),
-        ("stwcx.", (gen_stwcx_, 0x0)),
-        ("addzeo.", (gen_addze, 0x401)),
-        ("mfmsr", (gen_mfmsr, 0x0)),
-        ("stvxl128", (gen_stvxl128, 0x0)),
-        ("bdzfa+", (gen_bdzf, 0x200002)),
-        ("vsldoi", (gen_vsldoi, 0x0)),
-        ("bgel-", (gen_bge, 0x200001)),
-        ("vpkshus", (gen_vpkshus, 0x0)),
-        ("srw.", (gen_srw, 0x1)),
-        ("beqlrl", (gen_beqlr, 0x1)),
-        ("stvrx128", (gen_stvrx128, 0x0)),
-        ("vcmpequh.", (gen_vcmpequh, 0x400)),
-        ("bdztla", (gen_bdzt, 0x3)),
-        ("eqv.", (gen_eqv, 0x1)),
-        ("vpkuwus128", (gen_vpkuwus128, 0x0)),
-        ("bltlr", (gen_bltlr, 0x0)),
-        ("beqctr", (gen_beqctr, 0x0)),
-        ("lwzx", (gen_lwzx, 0x0)),
-        ("rlwnm.", (gen_rlwnm, 0x1)),
-        ("rldcl", (gen_rldcl, 0x0)),
-        ("bdnzta+", (gen_bdnzt, 0x200002)),
-        ("cntlzw", (gen_cntlzw, 0x0)),
-        ("cntlzd.", (gen_cntlzd, 0x1)),
-        ("vaddubm", (gen_vaddubm, 0x0)),
-        ("mtlr", (gen_mtlr, 0x0)),
-        ("rotld", (gen_rotld, 0x0)),
-        ("addo", (gen_add, 0x400)),
-        ("vcmpgtuw", (gen_vcmpgtuw, 0x0)),
-        ("bge-", (gen_bge, 0x200000)),
-        ("vspltish", (gen_vspltish, 0x0)),
-        ("vcmpeqfp.", (gen_vcmpeqfp, 0x400)),
-        ("vmulosb", (gen_vmulosb, 0x0)),
-        ("mullwo.", (gen_mullw, 0x401)),
-        ("vmaddfp", (gen_vmaddfp, 0x0)),
-        ("fneg", (gen_fneg, 0x0)),
-        ("bltl", (gen_blt, 0x1)),
-        ("stwu", (gen_stwu, 0x0)),
-        ("fdiv.", (gen_fdiv, 0x1)),
-        ("bnsa", (gen_bns, 0x2)),
-        ("fmr.", (gen_fmr, 0x1)),
-        ("sthbrx", (gen_sthbrx, 0x0)),
-        ("lhz", (gen_lhz, 0x0)),
-        ("beq+", (gen_beq, 0x200000)),
-        ("bclr+", (gen_bclr, 0x200000)),
-        ("vlogefp128", (gen_vlogefp128, 0x0)),
-        ("eieio", (gen_eieio, 0x0)),
-        ("vsrw128", (gen_vsrw128, 0x0)),
-        ("addme", (gen_addme, 0x0)),
-        ("crnand", (gen_crnand, 0x0)),
-        ("mfdsisr", (gen_mfdsisr, 0x0)),
-        ("dstst", (gen_dstst, 0x0)),
-        ("bsoctrl+", (gen_bsoctr, 0x200001)),
-        ("fmsubs", (gen_fmsubs, 0x0)),
-        ("icbi", (gen_icbi, 0x0)),
-        ("vsrh", (gen_vsrh, 0x0)),
-        ("tdi", (gen_tdi, 0x0)),
-        ("bdzta", (gen_bdzt, 0x2)),
-        ("vcmpequw128", (gen_vcmpequw128, 0x0)),
-        ("vmulouh", (gen_vmulouh, 0x0)),
-        ("tdnei", (gen_tdnei, 0x0)),
-        ("fnmsub", (gen_fnmsub, 0x0)),
-        ("extsh.", (gen_extsh, 0x1)),
-        ("crclr", (gen_crclr, 0x0)),
-        ("fadds", (gen_fadds, 0x0)),
-        ("dstt", (gen_dst, 0x2000000)),
-        ("bne+", (gen_bne, 0x200000)),
-        ("rlwinm.", (gen_rlwinm, 0x1)),
-        ("subfme", (gen_subfme, 0x0)),
-        ("lha", (gen_lha, 0x0)),
-        ("tw", (gen_tw, 0x0)),
-        ("bsolr", (gen_bsolr, 0x0)),
-        ("divd.", (gen_divd, 0x1)),
-        ("bnel-", (gen_bne, 0x200001)),
-        ("vcuxwfp128", (gen_vcuxwfp128, 0x0)),
-        ("vmrglb", (gen_vmrglb, 0x0)),
-        ("mfear", (gen_mfear, 0x0)),
-        ("srad", (gen_srad, 0x0)),
-        ("subfze.", (gen_subfze, 0x1)),
-        ("bnsl-", (gen_bns, 0x200001)),
-        ("vxor", (gen_vxor, 0x0)),
-        ("bdzla", (gen_bdz, 0x3)),
-        ("bltl-", (gen_blt, 0x200001)),
-        ("bgelr", (gen_bgelr, 0x0)),
-        ("mtibatu", (gen_mtibatu, 0x0)),
-        ("vsldoi128", (gen_vsldoi128, 0x0)),
-        ("lwarx", (gen_lwarx, 0x0)),
-        ("bgela-", (gen_bge, 0x200003)),
-        ("stfd", (gen_stfd, 0x0)),
-        ("blea+", (gen_ble, 0x200002)),
-        ("vmuloub", (gen_vmuloub, 0x0)),
-        ("vpkuhum128", (gen_vpkuhum128, 0x0)),
-        ("vsplth", (gen_vsplth, 0x0)),
-        ("vrfin128", (gen_vrfin128, 0x0)),
-        ("vrfin", (gen_vrfin, 0x0)),
-        ("srwi.", (gen_srwi, 0x1)),
-        ("fmadd.", (gen_fmadd, 0x1)),
-        ("bctrl", (gen_bctr, 0x1)),
+        ("dcbf", (gen_dcbf, 0x0)),
         ("blta-", (gen_blt, 0x200002)),
-        ("slbie", (gen_slbie, 0x0)),
-        ("mulld.", (gen_mulld, 0x1)),
-        ("orc", (gen_orc, 0x0)),
-        ("vaddfp128", (gen_vaddfp128, 0x0)),
-        ("bdzfl+", (gen_bdzf, 0x200001)),
-        ("bdnz+", (gen_bdnz, 0x200000)),
-        ("mcrxr", (gen_mcrxr, 0x0)),
-        ("bcl-", (gen_bc, 0x200001)),
-        ("beqlrl+", (gen_beqlr, 0x200001)),
-        ("stfsux", (gen_stfsux, 0x0)),
-        ("rlwnm", (gen_rlwnm, 0x0)),
-        ("bdztl", (gen_bdzt, 0x1)),
-        ("bcctrl+", (gen_bcctr, 0x200001)),
-        ("srd.", (gen_srd, 0x1)),
-        ("bnsla-", (gen_bns, 0x200003)),
-        ("bc-", (gen_bc, 0x200000)),
-        ("clrlwi", (gen_clrlwi, 0x0)),
-        ("vavgsb", (gen_vavgsb, 0x0)),
-        ("vrlb", (gen_vrlb, 0x0)),
-        ("bgea-", (gen_bge, 0x200002)),
-        ("ble+", (gen_ble, 0x200000)),
-        ("vupkhsb", (gen_vupkhsb, 0x0)),
-        ("vmulfp128", (gen_vmulfp128, 0x0)),
-        ("bltl+", (gen_blt, 0x200001)),
-        ("bdza-", (gen_bdz, 0x200002)),
-        ("vmsum3fp128", (gen_vmsum3fp128, 0x0)),
-        ("mtctr", (gen_mtctr, 0x0)),
-        ("dst", (gen_dst, 0x0)),
-        ("crset", (gen_crset, 0x0)),
-        ("vaddcuw", (gen_vaddcuw, 0x0)),
-        ("vmsummbm", (gen_vmsummbm, 0x0)),
-        ("stvrxl128", (gen_stvrxl128, 0x0)),
-        ("sthux", (gen_sthux, 0x0)),
-        ("bgt-", (gen_bgt, 0x200000)),
-        ("bdzla-", (gen_bdz, 0x200003)),
-        ("bdnzfla-", (gen_bdnzf, 0x200003)),
-        ("rotlwi", (gen_rotlwi, 0x0)),
-        ("lfdux", (gen_lfdux, 0x0)),
-        ("nego.", (gen_neg, 0x401)),
-        ("lvxl", (gen_lvxl, 0x0)),
-        ("cmpli", (gen_cmpli, 0x0)),
-        ("vmrglw", (gen_vmrglw, 0x0)),
-        ("fmul.", (gen_fmul, 0x1)),
-        ("fctidz", (gen_fctidz, 0x0)),
-        ("mtvscr", (gen_mtvscr, 0x0)),
-        ("blea-", (gen_ble, 0x200002)),
-        ("addmeo.", (gen_addme, 0x401)),
-        ("vminfp128", (gen_vminfp128, 0x0)),
-        ("bnela+", (gen_bne, 0x200003)),
-        ("bdzf-", (gen_bdzf, 0x200000)),
-        ("vcfpsxws128", (gen_vcfpsxws128, 0x0)),
-        ("vcmpeqfp128.", (gen_vcmpeqfp128, 0x40)),
-        ("fadds.", (gen_fadds, 0x1)),
-        ("bnela-", (gen_bne, 0x200003)),
-        ("sradi.", (gen_sradi, 0x1)),
-        ("blr", (gen_blr, 0x0)),
-        ("vmrghw", (gen_vmrghw, 0x0)),
-        ("bdzta+", (gen_bdzt, 0x200002)),
-        ("cmpwi", (gen_cmpwi, 0x0)),
-        ("addc", (gen_addc, 0x0)),
-        ("ldx", (gen_ldx, 0x0)),
-        ("vrlimi128", (gen_vrlimi128, 0x0)),
-        ("stvx128", (gen_stvx128, 0x0)),
-        ("mfdar", (gen_mfdar, 0x0)),
-        ("cmplw", (gen_cmplw, 0x0)),
-        ("frsqrte", (gen_frsqrte, 0x0)),
-        ("bgta+", (gen_bgt, 0x200002)),
-        ("tweq", (gen_tweq, 0x0)),
-        ("vslo", (gen_vslo, 0x0)),
-        ("and", (gen_and, 0x0)),
-        ("bgta-", (gen_bgt, 0x200002)),
-        ("vcmpgefp128", (gen_vcmpgefp128, 0x0)),
-        ("rotld.", (gen_rotld, 0x1)),
-        ("vpkshus128", (gen_vpkshus128, 0x0)),
-        ("vrlw", (gen_vrlw, 0x0)),
-        ("vpkuwum128", (gen_vpkuwum128, 0x0)),
-        ("stvehx", (gen_stvehx, 0x0)),
-        ("mtear", (gen_mtear, 0x0)),
-        ("andi.", (gen_andi_, 0x0)),
-        ("mullw", (gen_mullw, 0x0)),
-        ("bsoa-", (gen_bso, 0x200002)),
-        ("stvewx", (gen_stvewx, 0x0)),
-        ("mtsdr1", (gen_mtsdr1, 0x0)),
-        ("mttbu", (gen_mttbu, 0x0)),
-        ("vmaddfp128", (gen_vmaddfp128, 0x0)),
-        ("bla", (gen_b, 0x3)),
-        ("bdnzflrl+", (gen_bdnzflr, 0x200001)),
-        ("or", (gen_or, 0x0)),
-        ("bnel", (gen_bne, 0x1)),
-        ("lfsx", (gen_lfsx, 0x0)),
-        ("mfdbatl", (gen_mfdbatl, 0x0)),
-        ("mtibatl", (gen_mtibatl, 0x0)),
-        ("cmplwi", (gen_cmplwi, 0x0)),
-        ("bltctrl+", (gen_bltctr, 0x200001)),
-        ("frsp.", (gen_frsp, 0x1)),
-        ("fres", (gen_fres, 0x0)),
-        ("lwaux", (gen_lwaux, 0x0)),
-        ("vadduwm", (gen_vadduwm, 0x0)),
-        ("vcmpequw.", (gen_vcmpequw, 0x400)),
-        ("stvebx", (gen_stvebx, 0x0)),
-        ("bdnzt+", (gen_bdnzt, 0x200000)),
-        ("addo.", (gen_add, 0x401)),
-        ("bcla", (gen_bc, 0x3)),
-        ("vmsumubm", (gen_vmsumubm, 0x0)),
-        ("bdzflrl", (gen_bdzflr, 0x1)),
+        ("divwu.", (gen_divwu, 0x1)),
+        ("bdz+", (gen_bdz, 0x200000)),
+        ("vandc128", (gen_vandc128, 0x0)),
+        ("stvlx128", (gen_stvlx128, 0x0)),
+        ("bgtlrl", (gen_bgtlr, 0x1)),
+        ("bso+", (gen_bso, 0x200000)),
+        ("xor", (gen_xor, 0x0)),
+        ("eqv.", (gen_eqv, 0x1)),
         ("vcmpequh", (gen_vcmpequh, 0x0)),
-        ("vminsw", (gen_vminsw, 0x0)),
-        ("sradi", (gen_sradi, 0x0)),
-        ("bdnztla-", (gen_bdnzt, 0x200003)),
-        ("bnectr", (gen_bnectr, 0x0)),
-        ("fmuls.", (gen_fmuls, 0x1)),
-        ("blt", (gen_blt, 0x0)),
-        ("lvewx", (gen_lvewx, 0x0)),
-        ("ble", (gen_ble, 0x0)),
-        ("bcla+", (gen_bc, 0x200003)),
-        ("vupklsb", (gen_vupklsb, 0x0)),
-        ("bgelr+", (gen_bgelr, 0x200000)),
-        ("beqlr", (gen_beqlr, 0x0)),
-        ("bsol-", (gen_bso, 0x200001)),
-        ("fmadds.", (gen_fmadds, 0x1)),
-        ("andc.", (gen_andc, 0x1)),
-        ("stfdux", (gen_stfdux, 0x0)),
-        ("clrrwi", (gen_clrrwi, 0x0)),
-        ("rldicl", (gen_rldicl, 0x0)),
-        ("stb", (gen_stb, 0x0)),
-        ("vmrghh", (gen_vmrghh, 0x0)),
-        ("bdzt", (gen_bdzt, 0x0)),
-        ("bdztlr", (gen_bdztlr, 0x0)),
-        ("bdnztl", (gen_bdnzt, 0x1)),
-        ("lwax", (gen_lwax, 0x0)),
-        ("vpkuhus", (gen_vpkuhus, 0x0)),
-        ("divduo.", (gen_divdu, 0x401)),
-        ("mtfsfi.", (gen_mtfsfi, 0x1)),
-        ("clrlslwi", (gen_clrlslwi, 0x0)),
-        ("lvrxl128", (gen_lvrxl128, 0x0)),
-        ("bns+", (gen_bns, 0x200000)),
-        ("bdztlrl+", (gen_bdztlr, 0x200001)),
-        ("fmul", (gen_fmul, 0x0)),
-        ("mtdbatu", (gen_mtdbatu, 0x0)),
-        ("mullwo", (gen_mullw, 0x400)),
-        ("srawi.", (gen_srawi, 0x1)),
-        ("vcmpgtuw.", (gen_vcmpgtuw, 0x400)),
-        ("bsol", (gen_bso, 0x1)),
-        ("vsrb", (gen_vsrb, 0x0)),
-        ("mfvscr", (gen_mfvscr, 0x0)),
-        ("vperm", (gen_vperm, 0x0)),
-        ("std", (gen_std, 0x0)),
-        ("srwi", (gen_srwi, 0x0)),
-        ("lbzu", (gen_lbzu, 0x0)),
-        ("subfo.", (gen_subf, 0x401)),
-        ("vmaxfp", (gen_vmaxfp, 0x0)),
-        ("vaddubs", (gen_vaddubs, 0x0)),
-        ("vcmpbfp128.", (gen_vcmpbfp128, 0x40)),
-        ("lhax", (gen_lhax, 0x0)),
-        ("ldu", (gen_ldu, 0x0)),
-        ("vnot", (gen_vnot, 0x0)),
-        ("bsolr+", (gen_bsolr, 0x200000)),
-        ("bcl+", (gen_bc, 0x200001)),
-        ("bca", (gen_bc, 0x2)),
-        ("sth", (gen_sth, 0x0)),
-        ("bdnzflr+", (gen_bdnzflr, 0x200000)),
-        ("rldicr", (gen_rldicr, 0x0)),
-        ("rotlwi.", (gen_rotlwi, 0x1)),
-        ("vmrghw128", (gen_vmrghw128, 0x0)),
-        ("mffs.", (gen_mffs, 0x1)),
-        ("eciwx", (gen_eciwx, 0x0)),
-        ("oris", (gen_oris, 0x0)),
+        ("stswx", (gen_stswx, 0x0)),
+        ("cntlzw", (gen_cntlzw, 0x0)),
+        ("bltlrl+", (gen_bltlr, 0x200001)),
+        ("cmpi", (gen_cmpi, 0x0)),
+        ("srwi.", (gen_srwi, 0x1)),
+        ("fnmsubs.", (gen_fnmsubs, 0x1)),
+        ("lvxl128", (gen_lvxl128, 0x0)),
+        ("divwuo.", (gen_divwu, 0x401)),
+        ("subis", (gen_subis, 0x0)),
+        ("fctidz.", (gen_fctidz, 0x1)),
+        ("mcrfs", (gen_mcrfs, 0x0)),
+        ("bnsa", (gen_bns, 0x2)),
+        ("vcmpgtub.", (gen_vcmpgtub, 0x400)),
+        ("extsb", (gen_extsb, 0x0)),
+        ("dcbz_l", (gen_dcbz_l, 0x0)),
+        ("vmrglb", (gen_vmrglb, 0x0)),
+        ("beqa+", (gen_beq, 0x200002)),
+        ("bltl", (gen_blt, 0x1)),
+        ("eieio", (gen_eieio, 0x0)),
+        ("stvlxl", (gen_stvlxl, 0x0)),
+        ("bne+", (gen_bne, 0x200000)),
+        ("bdzlrl+", (gen_bdzlr, 0x200001)),
+        ("mfdar", (gen_mfdar, 0x0)),
+        ("stbux", (gen_stbux, 0x0)),
+        ("bdztla", (gen_bdzt, 0x3)),
+        ("beqla+", (gen_beq, 0x200003)),
+        ("vcmpgtub", (gen_vcmpgtub, 0x0)),
+        ("vavgsh", (gen_vavgsh, 0x0)),
+        ("orc", (gen_orc, 0x0)),
+        ("tw", (gen_tw, 0x0)),
+        ("vsububs", (gen_vsububs, 0x0)),
+        ("vrsqrtefp", (gen_vrsqrtefp, 0x0)),
         ("mflr", (gen_mflr, 0x0)),
-        ("dcbst", (gen_dcbst, 0x0)),
+        ("vcmpgtfp.", (gen_vcmpgtfp, 0x400)),
+        ("lwaux", (gen_lwaux, 0x0)),
+        ("vnot", (gen_vnot, 0x0)),
+        ("bsoa+", (gen_bso, 0x200002)),
+        ("bdnza", (gen_bdnz, 0x2)),
+        ("bdnza-", (gen_bdnz, 0x200002)),
+        ("vcfpsxws128", (gen_vcfpsxws128, 0x0)),
+        ("xoris", (gen_xoris, 0x0)),
+        ("vsl", (gen_vsl, 0x0)),
+        ("vaddfp128", (gen_vaddfp128, 0x0)),
+        ("vmrglw128", (gen_vmrglw128, 0x0)),
+        ("frsp", (gen_frsp, 0x0)),
+        ("mulhwu.", (gen_mulhwu, 0x1)),
+        ("bnsla", (gen_bns, 0x3)),
+        ("stbu", (gen_stbu, 0x0)),
+        ("cntlzw.", (gen_cntlzw, 0x1)),
+        ("vaddfp", (gen_vaddfp, 0x0)),
+        ("vaddsbs", (gen_vaddsbs, 0x0)),
+        ("vnmsubfp128", (gen_vnmsubfp128, 0x0)),
+        ("fmsubs.", (gen_fmsubs, 0x1)),
+        ("lis", (gen_lis, 0x0)),
+        ("rldicl", (gen_rldicl, 0x0)),
+        ("xori", (gen_xori, 0x0)),
+        ("srawi", (gen_srawi, 0x0)),
+        ("addzeo.", (gen_addze, 0x401)),
+        ("vor128", (gen_vor128, 0x0)),
+        ("mtfsb0", (gen_mtfsb0, 0x0)),
+        ("stfs", (gen_stfs, 0x0)),
+        ("bgta", (gen_bgt, 0x2)),
+        ("mfsrin", (gen_mfsrin, 0x0)),
+        ("bdnztlr+", (gen_bdnztlr, 0x200000)),
+        ("mfmsr", (gen_mfmsr, 0x0)),
         ("bnelr+", (gen_bnelr, 0x200000)),
+        ("bdnzflrl+", (gen_bdnzflr, 0x200001)),
+        ("vmsum4fp128", (gen_vmsum4fp128, 0x0)),
+        ("bgt-", (gen_bgt, 0x200000)),
+        ("bdzta", (gen_bdzt, 0x2)),
+        ("srawi.", (gen_srawi, 0x1)),
+        ("fctiwz", (gen_fctiwz, 0x0)),
+        ("vupklsb128", (gen_vupklsb128, 0x0)),
+        ("stb", (gen_stb, 0x0)),
+        ("cmpld", (gen_cmpld, 0x0)),
+        ("vperm128", (gen_vperm128, 0x0)),
+        ("bdnzfa-", (gen_bdnzf, 0x200002)),
+        ("cmpd", (gen_cmpd, 0x0)),
+        ("vsum4ubs", (gen_vsum4ubs, 0x0)),
+        ("eciwx", (gen_eciwx, 0x0)),
+        ("addzeo", (gen_addze, 0x400)),
+        ("fctid", (gen_fctid, 0x0)),
+        ("lvx128", (gen_lvx128, 0x0)),
+        ("nand.", (gen_nand, 0x1)),
+        ("bnea-", (gen_bne, 0x200002)),
+        ("bnectr+", (gen_bnectr, 0x200000)),
+        ("dcbi", (gen_dcbi, 0x0)),
+        ("vcuxwfp128", (gen_vcuxwfp128, 0x0)),
+        ("vminfp128", (gen_vminfp128, 0x0)),
+        ("vrsqrtefp128", (gen_vrsqrtefp128, 0x0)),
+        ("icbi.", (gen_icbi, 0x1)),
+        ("mulld", (gen_mulld, 0x0)),
+        ("lswi", (gen_lswi, 0x0)),
+        ("stvlxl128", (gen_stvlxl128, 0x0)),
+        ("fcmpu", (gen_fcmpu, 0x0)),
+        ("bdnzt", (gen_bdnzt, 0x0)),
+        ("vspltisw", (gen_vspltisw, 0x0)),
+        ("cmplwi", (gen_cmplwi, 0x0)),
+        ("slw", (gen_slw, 0x0)),
+        ("stbx", (gen_stbx, 0x0)),
+        ("bgtla+", (gen_bgt, 0x200003)),
+        ("mfibatl", (gen_mfibatl, 0x0)),
+        ("clrrwi.", (gen_clrrwi, 0x1)),
+        ("stvxl128", (gen_stvxl128, 0x0)),
+        ("rlwnm", (gen_rlwnm, 0x0)),
+        ("addis", (gen_addis, 0x0)),
+        ("sthbrx", (gen_sthbrx, 0x0)),
+        ("bne", (gen_bne, 0x0)),
+        ("divwo.", (gen_divw, 0x401)),
+        ("lwsync", (gen_lwsync, 0x0)),
+        ("vmsumshs", (gen_vmsumshs, 0x0)),
+        ("bnectr", (gen_bnectr, 0x0)),
+        ("stfd", (gen_stfd, 0x0)),
+        ("bc-", (gen_bc, 0x200000)),
+        ("bltlr", (gen_bltlr, 0x0)),
+        ("addeo", (gen_adde, 0x400)),
+        ("rldimi", (gen_rldimi, 0x0)),
+        ("mfear", (gen_mfear, 0x0)),
+        ("fnmadd", (gen_fnmadd, 0x0)),
+        ("bgtlrl+", (gen_bgtlr, 0x200001)),
+        ("vsel128", (gen_vsel128, 0x0)),
+        ("vcsxwfp128", (gen_vcsxwfp128, 0x0)),
+        ("blea+", (gen_ble, 0x200002)),
+        ("vcmpgtfp", (gen_vcmpgtfp, 0x0)),
+        ("vsraw128", (gen_vsraw128, 0x0)),
+        ("sraw", (gen_sraw, 0x0)),
+        ("sthux", (gen_sthux, 0x0)),
+        ("bsoa-", (gen_bso, 0x200002)),
+        ("vcmpeqfp.", (gen_vcmpeqfp, 0x400)),
+        ("bcctr+", (gen_bcctr, 0x200000)),
+        ("mffs", (gen_mffs, 0x0)),
+        ("vaddubs", (gen_vaddubs, 0x0)),
+        ("vcmpgtsb.", (gen_vcmpgtsb, 0x400)),
+        ("bnslr", (gen_bnslr, 0x0)),
+        ("bdztlr", (gen_bdztlr, 0x0)),
+        ("blelr", (gen_blelr, 0x0)),
+        ("bdzfla+", (gen_bdzf, 0x200003)),
+        ("bdnzl", (gen_bdnz, 0x1)),
+        ("lswx", (gen_lswx, 0x0)),
+        ("fnabs.", (gen_fnabs, 0x1)),
+        ("lmw", (gen_lmw, 0x0)),
+        ("tdlnl", (gen_tdlnl, 0x0)),
+        ("vminuw", (gen_vminuw, 0x0)),
+        ("mtdbatl", (gen_mtdbatl, 0x0)),
+        ("bnsl-", (gen_bns, 0x200001)),
+        ("bsola+", (gen_bso, 0x200003)),
+        ("mtdar", (gen_mtdar, 0x0)),
+        ("bdzt", (gen_bdzt, 0x0)),
+        ("and.", (gen_and, 0x1)),
+        ("bdza", (gen_bdz, 0x2)),
+        ("trap", (gen_trap, 0x0)),
+        ("vrfiz", (gen_vrfiz, 0x0)),
+        ("bcl+", (gen_bc, 0x200001)),
+        ("vrlb", (gen_vrlb, 0x0)),
+        ("mfibatu", (gen_mfibatu, 0x0)),
+        ("vadduhs", (gen_vadduhs, 0x0)),
+        ("beqa-", (gen_beq, 0x200002)),
+        ("bgt+", (gen_bgt, 0x200000)),
+        ("bso-", (gen_bso, 0x200000)),
+        ("bsoctrl", (gen_bsoctr, 0x1)),
+        ("rlwimi.", (gen_rlwimi, 0x1)),
+        ("mtxer", (gen_mtxer, 0x0)),
+        ("bgt", (gen_bgt, 0x0)),
+        ("nego", (gen_neg, 0x400)),
+        ("sraw.", (gen_sraw, 0x1)),
+        ("vxor", (gen_vxor, 0x0)),
+        ("bdz-", (gen_bdz, 0x200000)),
+        ("fcmpo", (gen_fcmpo, 0x0)),
+        ("vcmpeqfp128", (gen_vcmpeqfp128, 0x0)),
+        ("lhbrx", (gen_lhbrx, 0x0)),
+        ("vsumsws", (gen_vsumsws, 0x0)),
+        ("vrlw128", (gen_vrlw128, 0x0)),
+        ("subf", (gen_subf, 0x0)),
+        ("cmp", (gen_cmp, 0x0)),
+        ("vsubsws", (gen_vsubsws, 0x0)),
+        ("addi", (gen_addi, 0x0)),
+        ("stvrx", (gen_stvrx, 0x0)),
+        ("vsubuhm", (gen_vsubuhm, 0x0)),
+        ("vrfip", (gen_vrfip, 0x0)),
+        ("vrefp128", (gen_vrefp128, 0x0)),
+        ("bca-", (gen_bc, 0x200002)),
+        ("mtibatu", (gen_mtibatu, 0x0)),
+        ("mfsr", (gen_mfsr, 0x0)),
+        ("bdzlr", (gen_bdzlr, 0x0)),
+        ("fadd", (gen_fadd, 0x0)),
+        ("cmpwi", (gen_cmpwi, 0x0)),
+        ("vmsumshm", (gen_vmsumshm, 0x0)),
+        ("lvx", (gen_lvx, 0x0)),
+        ("vcmpgtuh.", (gen_vcmpgtuh, 0x400)),
+        ("fdiv", (gen_fdiv, 0x0)),
+        ("fctid.", (gen_fctid, 0x1)),
+        ("addic", (gen_addic, 0x0)),
+        ("bc", (gen_bc, 0x0)),
+        ("vsubcuw", (gen_vsubcuw, 0x0)),
+        ("vsubuhs", (gen_vsubuhs, 0x0)),
+        ("vperm", (gen_vperm, 0x0)),
+        ("subfco", (gen_subfc, 0x400)),
+        ("bsola-", (gen_bso, 0x200003)),
+        ("bnsla-", (gen_bns, 0x200003)),
+        ("stdux", (gen_stdux, 0x0)),
+        ("bdnz-", (gen_bdnz, 0x200000)),
+        ("divw.", (gen_divw, 0x1)),
+        ("andi.", (gen_andi_, 0x0)),
+        ("bgelrl+", (gen_bgelr, 0x200001)),
+        ("mtsprg", (gen_mtsprg, 0x0)),
+        ("bdnztla", (gen_bdnzt, 0x3)),
+        ("vpkuhus", (gen_vpkuhus, 0x0)),
+        ("subf.", (gen_subf, 0x1)),
+        ("crnot", (gen_crnot, 0x0)),
+        ("bdnzla+", (gen_bdnz, 0x200003)),
+        ("bdzta+", (gen_bdzt, 0x200002)),
+        ("lvehx", (gen_lvehx, 0x0)),
+        ("clrlslwi", (gen_clrlslwi, 0x0)),
+        ("bgtla-", (gen_bgt, 0x200003)),
+        ("stvewx128", (gen_stvewx128, 0x0)),
+        ("lfd", (gen_lfd, 0x0)),
+        ("vpkuwus128", (gen_vpkuwus128, 0x0)),
+        ("blelrl", (gen_blelr, 0x1)),
+        ("andis.", (gen_andis_, 0x0)),
+        ("lfs", (gen_lfs, 0x0)),
+        ("bdzfl-", (gen_bdzf, 0x200001)),
+        ("vrfim", (gen_vrfim, 0x0)),
+        ("fnmadds.", (gen_fnmadds, 0x1)),
+        ("stfsx", (gen_stfsx, 0x0)),
+        ("vpkuhum", (gen_vpkuhum, 0x0)),
+        ("lfsu", (gen_lfsu, 0x0)),
+        ("bltla", (gen_blt, 0x3)),
+        ("mtfsfi", (gen_mtfsfi, 0x0)),
+        ("bdnzt-", (gen_bdnzt, 0x200000)),
+        ("mfsrr0", (gen_mfsrr0, 0x0)),
+        ("bgelr", (gen_bgelr, 0x0)),
+        ("ba", (gen_b, 0x2)),
+        ("lwzu", (gen_lwzu, 0x0)),
+        ("vcfsx", (gen_vcfsx, 0x0)),
+        ("vminsw", (gen_vminsw, 0x0)),
+        ("xor.", (gen_xor, 0x1)),
+        ("ldarx", (gen_ldarx, 0x0)),
+        ("frsqrte.", (gen_frsqrte, 0x1)),
+        ("mtsrr0", (gen_mtsrr0, 0x0)),
+        ("blel-", (gen_ble, 0x200001)),
+        ("rlwimi", (gen_rlwimi, 0x0)),
+        ("stvrxl128", (gen_stvrxl128, 0x0)),
+        ("addc", (gen_addc, 0x0)),
+        ("vcmpequw128", (gen_vcmpequw128, 0x0)),
+        ("addc.", (gen_addc, 0x1)),
+        ("vmaxub", (gen_vmaxub, 0x0)),
+        ("subfco.", (gen_subfc, 0x401)),
+        ("vpkuwum", (gen_vpkuwum, 0x0)),
+        ("divduo", (gen_divdu, 0x400)),
+        ("stdcx.", (gen_stdcx_, 0x0)),
+        ("lhax", (gen_lhax, 0x0)),
+        ("vsraw", (gen_vsraw, 0x0)),
+        ("rldic.", (gen_rldic, 0x1)),
+        ("bge+", (gen_bge, 0x200000)),
+        ("bge", (gen_bge, 0x0)),
+        ("vmaxuh", (gen_vmaxuh, 0x0)),
+        ("divdo.", (gen_divd, 0x401)),
+        ("stwcx.", (gen_stwcx_, 0x0)),
+        ("lhzu", (gen_lhzu, 0x0)),
+        ("bdnz", (gen_bdnz, 0x0)),
+        ("vcmpgtuw.", (gen_vcmpgtuw, 0x400)),
+        ("lvsr128", (gen_lvsr128, 0x0)),
+        ("bnel+", (gen_bne, 0x200001)),
+        ("mcrf", (gen_mcrf, 0x0)),
+        ("bns", (gen_bns, 0x0)),
+        ("bgelr+", (gen_bgelr, 0x200000)),
+        ("fctidz", (gen_fctidz, 0x0)),
+        ("bltlr+", (gen_bltlr, 0x200000)),
+        ("sradi", (gen_sradi, 0x0)),
+        ("vlogefp", (gen_vlogefp, 0x0)),
+        ("vadduwm", (gen_vadduwm, 0x0)),
+        ("vrlh", (gen_vrlh, 0x0)),
+        ("fmr.", (gen_fmr, 0x1)),
+        ("subfeo", (gen_subfe, 0x400)),
+        ("mfdec", (gen_mfdec, 0x0)),
+        ("vmuleub", (gen_vmuleub, 0x0)),
+        ("stvx", (gen_stvx, 0x0)),
+        ("tlbsync", (gen_tlbsync, 0x0)),
+        ("bdza+", (gen_bdz, 0x200002)),
+        ("fctiw", (gen_fctiw, 0x0)),
+        ("vmulouh", (gen_vmulouh, 0x0)),
+        ("andc", (gen_andc, 0x0)),
+        ("vrfiz128", (gen_vrfiz128, 0x0)),
+        ("mullwo", (gen_mullw, 0x400)),
+        ("blt-", (gen_blt, 0x200000)),
+        ("frsqrte", (gen_frsqrte, 0x0)),
+        ("mtcrf", (gen_mtcrf, 0x0)),
+        ("bdnz+", (gen_bdnz, 0x200000)),
+        ("bgectr", (gen_bgectr, 0x0)),
+        ("vcmpbfp", (gen_vcmpbfp, 0x0)),
+        ("beql", (gen_beq, 0x1)),
+        ("bdnzflrl", (gen_bdnzflr, 0x1)),
+        ("bnsa+", (gen_bns, 0x200002)),
+        ("bclr+", (gen_bclr, 0x200000)),
+        ("stfdx", (gen_stfdx, 0x0)),
+        ("vminuh", (gen_vminuh, 0x0)),
+        ("bnelr", (gen_bnelr, 0x0)),
+        ("bdzt+", (gen_bdzt, 0x200000)),
+        ("beql+", (gen_beq, 0x200001)),
+        ("stvrxl", (gen_stvrxl, 0x0)),
+        ("rotrwi", (gen_rotrwi, 0x0)),
+        ("rldicl.", (gen_rldicl, 0x1)),
+        ("bca", (gen_bc, 0x2)),
+        ("bltctr+", (gen_bltctr, 0x200000)),
+        ("bnslrl+", (gen_bnslr, 0x200001)),
+        ("srd.", (gen_srd, 0x1)),
+        ("lfdx", (gen_lfdx, 0x0)),
+        ("crnand", (gen_crnand, 0x0)),
+        ("subfze", (gen_subfze, 0x0)),
+        ("vsrah", (gen_vsrah, 0x0)),
+        ("bdnzl-", (gen_bdnz, 0x200001)),
+        ("vcmpequb", (gen_vcmpequb, 0x0)),
+        ("lhz", (gen_lhz, 0x0)),
+        ("bdnzf+", (gen_bdnzf, 0x200000)),
+        ("bnelrl+", (gen_bnelr, 0x200001)),
+        ("fdiv.", (gen_fdiv, 0x1)),
+        ("divd.", (gen_divd, 0x1)),
+        ("mtsrdin", (gen_mtsrdin, 0x0)),
+        ("vpkswss", (gen_vpkswss, 0x0)),
+        ("bdnzta-", (gen_bdnzt, 0x200002)),
+        ("bdzfl+", (gen_bdzf, 0x200001)),
+        ("slbie", (gen_slbie, 0x0)),
+        ("divdu", (gen_divdu, 0x0)),
+        ("dcbt", (gen_dcbt, 0x0)),
+        ("std", (gen_std, 0x0)),
+        ("stvehx", (gen_stvehx, 0x0)),
+        ("beq-", (gen_beq, 0x200000)),
+        ("bnel", (gen_bne, 0x1)),
+        ("bsoa", (gen_bso, 0x2)),
+        ("bgea-", (gen_bge, 0x200002)),
+        ("ori", (gen_ori, 0x0)),
+        ("eqv", (gen_eqv, 0x0)),
+        ("bnsctr", (gen_bnsctr, 0x0)),
+        ("dcbst", (gen_dcbst, 0x0)),
+        ("addmeo", (gen_addme, 0x400)),
+        ("tlbie", (gen_tlbie, 0x0)),
+        ("divdu.", (gen_divdu, 0x1)),
+        ("vcmpgefp.", (gen_vcmpgefp, 0x400)),
+        ("td", (gen_td, 0x0)),
+        ("mr.", (gen_mr, 0x1)),
+        ("mulhdu.", (gen_mulhdu, 0x1)),
+        ("bsoctrl+", (gen_bsoctr, 0x200001)),
+        ("mftb", (gen_mftb, 0x0)),
+        ("fmadds", (gen_fmadds, 0x0)),
+        ("fmsub.", (gen_fmsub, 0x1)),
+        ("bgtctr+", (gen_bgtctr, 0x200000)),
+        ("bla", (gen_b, 0x3)),
+        ("bsoctr", (gen_bsoctr, 0x0)),
+        ("bdzfa+", (gen_bdzf, 0x200002)),
+        ("bdzflr", (gen_bdzflr, 0x0)),
+        ("stfdux", (gen_stfdux, 0x0)),
+        ("subfmeo.", (gen_subfme, 0x401)),
+        ("bgela", (gen_bge, 0x3)),
+        ("bgel", (gen_bge, 0x1)),
+        ("mulli", (gen_mulli, 0x0)),
+        ("bgtlr", (gen_bgtlr, 0x0)),
+        ("vupklsb", (gen_vupklsb, 0x0)),
+        ("vrlw", (gen_vrlw, 0x0)),
+        ("fmadds.", (gen_fmadds, 0x1)),
+        ("vslb", (gen_vslb, 0x0)),
+        ("fdivs.", (gen_fdivs, 0x1)),
+        ("bltctrl", (gen_bltctr, 0x1)),
+        ("mullw.", (gen_mullw, 0x1)),
+        ("bdnzfla+", (gen_bdnzf, 0x200003)),
+        ("nego.", (gen_neg, 0x401)),
+        ("vand", (gen_vand, 0x0)),
+        ("vminsh", (gen_vminsh, 0x0)),
+        ("mfdbatl", (gen_mfdbatl, 0x0)),
+        ("mfsrr1", (gen_mfsrr1, 0x0)),
+        ("subfzeo", (gen_subfze, 0x400)),
+        ("bgta+", (gen_bgt, 0x200002)),
+        ("vcmpgefp128", (gen_vcmpgefp128, 0x0)),
+        ("bdzf-", (gen_bdzf, 0x200000)),
+        ("fadd.", (gen_fadd, 0x1)),
+        ("vspltb", (gen_vspltb, 0x0)),
+        ("rlwinm", (gen_rlwinm, 0x0)),
+        ("fmsubs", (gen_fmsubs, 0x0)),
+        ("beq", (gen_beq, 0x0)),
+        ("bdnztlrl+", (gen_bdnztlr, 0x200001)),
+        ("vnor", (gen_vnor, 0x0)),
+        ("bdnzfla", (gen_bdnzf, 0x3)),
+        ("add", (gen_add, 0x0)),
+        ("ldx", (gen_ldx, 0x0)),
+        ("andc.", (gen_andc, 0x1)),
+        ("subfc.", (gen_subfc, 0x1)),
+        ("mulldo.", (gen_mulld, 0x401)),
+        ("mfxer", (gen_mfxer, 0x0)),
+        ("lbz", (gen_lbz, 0x0)),
+        ("fabs.", (gen_fabs, 0x1)),
+        ("vspltisw128", (gen_vspltisw128, 0x0)),
+        ("and", (gen_and, 0x0)),
+        ("vmaxsw", (gen_vmaxsw, 0x0)),
+        ("bnela-", (gen_bne, 0x200003)),
+        ("bsol", (gen_bso, 0x1)),
+        ("rldicr", (gen_rldicr, 0x0)),
+        ("clrlwi.", (gen_clrlwi, 0x1)),
+        ("srwi", (gen_srwi, 0x0)),
+        ("vpkuhus128", (gen_vpkuhus128, 0x0)),
+        ("bdnzlr", (gen_bdnzlr, 0x0)),
+        ("fabs", (gen_fabs, 0x0)),
+        ("rotlwi.", (gen_rotlwi, 0x1)),
+        ("vsplth", (gen_vsplth, 0x0)),
+        ("vminsb", (gen_vminsb, 0x0)),
+        ("crset", (gen_crset, 0x0)),
+        ("bclr", (gen_bclr, 0x0)),
+        ("bdztl-", (gen_bdzt, 0x200001)),
+        ("fmadd", (gen_fmadd, 0x0)),
+        ("twi", (gen_twi, 0x0)),
+        ("vexptefp", (gen_vexptefp, 0x0)),
+        ("vpkuwum128", (gen_vpkuwum128, 0x0)),
+        ("slwi", (gen_slwi, 0x0)),
+        ("lvrxl128", (gen_lvrxl128, 0x0)),
+        ("vmrglh", (gen_vmrglh, 0x0)),
+        ("vpkshss", (gen_vpkshss, 0x0)),
+        ("cmpldi", (gen_cmpldi, 0x0)),
+        ("bltctrl+", (gen_bltctr, 0x200001)),
+        ("vupklsh", (gen_vupklsh, 0x0)),
+        ("vcmpbfp128", (gen_vcmpbfp128, 0x0)),
+        ("ld", (gen_ld, 0x0)),
+        ("ble-", (gen_ble, 0x200000)),
+        ("bsol+", (gen_bso, 0x200001)),
+        ("oris", (gen_oris, 0x0)),
+        ("rldcr", (gen_rldcr, 0x0)),
+        ("crclr", (gen_crclr, 0x0)),
+        ("twui", (gen_twui, 0x0)),
+        ("vandc", (gen_vandc, 0x0)),
+        ("bsolr+", (gen_bsolr, 0x200000)),
+        ("stfsux", (gen_stfsux, 0x0)),
+        ("bnsctrl+", (gen_bnsctr, 0x200001)),
+        ("fres", (gen_fres, 0x0)),
+        ("lbzux", (gen_lbzux, 0x0)),
+        ("or", (gen_or, 0x0)),
+        ("crandc", (gen_crandc, 0x0)),
+        ("bca+", (gen_bc, 0x200002)),
+        ("bgtlr+", (gen_bgtlr, 0x200000)),
+        ("dstst", (gen_dstst, 0x0)),
+        ("stwu", (gen_stwu, 0x0)),
+        ("bdnztlrl", (gen_bdnztlr, 0x1)),
+        ("bdnzflr", (gen_bdnzflr, 0x0)),
+        ("addme.", (gen_addme, 0x1)),
+        ("li", (gen_li, 0x0)),
+        ("vavgsw", (gen_vavgsw, 0x0)),
+        ("fnmadd.", (gen_fnmadd, 0x1)),
+        ("fcfid", (gen_fcfid, 0x0)),
+        ("vpkuhum128", (gen_vpkuhum128, 0x0)),
+        ("bgectr+", (gen_bgectr, 0x200000)),
+        ("vslo", (gen_vslo, 0x0)),
+        ("bdzfla", (gen_bdzf, 0x3)),
+        ("dcbtst", (gen_dcbtst, 0x0)),
+        ("rldic", (gen_rldic, 0x0)),
+        ("vpkshss128", (gen_vpkshss128, 0x0)),
+        ("bcctr", (gen_bcctr, 0x0)),
+        ("vsrw128", (gen_vsrw128, 0x0)),
+        ("lwbrx", (gen_lwbrx, 0x0)),
+        ("vlogefp128", (gen_vlogefp128, 0x0)),
+        ("divwuo", (gen_divwu, 0x400)),
+        ("bltl-", (gen_blt, 0x200001)),
+        ("clrrwi", (gen_clrrwi, 0x0)),
+        ("blelrl+", (gen_blelr, 0x200001)),
+        ("stdx", (gen_stdx, 0x0)),
+        ("vrefp", (gen_vrefp, 0x0)),
+        ("or.", (gen_or, 0x1)),
+        ("extsw", (gen_extsw, 0x0)),
+        ("mfspr", (gen_mfspr, 0x0)),
+        ("fcfid.", (gen_fcfid, 0x1)),
+        ("vmaddfp", (gen_vmaddfp, 0x0)),
+        ("mfvscr", (gen_mfvscr, 0x0)),
+        ("srd", (gen_srd, 0x0)),
+        ("vmladduhm", (gen_vmladduhm, 0x0)),
+        ("vmsum3fp128", (gen_vmsum3fp128, 0x0)),
+        ("vcmpgtsw", (gen_vcmpgtsw, 0x0)),
+        ("rldicr.", (gen_rldicr, 0x1)),
+        ("vcmpgtsb", (gen_vcmpgtsb, 0x0)),
+        ("bdnztlr", (gen_bdnztlr, 0x0)),
+        ("subfo", (gen_subf, 0x400)),
+        ("nor.", (gen_nor, 0x1)),
+        ("vsro128", (gen_vsro128, 0x0)),
+        ("vminub", (gen_vminub, 0x0)),
+        ("bdnzfa+", (gen_bdnzf, 0x200002)),
+        ("sld.", (gen_sld, 0x1)),
+        ("vpermwi128", (gen_vpermwi128, 0x0)),
+        ("vrfip128", (gen_vrfip128, 0x0)),
+        ("bgela+", (gen_bge, 0x200003)),
+        ("lhzux", (gen_lhzux, 0x0)),
+        ("beqlrl", (gen_beqlr, 0x1)),
+        ("mtdsisr", (gen_mtdsisr, 0x0)),
+        ("mfsprg", (gen_mfsprg, 0x0)),
+        ("subfzeo.", (gen_subfze, 0x401)),
+        ("fnmsubs", (gen_fnmsubs, 0x0)),
+        ("bgel+", (gen_bge, 0x200001)),
+        ("lfdu", (gen_lfdu, 0x0)),
+        ("bdnzf", (gen_bdnzf, 0x0)),
+        ("bgectrl+", (gen_bgectr, 0x200001)),
+        ("vmaxfp", (gen_vmaxfp, 0x0)),
+        ("vrfin", (gen_vrfin, 0x0)),
+        ("slbia", (gen_slbia, 0x0)),
+        ("bdza-", (gen_bdz, 0x200002)),
+        ("lwa", (gen_lwa, 0x0)),
+        ("blectr", (gen_blectr, 0x0)),
+        ("bsoctr+", (gen_bsoctr, 0x200000)),
+        ("lfsx", (gen_lfsx, 0x0)),
+        ("tdi", (gen_tdi, 0x0)),
+        ("twlge", (gen_twlge, 0x0)),
+        ("bdnzlrl+", (gen_bdnzlr, 0x200001)),
+        ("fadds.", (gen_fadds, 0x1)),
+        ("sthu", (gen_sthu, 0x0)),
+        ("mfctr", (gen_mfctr, 0x0)),
+        ("subfeo.", (gen_subfe, 0x401)),
+        ("bdnzl+", (gen_bdnz, 0x200001)),
+        ("vpkswss128", (gen_vpkswss128, 0x0)),
+        ("stwx", (gen_stwx, 0x0)),
+        ("vavgsb", (gen_vavgsb, 0x0)),
+        ("bcl-", (gen_bc, 0x200001)),
+        ("rfid", (gen_rfid, 0x0)),
+        ("lvlx128", (gen_lvlx128, 0x0)),
+        ("rfi", (gen_rfi, 0x0)),
+        ("vpkshus128", (gen_vpkshus128, 0x0)),
+        ("bns+", (gen_bns, 0x200000)),
+        ("bdztla+", (gen_bdzt, 0x200003)),
+        ("stfiwx", (gen_stfiwx, 0x0)),
+        ("mulhd.", (gen_mulhd, 0x1)),
+        ("sld", (gen_sld, 0x0)),
+        ("vpkswus", (gen_vpkswus, 0x0)),
+        ("vsum4sbs", (gen_vsum4sbs, 0x0)),
+        ("vmaddcfp128", (gen_vmaddcfp128, 0x0)),
+        ("bdzf", (gen_bdzf, 0x0)),
+        ("vxor128", (gen_vxor128, 0x0)),
+        ("addco", (gen_addc, 0x400)),
+        ("blectrl", (gen_blectr, 0x1)),
+        ("vsrab", (gen_vsrab, 0x0)),
+        ("bdzfl", (gen_bdzf, 0x1)),
+        ("blelr+", (gen_blelr, 0x200000)),
+        ("ecowx", (gen_ecowx, 0x0)),
+        ("lvxl", (gen_lvxl, 0x0)),
+        ("vaddsws", (gen_vaddsws, 0x0)),
+        ("bdztl", (gen_bdzt, 0x1)),
+        ("bdnzfa", (gen_bdnzf, 0x2)),
+        ("mtsrr1", (gen_mtsrr1, 0x0)),
+        ("dststt", (gen_dstst, 0x2000000)),
+        ("bgtctrl+", (gen_bgtctr, 0x200001)),
+        ("fmul.", (gen_fmul, 0x1)),
+        ("vand128", (gen_vand128, 0x0)),
+        ("subfo.", (gen_subf, 0x401)),
+        ("mfsdr1", (gen_mfsdr1, 0x0)),
+        ("bdnzlrl", (gen_bdnzlr, 0x1)),
+        ("addeo.", (gen_adde, 0x401)),
+        ("bdzl", (gen_bdz, 0x1)),
+        ("fneg", (gen_fneg, 0x0)),
+        ("vmulosh", (gen_vmulosh, 0x0)),
+        ("fnmsub", (gen_fnmsub, 0x0)),
+        ("bdnzta", (gen_bdnzt, 0x2)),
+        ("vmrghb", (gen_vmrghb, 0x0)),
+        ("divduo.", (gen_divdu, 0x401)),
+        ("ptesync", (gen_ptesync, 0x0)),
+        ("mtdbatu", (gen_mtdbatu, 0x0)),
+        ("fnmadds", (gen_fnmadds, 0x0)),
+        ("subfme.", (gen_subfme, 0x1)),
+        ("vpkswus128", (gen_vpkswus128, 0x0)),
+        ("bgela-", (gen_bge, 0x200003)),
+        ("vnor128", (gen_vnor128, 0x0)),
+        ("orc.", (gen_orc, 0x1)),
+        ("beqlr+", (gen_beqlr, 0x200000)),
+        ("bso", (gen_bso, 0x0)),
+        ("crnor", (gen_crnor, 0x0)),
+        ("bcla+", (gen_bc, 0x200003)),
+        ("mtsdr1", (gen_mtsdr1, 0x0)),
+        ("vmhaddshs", (gen_vmhaddshs, 0x0)),
+        ("vspltw128", (gen_vspltw128, 0x0)),
+        ("lvlx", (gen_lvlx, 0x0)),
+        ("lvewx", (gen_lvewx, 0x0)),
+        ("vnmsubfp", (gen_vnmsubfp, 0x0)),
+        ("vupkhsb", (gen_vupkhsb, 0x0)),
+        ("rotlwi", (gen_rotlwi, 0x0)),
+        ("bdzl+", (gen_bdz, 0x200001)),
+        ("bdnzlr+", (gen_bdnzlr, 0x200000)),
+        ("stvxl", (gen_stvxl, 0x0)),
+        ("vexptefp128", (gen_vexptefp128, 0x0)),
+        ("mtdec", (gen_mtdec, 0x0)),
+        ("vmhraddshs", (gen_vmhraddshs, 0x0)),
+        ("mffs.", (gen_mffs, 0x1)),
+        ("lvlxl128", (gen_lvlxl128, 0x0)),
+        ("vupkhsb128", (gen_vupkhsb128, 0x0)),
+        ("rotld", (gen_rotld, 0x0)),
+        ("mulhw.", (gen_mulhw, 0x1)),
+        ("slwi.", (gen_slwi, 0x1)),
+        ("bgelrl", (gen_bgelr, 0x1)),
+        ("fctiwz.", (gen_fctiwz, 0x1)),
+        ("vsr", (gen_vsr, 0x0)),
+        ("bgtctrl", (gen_bgtctr, 0x1)),
+        ("bdnztl+", (gen_bdnzt, 0x200001)),
+        ("blectrl+", (gen_blectr, 0x200001)),
+        ("rldimi.", (gen_rldimi, 0x1)),
+        ("slw.", (gen_slw, 0x1)),
+        ("bdztl+", (gen_bdzt, 0x200001)),
+        ("tdnei", (gen_tdnei, 0x0)),
+        ("vcmpequw128.", (gen_vcmpequw128, 0x40)),
+        ("bdnzta+", (gen_bdnzt, 0x200002)),
+        ("fmr", (gen_fmr, 0x0)),
+        ("bdzflrl+", (gen_bdzflr, 0x200001)),
+        ("bdnztla-", (gen_bdnzt, 0x200003)),
+        ("bdnzfla-", (gen_bdnzf, 0x200003)),
+        ("vsububm", (gen_vsububm, 0x0)),
+        ("vcmpequw", (gen_vcmpequw, 0x0)),
+        ("vrlimi128", (gen_vrlimi128, 0x0)),
+        ("bge-", (gen_bge, 0x200000)),
+        ("vcmpgtsh", (gen_vcmpgtsh, 0x0)),
+        ("blel", (gen_ble, 0x1)),
+        ("bgectrl", (gen_bgectr, 0x1)),
+        ("addze.", (gen_addze, 0x1)),
+        ("mtibatl", (gen_mtibatl, 0x0)),
+        ("sth", (gen_sth, 0x0)),
+        ("vmaxsh", (gen_vmaxsh, 0x0)),
+        ("bdnztl-", (gen_bdnzt, 0x200001)),
+        ("mtfsf", (gen_mtfsf, 0x0)),
+        ("bdzfla-", (gen_bdzf, 0x200003)),
+        ("ldux", (gen_ldux, 0x0)),
+        ("beqa", (gen_beq, 0x2)),
+        ("dstt", (gen_dst, 0x2000000)),
+        ("lvrx", (gen_lvrx, 0x0)),
+        ("vslo128", (gen_vslo128, 0x0)),
+        ("lwzux", (gen_lwzux, 0x0)),
+        ("ble", (gen_ble, 0x0)),
+        ("lha", (gen_lha, 0x0)),
+        ("vupklpx", (gen_vupklpx, 0x0)),
+        ("vspltisb", (gen_vspltisb, 0x0)),
+        ("bgtctr", (gen_bgtctr, 0x0)),
+        ("bltla+", (gen_blt, 0x200003)),
+        ("bgel-", (gen_bge, 0x200001)),
+        ("vsubfp", (gen_vsubfp, 0x0)),
+        ("fadds", (gen_fadds, 0x0)),
+        ("vupkhsh", (gen_vupkhsh, 0x0)),
+        ("fsel", (gen_fsel, 0x0)),
+        ("vavguh", (gen_vavguh, 0x0)),
+        ("bsol-", (gen_bso, 0x200001)),
+        ("mtmsrd", (gen_mtmsrd, 0x0)),
+        ("fdivs", (gen_fdivs, 0x0)),
+        ("bdztla-", (gen_bdzt, 0x200003)),
+        ("vmsumuhs", (gen_vmsumuhs, 0x0)),
+        ("vsubshs", (gen_vsubshs, 0x0)),
+        ("vmulosb", (gen_vmulosb, 0x0)),
+        ("vavgub", (gen_vavgub, 0x0)),
+        ("subfc", (gen_subfc, 0x0)),
+        ("mtsrd", (gen_mtsrd, 0x0)),
+        ("vaddcuw", (gen_vaddcuw, 0x0)),
+        ("beqlrl+", (gen_beqlr, 0x200001)),
+        ("vcmpequw.", (gen_vcmpequw, 0x400)),
+        ("blela+", (gen_ble, 0x200003)),
+        ("mtfsf.", (gen_mtfsf, 0x1)),
+        ("bgtla", (gen_bgt, 0x3)),
+        ("dssall", (gen_dssall, 0x0)),
+        ("stswi", (gen_stswi, 0x0)),
+        ("extsh", (gen_extsh, 0x0)),
+        ("subfic", (gen_subfic, 0x0)),
+        ("bnectrl", (gen_bnectr, 0x1)),
+        ("vcmpgtuh", (gen_vcmpgtuh, 0x0)),
+        ("blrl", (gen_blr, 0x1)),
+        ("vsubfp128", (gen_vsubfp128, 0x0)),
+        ("bnslr+", (gen_bnslr, 0x200000)),
+        ("vsubuws", (gen_vsubuws, 0x0)),
+        ("beqctr", (gen_beqctr, 0x0)),
+        ("bgtl", (gen_bgt, 0x1)),
+        ("vcmpgtfp128.", (gen_vcmpgtfp128, 0x40)),
+        ("rlwinm.", (gen_rlwinm, 0x1)),
+        ("subfe", (gen_subfe, 0x0)),
+        ("mulldo", (gen_mulld, 0x400)),
+        ("mttbu", (gen_mttbu, 0x0)),
+        ("vcmpgefp128.", (gen_vcmpgefp128, 0x40)),
+        ("bne-", (gen_bne, 0x200000)),
+        ("bgta-", (gen_bgt, 0x200002)),
+        ("lvrx128", (gen_lvrx128, 0x0)),
+        ("lvebx", (gen_lvebx, 0x0)),
+        ("vupkd3d128", (gen_vupkd3d128, 0x0)),
+        ("rldcl", (gen_rldcl, 0x0)),
+        ("blectr+", (gen_blectr, 0x200000)),
+        ("blea-", (gen_ble, 0x200002)),
+        ("add.", (gen_add, 0x1)),
+        ("mulhdu", (gen_mulhdu, 0x0)),
+        ("bctr", (gen_bctr, 0x0)),
+        ("fres.", (gen_fres, 0x1)),
+        ("stvrx128", (gen_stvrx128, 0x0)),
+        ("vavguw", (gen_vavguw, 0x0)),
+        ("frsp.", (gen_frsp, 0x1)),
+        ("lwarx", (gen_lwarx, 0x0)),
+        ("vrfin128", (gen_vrfin128, 0x0)),
+        ("vmr", (gen_vmr, 0x0)),
+        ("mfcr", (gen_mfcr, 0x0)),
+        ("vsrh", (gen_vsrh, 0x0)),
+        ("bdnztl", (gen_bdnzt, 0x1)),
+        ("cntlzd.", (gen_cntlzd, 0x1)),
+        ("vslw", (gen_vslw, 0x0)),
+        ("vpkd3d128", (gen_vpkd3d128, 0x0)),
+        ("subic", (gen_subic, 0x0)),
+        ("vor", (gen_vor, 0x0)),
+        ("lbzu", (gen_lbzu, 0x0)),
+        ("bnea", (gen_bne, 0x2)),
+        ("ble+", (gen_ble, 0x200000)),
+        ("bdnza+", (gen_bdnz, 0x200002)),
+        ("vcmpgtuw", (gen_vcmpgtuw, 0x0)),
+        ("tweq", (gen_tweq, 0x0)),
+        ("creqv", (gen_creqv, 0x0)),
+        ("bdzf+", (gen_bdzf, 0x200000)),
+        ("mulhd", (gen_mulhd, 0x0)),
+        ("bgea+", (gen_bge, 0x200002)),
+        ("bcl", (gen_bc, 0x1)),
+        ("bdzfa-", (gen_bdzf, 0x200002)),
+        ("vsldoi128", (gen_vsldoi128, 0x0)),
+        ("blt+", (gen_blt, 0x200000)),
+        ("addo", (gen_add, 0x400)),
+        ("bsolr", (gen_bsolr, 0x0)),
+        ("vsldoi", (gen_vsldoi, 0x0)),
+        ("vcmpeqfp", (gen_vcmpeqfp, 0x0)),
+        ("clrlwi", (gen_clrlwi, 0x0)),
+        ("bdzla-", (gen_bdz, 0x200003)),
+        ("bdzta-", (gen_bdzt, 0x200002)),
+        ("extsw.", (gen_extsw, 0x1)),
+        ("extrwi", (gen_extrwi, 0x0)),
+        ("stvlx", (gen_stvlx, 0x0)),
+        ("cmpl", (gen_cmpl, 0x0)),
+        ("crorc", (gen_crorc, 0x0)),
+        ("mtsr", (gen_mtsr, 0x0)),
+        ("bsolrl", (gen_bsolr, 0x1)),
+        ("fsub", (gen_fsub, 0x0)),
+        ("stvewx", (gen_stvewx, 0x0)),
+        ("bdnzf-", (gen_bdnzf, 0x200000)),
+        ("divwo", (gen_divw, 0x400)),
+        ("bnelrl", (gen_bnelr, 0x1)),
+        ("bcla-", (gen_bc, 0x200003)),
+        ("rotlw", (gen_rotlw, 0x0)),
+        ("bdzt-", (gen_bdzt, 0x200000)),
+        ("bdz", (gen_bdz, 0x0)),
+        ("lbzx", (gen_lbzx, 0x0)),
+        ("bc+", (gen_bc, 0x200000)),
+        ("mtfsb0.", (gen_mtfsb0, 0x1)),
+        ("bns-", (gen_bns, 0x200000)),
+        ("vsubsbs", (gen_vsubsbs, 0x0)),
+        ("bnsa-", (gen_bns, 0x200002)),
+        ("bctrl", (gen_bctr, 0x1)),
+        ("crxor", (gen_crxor, 0x0)),
+        ("subfmeo", (gen_subfme, 0x400)),
+        ("blea", (gen_ble, 0x2)),
+        ("sync", (gen_sync, 0x0)),
+        ("icbi", (gen_icbi, 0x0)),
+        ("vcmpeqfp128.", (gen_vcmpeqfp128, 0x40)),
+        ("blela", (gen_ble, 0x3)),
+        ("bclrl", (gen_bclr, 0x1)),
+        ("bcctrl+", (gen_bcctr, 0x200001)),
+        ("lwzx", (gen_lwzx, 0x0)),
+        ("rotrwi.", (gen_rotrwi, 0x1)),
+        ("bnsl", (gen_bns, 0x1)),
+        ("mulhw", (gen_mulhw, 0x0)),
+        ("bnectrl+", (gen_bnectr, 0x200001)),
+        ("bnsctr+", (gen_bnsctr, 0x200000)),
+        ("vspltish", (gen_vspltish, 0x0)),
+        ("vctuxs", (gen_vctuxs, 0x0)),
+        ("rotld.", (gen_rotld, 0x1)),
+        ("cror", (gen_cror, 0x0)),
+        ("fsub.", (gen_fsub, 0x1)),
+        ("bdzflrl", (gen_bdzflr, 0x1)),
+        ("bdnzfl-", (gen_bdnzf, 0x200001)),
+        ("addmeo.", (gen_addme, 0x401)),
+        ("srw.", (gen_srw, 0x1)),
+        ("mcrxr", (gen_mcrxr, 0x0)),
+        ("bgtl-", (gen_bgt, 0x200001)),
+        ("beqla", (gen_beq, 0x3)),
+        ("vmulfp128", (gen_vmulfp128, 0x0)),
+        ("vcmpequb.", (gen_vcmpequb, 0x400)),
+        ("rotlw.", (gen_rotlw, 0x1)),
+        ("cmplw", (gen_cmplw, 0x0)),
+        ("clrlslwi.", (gen_clrlslwi, 0x1)),
+        ("lhau", (gen_lhau, 0x0)),
+        ("mtfsb1.", (gen_mtfsb1, 0x1)),
+        ("vcmpgtsh.", (gen_vcmpgtsh, 0x400)),
+        ("blr", (gen_blr, 0x0)),
+        ("fsel.", (gen_fsel, 0x1)),
+        ("vcmpgtsw.", (gen_vcmpgtsw, 0x400)),
+        ("bdnzfl+", (gen_bdnzf, 0x200001)),
+        ("bnsctrl", (gen_bnsctr, 0x1)),
+        ("adde", (gen_adde, 0x0)),
+        ("blta+", (gen_blt, 0x200002)),
+        ("bgea", (gen_bge, 0x2)),
+        ("bnela+", (gen_bne, 0x200003)),
+        ("bsolrl+", (gen_bsolr, 0x200001)),
+        ("bl", (gen_b, 0x1)),
+        ("cmpw", (gen_cmpw, 0x0)),
+        ("extsb.", (gen_extsb, 0x1)),
+        ("mulld.", (gen_mulld, 0x1)),
+        ("bltlrl", (gen_bltlr, 0x1)),
+        ("bcctrl", (gen_bcctr, 0x1)),
+        ("vadduws", (gen_vadduws, 0x0)),
+        ("mfdbatu", (gen_mfdbatu, 0x0)),
+        ("rlwnm.", (gen_rlwnm, 0x1)),
+        ("mtctr", (gen_mtctr, 0x0)),
+        ("mtlr", (gen_mtlr, 0x0)),
+        ("vslh", (gen_vslh, 0x0)),
+        ("bnela", (gen_bne, 0x3)),
+        ("bdnzfl", (gen_bdnzf, 0x1)),
+        ("vsrb", (gen_vsrb, 0x0)),
+        ("lwax", (gen_lwax, 0x0)),
+        ("isync", (gen_isync, 0x0)),
+        ("bdzla", (gen_bdz, 0x3)),
+        ("vslw128", (gen_vslw128, 0x0)),
+        ("dst", (gen_dst, 0x0)),
+        ("vmrghw", (gen_vmrghw, 0x0)),
+        ("rldcl.", (gen_rldcl, 0x1)),
+        ("vctsxs", (gen_vctsxs, 0x0)),
+        ("mtfsfi.", (gen_mtfsfi, 0x1)),
+        ("vmsumubm", (gen_vmsumubm, 0x0)),
+        ("blta", (gen_blt, 0x2)),
+        ("mullw", (gen_mullw, 0x0)),
+        ("crand", (gen_crand, 0x0)),
+        ("bnsl+", (gen_bns, 0x200001)),
+        ("twgti", (gen_twgti, 0x0)),
+        ("ldu", (gen_ldu, 0x0)),
+        ("bdzl-", (gen_bdz, 0x200001)),
+        ("beqla-", (gen_beq, 0x200003)),
+        ("mulhwu", (gen_mulhwu, 0x0)),
+        ("bcla", (gen_bc, 0x3)),
+        ("bdzflr+", (gen_bdzflr, 0x200000)),
+        ("bclrl+", (gen_bclr, 0x200001)),
+        ("fnabs", (gen_fnabs, 0x0)),
+        ("cmpli", (gen_cmpli, 0x0)),
+        ("vminfp", (gen_vminfp, 0x0)),
+        ("divw", (gen_divw, 0x0)),
+        ("beqctrl+", (gen_beqctr, 0x200001)),
+        ("divd", (gen_divd, 0x0)),
+        ("extsh.", (gen_extsh, 0x1)),
+        ("sthx", (gen_sthx, 0x0)),
+        ("lwz", (gen_lwz, 0x0)),
+        ("vcfux", (gen_vcfux, 0x0)),
+        ("mtspr", (gen_mtspr, 0x0)),
+        ("vsum4shs", (gen_vsum4shs, 0x0)),
+        ("extlwi", (gen_extlwi, 0x0)),
+        ("bdnzla", (gen_bdnz, 0x3)),
+        ("vcmpgefp", (gen_vcmpgefp, 0x0)),
+        ("fsubs.", (gen_fsubs, 0x1)),
+        ("lvlxl", (gen_lvlxl, 0x0)),
+        ("bdztlr+", (gen_bdztlr, 0x200000)),
+        ("vmrglw", (gen_vmrglw, 0x0)),
+        ("srad.", (gen_srad, 0x1)),
+        ("addco.", (gen_addc, 0x401)),
+        ("nor", (gen_nor, 0x0)),
+        ("beqlr", (gen_beqlr, 0x0)),
+        ("vspltw", (gen_vspltw, 0x0)),
+        ("neg.", (gen_neg, 0x1)),
+        ("tdge", (gen_tdge, 0x0)),
+        ("vmrghh", (gen_vmrghh, 0x0)),
+        ("mtear", (gen_mtear, 0x0)),
+        ("fmul", (gen_fmul, 0x0)),
+        ("bnea+", (gen_bne, 0x200002)),
+        ("lvrxl", (gen_lvrxl, 0x0)),
+        ("bdnztla+", (gen_bdnzt, 0x200003)),
+        ("bdzfa", (gen_bdzf, 0x2)),
+        ("lvsl", (gen_lvsl, 0x0)),
+        ("extlwi.", (gen_extlwi, 0x1)),
+        ("twllei", (gen_twllei, 0x0)),
+        ("bdztlrl+", (gen_bdztlr, 0x200001)),
+        ("lvsr", (gen_lvsr, 0x0)),
+        ("bdnzflr+", (gen_bdnzflr, 0x200000)),
+        ("vsum2sws", (gen_vsum2sws, 0x0)),
         ("divdo", (gen_divd, 0x400)),
+        ("stdu", (gen_stdu, 0x0)),
+        ("vmsumuhm", (gen_vmsumuhm, 0x0)),
+        ("beq+", (gen_beq, 0x200000)),
+        ("bltctr", (gen_bltctr, 0x0)),
+        ("fctiw.", (gen_fctiw, 0x1)),
+        ("beqctrl", (gen_beqctr, 0x1)),
+        ("stw", (gen_stw, 0x0)),
+        ("addic.", (gen_addic_, 0x0)),
+        ("bltl+", (gen_blt, 0x200001)),
+        ("blt", (gen_blt, 0x0)),
+        ("bdztlrl", (gen_bdztlr, 0x1)),
+        ("lhzx", (gen_lhzx, 0x0)),
+        ("vcfpuxws128", (gen_vcfpuxws128, 0x0)),
+        ("dcbz", (gen_dcbz, 0x0)),
+        ("vsrw", (gen_vsrw, 0x0)),
+        ("divwu", (gen_divwu, 0x0)),
+        ("lfdux", (gen_lfdux, 0x0)),
+        ("bnel-", (gen_bne, 0x200001)),
+        ("mtmsr", (gen_mtmsr, 0x0)),
+        ("vupkhpx", (gen_vupkhpx, 0x0)),
+        ("vcmpbfp128.", (gen_vcmpbfp128, 0x40)),
+        ("subi", (gen_subi, 0x0)),
+        ("vcmpbfp.", (gen_vcmpbfp, 0x400)),
+        ("mr", (gen_mr, 0x0)),
+        ("subfze.", (gen_subfze, 0x1)),
+        ("sc", (gen_sc, 0x0)),
+        ("bdnzt+", (gen_bdnzt, 0x200000)),
+        ("vmrghw128", (gen_vmrghw128, 0x0)),
+        ("mttbl", (gen_mttbl, 0x0)),
+        ("vcmpgtfp128", (gen_vcmpgtfp128, 0x0)),
+        ("fneg.", (gen_fneg, 0x1)),
+        ("vmuloub", (gen_vmuloub, 0x0)),
+        ("vaddubm", (gen_vaddubm, 0x0)),
+        ("mullwo.", (gen_mullw, 0x401)),
+        ("stfsu", (gen_stfsu, 0x0)),
+        ("nand", (gen_nand, 0x0)),
+        ("vsubuwm", (gen_vsubuwm, 0x0)),
+        ("stvebx", (gen_stvebx, 0x0)),
+        ("extrwi.", (gen_extrwi, 0x1)),
+        ("vpkpx", (gen_vpkpx, 0x0)),
+        ("addme", (gen_addme, 0x0)),
+        ("vcmpequh.", (gen_vcmpequh, 0x400)),
+        ("vmaxsb", (gen_vmaxsb, 0x0)),
+        ("mtfsb1", (gen_mtfsb1, 0x0)),
+        ("bnslrl", (gen_bnslr, 0x1)),
+        ("cmpdi", (gen_cmpdi, 0x0)),
+        ("b", (gen_b, 0x0)),
+        ("bdzla+", (gen_bdz, 0x200003)),
+        ("lvsl128", (gen_lvsl128, 0x0)),
+        ("vmaddfp128", (gen_vmaddfp128, 0x0)),
+        ("subfme", (gen_subfme, 0x0)),
+        ("subic.", (gen_subic_, 0x0)),
+        ("bdzlrl", (gen_bdzlr, 0x1)),
+        ("vaddshs", (gen_vaddshs, 0x0)),
+        ("nop", (gen_nop, 0x0)),
+        ("blel+", (gen_ble, 0x200001)),
+        ("srad", (gen_srad, 0x0)),
+        ("vsel", (gen_vsel, 0x0)),
+        ("vpkshus", (gen_vpkshus, 0x0)),
+        ("vmaxfp128", (gen_vmaxfp128, 0x0)),
+        ("beql-", (gen_beq, 0x200001)),
+        ("mtvscr", (gen_mtvscr, 0x0)),
+        ("adde.", (gen_adde, 0x1)),
+        ("stwux", (gen_stwux, 0x0)),
+        ("vmuleuh", (gen_vmuleuh, 0x0)),
+        ("fmuls", (gen_fmuls, 0x0)),
+        ("tdlti", (gen_tdlti, 0x0)),
+        ("crmove", (gen_crmove, 0x0)),
+        ("lvewx128", (gen_lvewx128, 0x0)),
+        ("cntlzd", (gen_cntlzd, 0x0)),
+        ("stfdu", (gen_stfdu, 0x0)),
+        ("fmuls.", (gen_fmuls, 0x1)),
+        ("lhaux", (gen_lhaux, 0x0)),
+        ("addo.", (gen_add, 0x401)),
+        ("addze", (gen_addze, 0x0)),
+        ("bltla-", (gen_blt, 0x200003)),
+        ("beqctr+", (gen_beqctr, 0x200000)),
+        ("neg", (gen_neg, 0x0)),
+        ("fnmsub.", (gen_fnmsub, 0x1)),
+        ("lfsux", (gen_lfsux, 0x0)),
+        ("vrfim128", (gen_vrfim128, 0x0)),
+        ("bnsla+", (gen_bns, 0x200003)),
+        ("vmaxuw", (gen_vmaxuw, 0x0)),
+        ("fsubs", (gen_fsubs, 0x0)),
+        ("mtsrin", (gen_mtsrin, 0x0)),
+        ("mfdsisr", (gen_mfdsisr, 0x0)),
+        ("srw", (gen_srw, 0x0)),
+        ("bdzlr+", (gen_bdzlr, 0x200000)),
+        ("vmulesb", (gen_vmulesb, 0x0)),
+        ("fmsub", (gen_fmsub, 0x0)),
+        ("dss", (gen_dss, 0x0)),
+        ("sradi.", (gen_sradi, 0x1)),
+        ("blela-", (gen_ble, 0x200003)),
+        ("rldcr.", (gen_rldcr, 0x1)),
+        ("stmw", (gen_stmw, 0x0)),
+        ("vsro", (gen_vsro, 0x0)),
+        ("fmadd.", (gen_fmadd, 0x1)),
+        ("vadduhm", (gen_vadduhm, 0x0)),
+        ("bgtl+", (gen_bgt, 0x200001)),
+        ("vpkuwus", (gen_vpkuwus, 0x0)),
+        ("stvx128", (gen_stvx128, 0x0)),
+        ("bsola", (gen_bso, 0x3)),
+        ("vmsummbm", (gen_vmsummbm, 0x0)),
+        ("vmulesh", (gen_vmulesh, 0x0)),
+        ("stwbrx", (gen_stwbrx, 0x0)),
+        ("bdnzla-", (gen_bdnz, 0x200003)),
     ],
 };
 pub fn assemble(mnemonic: &str, args: &Arguments) -> Result<u32, ArgumentError> {
diff --git a/disasm/src/generated.rs b/disasm/src/generated.rs
index d80fa53..82c59e1 100644
--- a/disasm/src/generated.rs
+++ b/disasm/src/generated.rs
@@ -36,15 +36,7 @@ static OPCODE_ENTRIES: [(u16, u16); 64] = [
     (254, 255),
     (255, 256),
     (256, 262),
-    (262, 394),
-    (394, 395),
-    (395, 396),
-    (396, 397),
-    (397, 398),
-    (398, 399),
-    (399, 400),
-    (400, 401),
-    (401, 402),
+    (262, 402),
     (402, 403),
     (403, 404),
     (404, 405),
@@ -61,17 +53,25 @@ static OPCODE_ENTRIES: [(u16, u16); 64] = [
     (415, 416),
     (416, 417),
     (417, 418),
+    (418, 419),
+    (419, 420),
+    (420, 421),
+    (421, 422),
+    (422, 423),
+    (423, 424),
+    (424, 425),
+    (425, 426),
     (0, 0),
     (0, 0),
-    (418, 421),
-    (421, 430),
+    (426, 429),
+    (429, 438),
     (0, 0),
     (0, 0),
-    (430, 432),
-    (432, 460),
+    (438, 440),
+    (440, 468),
 ];
 /// The bitmask and pattern for each opcode.
-static OPCODE_PATTERNS: [(u32, u32); 460] = [
+static OPCODE_PATTERNS: [(u32, u32); 468] = [
     (0xfc000000, 0x8000000),
     (0xfc000000, 0xc000000),
     (0xffe007ff, 0x100007ec),
@@ -221,14 +221,14 @@ static OPCODE_PATTERNS: [(u32, u32); 460] = [
     (0xfc0007ff, 0x100004c4),
     (0xfc0007f3, 0x10000083),
     (0xfc0007f3, 0x10000403),
-    (0xfc0007f3, 0x10000443),
     (0xfc0007f3, 0x10000603),
+    (0xfc0007f3, 0x10000443),
     (0xfc0007f3, 0x10000643),
     (0xfc0007f3, 0x10000003),
     (0xfc0007f3, 0x10000043),
     (0xfc0007f3, 0x100000c3),
     (0xfc0007f3, 0x100002c3),
-    (0xfc0007f3, 0x10000303),
+    (0xfc0007f3, 0x10000183),
     (0xfc0007f3, 0x10000503),
     (0xfc0007f3, 0x10000703),
     (0xfc0007f3, 0x10000543),
@@ -238,7 +238,7 @@ static OPCODE_PATTERNS: [(u32, u32); 460] = [
     (0xfc000010, 0x10000010),
     (0xfc0003d0, 0x14000010),
     (0xfc0003d0, 0x14000210),
-    (0xfc0003d0, 0x14000290),
+    (0xfc0003d0, 0x14000250),
     (0xfc0003d0, 0x14000110),
     (0xfc0003d0, 0x140000d0),
     (0xfc0003d0, 0x14000190),
@@ -256,9 +256,9 @@ static OPCODE_PATTERNS: [(u32, u32); 460] = [
     (0xfc0003d0, 0x14000340),
     (0xfc0003d0, 0x14000380),
     (0xfc0003d0, 0x140003c0),
-    (0xfc0003d0, 0x14000050),
     (0xfc0003d0, 0x14000350),
     (0xfc0003d0, 0x14000390),
+    (0xfc0003d0, 0x140003d0),
     (0xfc0003d0, 0x14000050),
     (0xfc0003d0, 0x14000310),
     (0xfc0007f0, 0x18000230),
@@ -284,12 +284,12 @@ static OPCODE_PATTERNS: [(u32, u32); 460] = [
     (0xfc1f07f0, 0x180003b0),
     (0xfc1f07f0, 0x180003f0),
     (0xfc000730, 0x18000710),
+    (0xfc0003d0, 0x18000050),
     (0xfc1f07f0, 0x18000670),
     (0xfc0003d0, 0x180000d0),
     (0xfc0007f0, 0x18000770),
     (0xfc0007f0, 0x18000730),
     (0xfc0003d0, 0x18000150),
-    (0xfc0003d0, 0x180003d0),
     (0xfc0003d0, 0x180001d0),
     (0xfc0007f0, 0x180007f0),
     (0xfc1f07f0, 0x18000380),
@@ -457,6 +457,10 @@ static OPCODE_PATTERNS: [(u32, u32); 460] = [
     (0xfc0007ff, 0x7c00000e),
     (0xfc0007ff, 0x7c00004e),
     (0xfc0007ff, 0x7c00008e),
+    (0xfc0007ff, 0x7c00040e),
+    (0xfc0007ff, 0x7c00060e),
+    (0xfc0007ff, 0x7c00044e),
+    (0xfc0007ff, 0x7c00064e),
     (0xfc0007ff, 0x7c00000c),
     (0xfc0007ff, 0x7c00004c),
     (0xfc0007ff, 0x7c0000ce),
@@ -464,6 +468,10 @@ static OPCODE_PATTERNS: [(u32, u32); 460] = [
     (0xfc0007ff, 0x7c00010e),
     (0xfc0007ff, 0x7c00014e),
     (0xfc0007ff, 0x7c00018e),
+    (0xfc0007ff, 0x7c00050e),
+    (0xfc0007ff, 0x7c00070e),
+    (0xfc0007ff, 0x7c00054e),
+    (0xfc0007ff, 0x7c00074e),
     (0xfc0007ff, 0x7c0001ce),
     (0xfc0007ff, 0x7c0003ce),
     (0xfc000000, 0x80000000),
@@ -534,7 +542,7 @@ static OPCODE_PATTERNS: [(u32, u32); 460] = [
     (0xfc7f0ffe, 0xfc00010c),
 ];
 /// The name of each opcode.
-static OPCODE_NAMES: [&str; 460] = [
+static OPCODE_NAMES: [&str; 468] = [
     "tdi",
     "twi",
     "dcbz_l",
@@ -684,8 +692,8 @@ static OPCODE_NAMES: [&str; 460] = [
     "vxor",
     "lvewx128",
     "lvlx128",
-    "lvrx128",
     "lvlxl128",
+    "lvrx128",
     "lvrxl128",
     "lvsl128",
     "lvsr128",
@@ -719,9 +727,9 @@ static OPCODE_NAMES: [&str; 460] = [
     "vpkuhus128",
     "vpkuwum128",
     "vpkuwus128",
-    "vrlw128",
     "vsel128",
     "vslo128",
+    "vsro128",
     "vsubfp128",
     "vxor128",
     "vcfpsxws128",
@@ -747,12 +755,12 @@ static OPCODE_NAMES: [&str; 460] = [
     "vrfip128",
     "vrfiz128",
     "vrlimi128",
+    "vrlw128",
     "vrsqrtefp128",
     "vslw128",
     "vspltisw128",
     "vspltw128",
     "vsraw128",
-    "vsro128",
     "vsrw128",
     "vupkd3d128",
     "vupkhsb128",
@@ -920,6 +928,10 @@ static OPCODE_NAMES: [&str; 460] = [
     "lvebx",
     "lvehx",
     "lvewx",
+    "lvlx",
+    "lvlxl",
+    "lvrx",
+    "lvrxl",
     "lvsl",
     "lvsr",
     "lvx",
@@ -927,6 +939,10 @@ static OPCODE_NAMES: [&str; 460] = [
     "stvebx",
     "stvehx",
     "stvewx",
+    "stvlx",
+    "stvlxl",
+    "stvrx",
+    "stvrxl",
     "stvx",
     "stvxl",
     "lwz",
@@ -1301,10 +1317,10 @@ pub enum Opcode {
     Lvewx128 = 147,
     /// lvlx128: Load Vector128 Left Indexed
     Lvlx128 = 148,
-    /// lvrx128: Load Vector128 Right Indexed
-    Lvrx128 = 149,
     /// lvlxl128: Load Vector128 Left Indexed LRU
-    Lvlxl128 = 150,
+    Lvlxl128 = 149,
+    /// lvrx128: Load Vector128 Right Indexed
+    Lvrx128 = 150,
     /// lvrxl128: Load Vector128 Right Indexed LRU
     Lvrxl128 = 151,
     /// lvsl128: Load Vector128 for Shift Left
@@ -1371,12 +1387,12 @@ pub enum Opcode {
     Vpkuwum128 = 182,
     /// vpkuwus128: Vector128 Pack Unsigned Word Unsigned Saturate
     Vpkuwus128 = 183,
-    /// vrlw128: Vector128 Rotate Left Word
-    Vrlw128 = 184,
     /// vsel128: Vector128 Select
-    Vsel128 = 185,
+    Vsel128 = 184,
     /// vslo128: Vector128 Shift Left Octet
-    Vslo128 = 186,
+    Vslo128 = 185,
+    /// vsro128: Vector128 Shift Right Octet
+    Vsro128 = 186,
     /// vsubfp128: Vector128 Subtract Floating Point
     Vsubfp128 = 187,
     /// vxor128: Vector128 Logical XOR
@@ -1427,18 +1443,18 @@ pub enum Opcode {
     Vrfiz128 = 210,
     /// vrlimi128: Vector128 Rotate Left Immediate and Mask Insert
     Vrlimi128 = 211,
+    /// vrlw128: Vector128 Rotate Left Word
+    Vrlw128 = 212,
     /// vrsqrtefp128: Vector128 Reciprocal Square Root Estimate Floating Point
-    Vrsqrtefp128 = 212,
+    Vrsqrtefp128 = 213,
     /// vslw128: Vector128 Shift Left Word
-    Vslw128 = 213,
+    Vslw128 = 214,
     /// vspltisw128: Vector128 Splat Immediate Signed Word
-    Vspltisw128 = 214,
+    Vspltisw128 = 215,
     /// vspltw128: Vector128 Splat Word
-    Vspltw128 = 215,
+    Vspltw128 = 216,
     /// vsraw128: Vector128 Shift Right Arithmetic Word
-    Vsraw128 = 216,
-    /// vsro128: Vector128 Shift Right Octet
-    Vsro128 = 217,
+    Vsraw128 = 217,
     /// vsrw128: Vector128 Shift Right Word
     Vsrw128 = 218,
     /// vupkd3d128: Vector128 Unpack D3Dtype
@@ -1773,156 +1789,172 @@ pub enum Opcode {
     Lvehx = 383,
     /// lvewx: Load Vector Element Word Indexed
     Lvewx = 384,
+    /// lvlx: Load Vector Left Indexed
+    Lvlx = 385,
+    /// lvlxl: Load Vector Left Indexed Last
+    Lvlxl = 386,
+    /// lvrx: Load Vector Right Indexed
+    Lvrx = 387,
+    /// lvrxl: Load Vector Right Indexed Last
+    Lvrxl = 388,
     /// lvsl: Load Vector for Shift Left
-    Lvsl = 385,
+    Lvsl = 389,
     /// lvsr: Load Vector for Shift Right
-    Lvsr = 386,
+    Lvsr = 390,
     /// lvx: Load Vector Indexed
-    Lvx = 387,
+    Lvx = 391,
     /// lvxl: Load Vector Indexed LRU
-    Lvxl = 388,
+    Lvxl = 392,
     /// stvebx: Store Vector Element Byte Indexed
-    Stvebx = 389,
+    Stvebx = 393,
     /// stvehx: Store Vector Element Half Word Indexed
-    Stvehx = 390,
+    Stvehx = 394,
     /// stvewx: Store Vector Element Word Indexed
-    Stvewx = 391,
+    Stvewx = 395,
+    /// stvlx: Store Vector Left Indexed
+    Stvlx = 396,
+    /// stvlxl: Store Vector Left Indexed Last
+    Stvlxl = 397,
+    /// stvrx: Store Vector Right Indexed
+    Stvrx = 398,
+    /// stvrxl: Store Vector Right Indexed Last
+    Stvrxl = 399,
     /// stvx: Store Vector Indexed
-    Stvx = 392,
+    Stvx = 400,
     /// stvxl: Store Vector Indexed LRU
-    Stvxl = 393,
+    Stvxl = 401,
     /// lwz: Load Word and Zero
-    Lwz = 394,
+    Lwz = 402,
     /// lwzu: Load Word and Zero with Update
-    Lwzu = 395,
+    Lwzu = 403,
     /// lbz: Load Byte and Zero
-    Lbz = 396,
+    Lbz = 404,
     /// lbzu: Load Byte and Zero with Update
-    Lbzu = 397,
+    Lbzu = 405,
     /// stw: Store Word
-    Stw = 398,
+    Stw = 406,
     /// stwu: Store Word with Update
-    Stwu = 399,
+    Stwu = 407,
     /// stb: Store Byte
-    Stb = 400,
+    Stb = 408,
     /// stbu: Store Byte with Update
-    Stbu = 401,
+    Stbu = 409,
     /// lhz: Load Half Word and Zero
-    Lhz = 402,
+    Lhz = 410,
     /// lhzu: Load Half Word and Zero with Update
-    Lhzu = 403,
+    Lhzu = 411,
     /// lha: Load Half Word Algebraic
-    Lha = 404,
+    Lha = 412,
     /// lhau: Load Half Word Algebraic with Update
-    Lhau = 405,
+    Lhau = 413,
     /// sth: Store Half Word
-    Sth = 406,
+    Sth = 414,
     /// sthu: Store Half Word with Update
-    Sthu = 407,
+    Sthu = 415,
     /// lmw: Load Multiple Word
-    Lmw = 408,
+    Lmw = 416,
     /// stmw: Store Multiple Word
-    Stmw = 409,
+    Stmw = 417,
     /// lfs: Load Floating-Point Single
-    Lfs = 410,
+    Lfs = 418,
     /// lfsu: Load Floating-Point Single with Update
-    Lfsu = 411,
+    Lfsu = 419,
     /// lfd: Load Floating-Point Double
-    Lfd = 412,
+    Lfd = 420,
     /// lfdu: Load Floating-Point Double with Update
-    Lfdu = 413,
+    Lfdu = 421,
     /// stfs: Store Floating-Point Single
-    Stfs = 414,
+    Stfs = 422,
     /// stfsu: Store Floating-Point Single with Update
-    Stfsu = 415,
+    Stfsu = 423,
     /// stfd: Store Floating-Point Double
-    Stfd = 416,
+    Stfd = 424,
     /// stfdu: Store Floating-Point Double with Update
-    Stfdu = 417,
+    Stfdu = 425,
     /// ld: Load Double Word
-    Ld = 418,
+    Ld = 426,
     /// ldu: Load Double Word with Update
-    Ldu = 419,
+    Ldu = 427,
     /// lwa: Load Word Algebraic
-    Lwa = 420,
+    Lwa = 428,
     /// fadds: Floating Add (Single-Precision)
-    Fadds = 421,
+    Fadds = 429,
     /// fdivs: Floating Divide (Single-Precision)
-    Fdivs = 422,
+    Fdivs = 430,
     /// fmadds: Floating Multiply-Add (Single-Precision)
-    Fmadds = 423,
+    Fmadds = 431,
     /// fmsubs: Floating Multiply-Subtract (Single-Precision)
-    Fmsubs = 424,
+    Fmsubs = 432,
     /// fmuls: Floating Multiply (Single-Precision)
-    Fmuls = 425,
+    Fmuls = 433,
     /// fnmadds: Floating Negative Multiply-Add (Single-Precision)
-    Fnmadds = 426,
+    Fnmadds = 434,
     /// fnmsubs: Floating Negative Multiply-Subtract (Single-Precision)
-    Fnmsubs = 427,
+    Fnmsubs = 435,
     /// fres: Floating Reciprocal Estimate Single
-    Fres = 428,
+    Fres = 436,
     /// fsubs: Floating Subtract (Single-Precision)
-    Fsubs = 429,
+    Fsubs = 437,
     /// std: Store Double Word
-    Std = 430,
+    Std = 438,
     /// stdu: Store Double Word with Update
-    Stdu = 431,
+    Stdu = 439,
     /// fabs: Floating Absolute Value
-    Fabs = 432,
+    Fabs = 440,
     /// fadd: Floating Add (Double-Precision)
-    Fadd = 433,
+    Fadd = 441,
     /// fcfid: Floating Convert from Integer Double Word
-    Fcfid = 434,
+    Fcfid = 442,
     /// fcmpo: Floating Compare Ordered
-    Fcmpo = 435,
+    Fcmpo = 443,
     /// fcmpu: Floating Compare Unordered
-    Fcmpu = 436,
+    Fcmpu = 444,
     /// fctid: Floating Convert to Integer Double Word
-    Fctid = 437,
+    Fctid = 445,
     /// fctidz: Floating Convert to Integer Double Word with Round toward Zero
-    Fctidz = 438,
+    Fctidz = 446,
     /// fctiw: Floating Convert to Integer Word
-    Fctiw = 439,
+    Fctiw = 447,
     /// fctiwz: Floating Convert to Integer Word with Round toward Zero
-    Fctiwz = 440,
+    Fctiwz = 448,
     /// fdiv: Floating Divide (Double-Precision)
-    Fdiv = 441,
+    Fdiv = 449,
     /// fmadd: Floating Multiply-Add (Double-Precision)
-    Fmadd = 442,
+    Fmadd = 450,
     /// fmr: Floating Move Register (Double-Precision)
-    Fmr = 443,
+    Fmr = 451,
     /// fmsub: Floating Multiply-Subtract (Double-Precision)
-    Fmsub = 444,
+    Fmsub = 452,
     /// fmul: Floating Multiply (Double-Precision)
-    Fmul = 445,
+    Fmul = 453,
     /// fnabs: Floating Negative Absolute Value
-    Fnabs = 446,
+    Fnabs = 454,
     /// fneg: Floating Negate
-    Fneg = 447,
+    Fneg = 455,
     /// fnmadd: Floating Negative Multiply-Add (Double-Precision)
-    Fnmadd = 448,
+    Fnmadd = 456,
     /// fnmsub: Floating Negative Multiply-Subtract (Double-Precision)
-    Fnmsub = 449,
+    Fnmsub = 457,
     /// frsp: Floating Round to Single
-    Frsp = 450,
+    Frsp = 458,
     /// frsqrte: Floating Reciprocal Square Root Estimate
-    Frsqrte = 451,
+    Frsqrte = 459,
     /// fsel: Floating Select
-    Fsel = 452,
+    Fsel = 460,
     /// fsub: Floating Subtract (Double-Precision)
-    Fsub = 453,
+    Fsub = 461,
     /// mcrfs: Move to Condition Register from FPSCR
-    Mcrfs = 454,
+    Mcrfs = 462,
     /// mffs: Move from FPSCR
-    Mffs = 455,
+    Mffs = 463,
     /// mtfsb0: Move to FPSCR Bit 0
-    Mtfsb0 = 456,
+    Mtfsb0 = 464,
     /// mtfsb1: Move to FPSCR Bit 1
-    Mtfsb1 = 457,
+    Mtfsb1 = 465,
     /// mtfsf: Move to FPSCR Fields
-    Mtfsf = 458,
+    Mtfsf = 466,
     /// mtfsfi: Move to FPSCR Field Immediate
-    Mtfsfi = 459,
+    Mtfsfi = 467,
 }
 impl Opcode {
     #[inline]
@@ -1945,7 +1977,7 @@ impl Opcode {
 impl From<u16> for Opcode {
     #[inline]
     fn from(value: u16) -> Self {
-        if value > 459 {
+        if value > 467 {
             Self::Illegal
         } else {
             // Safety: The enum is repr(u16) and the value is within the enum's range
@@ -2241,17 +2273,17 @@ impl Ins {
     pub const fn field_perm(&self) -> u8 {
         (((self.code >> 16) & 0x1f) | ((self.code >> 1) & 0xe0)) as u8
     }
-    /// Ximm: unknown immediate
+    /// D3DType: the packed data type
     #[inline(always)]
-    pub const fn field_ximm(&self) -> u8 {
+    pub const fn field_d3dtype(&self) -> u8 {
         ((self.code >> 18) & 0x7) as u8
     }
-    /// Yimm: unknown immediate
+    /// VMASK: the pack mask
     #[inline(always)]
-    pub const fn field_yimm(&self) -> u8 {
+    pub const fn field_vmask(&self) -> u8 {
         ((self.code >> 16) & 0x3) as u8
     }
-    /// Zimm: unknown immediate
+    /// Zimm: amount to rotate/shift left
     #[inline(always)]
     pub const fn field_zimm(&self) -> u8 {
         ((self.code >> 6) & 0x3) as u8
@@ -4246,9 +4278,9 @@ fn basic_lvlx128(out: &mut ParsedIns, ins: Ins) {
         ],
     };
 }
-fn basic_lvrx128(out: &mut ParsedIns, ins: Ins) {
+fn basic_lvlxl128(out: &mut ParsedIns, ins: Ins) {
     *out = ParsedIns {
-        mnemonic: "lvrx128",
+        mnemonic: "lvlxl128",
         args: [
             Argument::VR(VR(ins.field_vds128() as _)),
             Argument::GPR(GPR(ins.field_ra() as _)),
@@ -4258,9 +4290,9 @@ fn basic_lvrx128(out: &mut ParsedIns, ins: Ins) {
         ],
     };
 }
-fn basic_lvlxl128(out: &mut ParsedIns, ins: Ins) {
+fn basic_lvrx128(out: &mut ParsedIns, ins: Ins) {
     *out = ParsedIns {
-        mnemonic: "lvlxl128",
+        mnemonic: "lvrx128",
         args: [
             Argument::VR(VR(ins.field_vds128() as _)),
             Argument::GPR(GPR(ins.field_ra() as _)),
@@ -4666,18 +4698,6 @@ fn basic_vpkuwus128(out: &mut ParsedIns, ins: Ins) {
         ],
     };
 }
-fn basic_vrlw128(out: &mut ParsedIns, ins: Ins) {
-    *out = ParsedIns {
-        mnemonic: "vrlw128",
-        args: [
-            Argument::VR(VR(ins.field_vds128() as _)),
-            Argument::VR(VR(ins.field_va128() as _)),
-            Argument::VR(VR(ins.field_vb128() as _)),
-            Argument::None,
-            Argument::None,
-        ],
-    };
-}
 fn basic_vsel128(out: &mut ParsedIns, ins: Ins) {
     *out = ParsedIns {
         mnemonic: "vsel128",
@@ -4702,6 +4722,18 @@ fn basic_vslo128(out: &mut ParsedIns, ins: Ins) {
         ],
     };
 }
+fn basic_vsro128(out: &mut ParsedIns, ins: Ins) {
+    *out = ParsedIns {
+        mnemonic: "vsro128",
+        args: [
+            Argument::VR(VR(ins.field_vds128() as _)),
+            Argument::VR(VR(ins.field_va128() as _)),
+            Argument::VR(VR(ins.field_vb128() as _)),
+            Argument::None,
+            Argument::None,
+        ],
+    };
+}
 fn basic_vsubfp128(out: &mut ParsedIns, ins: Ins) {
     *out = ParsedIns {
         mnemonic: "vsubfp128",
@@ -4939,8 +4971,8 @@ fn basic_vpkd3d128(out: &mut ParsedIns, ins: Ins) {
         args: [
             Argument::VR(VR(ins.field_vds128() as _)),
             Argument::VR(VR(ins.field_vb128() as _)),
-            Argument::OpaqueU(OpaqueU(ins.field_ximm() as _)),
-            Argument::OpaqueU(OpaqueU(ins.field_yimm() as _)),
+            Argument::OpaqueU(OpaqueU(ins.field_d3dtype() as _)),
+            Argument::OpaqueU(OpaqueU(ins.field_vmask() as _)),
             Argument::OpaqueU(OpaqueU(ins.field_zimm() as _)),
         ],
     };
@@ -5017,6 +5049,18 @@ fn basic_vrlimi128(out: &mut ParsedIns, ins: Ins) {
         ],
     };
 }
+fn basic_vrlw128(out: &mut ParsedIns, ins: Ins) {
+    *out = ParsedIns {
+        mnemonic: "vrlw128",
+        args: [
+            Argument::VR(VR(ins.field_vds128() as _)),
+            Argument::VR(VR(ins.field_va128() as _)),
+            Argument::VR(VR(ins.field_vb128() as _)),
+            Argument::None,
+            Argument::None,
+        ],
+    };
+}
 fn basic_vrsqrtefp128(out: &mut ParsedIns, ins: Ins) {
     *out = ParsedIns {
         mnemonic: "vrsqrtefp128",
@@ -5077,18 +5121,6 @@ fn basic_vsraw128(out: &mut ParsedIns, ins: Ins) {
         ],
     };
 }
-fn basic_vsro128(out: &mut ParsedIns, ins: Ins) {
-    *out = ParsedIns {
-        mnemonic: "vsro128",
-        args: [
-            Argument::VR(VR(ins.field_vds128() as _)),
-            Argument::VR(VR(ins.field_va128() as _)),
-            Argument::VR(VR(ins.field_vb128() as _)),
-            Argument::None,
-            Argument::None,
-        ],
-    };
-}
 fn basic_vsrw128(out: &mut ParsedIns, ins: Ins) {
     *out = ParsedIns {
         mnemonic: "vsrw128",
@@ -5106,8 +5138,8 @@ fn basic_vupkd3d128(out: &mut ParsedIns, ins: Ins) {
         mnemonic: "vupkd3d128",
         args: [
             Argument::VR(VR(ins.field_vds128() as _)),
-            Argument::Uimm(Uimm(ins.field_vuimm() as _)),
             Argument::VR(VR(ins.field_vb128() as _)),
+            Argument::Uimm(Uimm(ins.field_vuimm() as _)),
             Argument::None,
             Argument::None,
         ],
@@ -9659,7 +9691,7 @@ fn simplified_dss(out: &mut ParsedIns, ins: Ins) {
         };
         return;
     }
-    if ins.field_ds_a() == 0x1 && ins.field_strm() == 0x0 {
+    if ins.field_ds_a() == 0x1 {
         *out = ParsedIns {
             mnemonic: "dssall",
             args: EMPTY_ARGS,
@@ -9734,6 +9766,54 @@ fn basic_lvewx(out: &mut ParsedIns, ins: Ins) {
         ],
     };
 }
+fn basic_lvlx(out: &mut ParsedIns, ins: Ins) {
+    *out = ParsedIns {
+        mnemonic: "lvlx",
+        args: [
+            Argument::VR(VR(ins.field_vd() as _)),
+            Argument::GPR(GPR(ins.field_ra() as _)),
+            Argument::GPR(GPR(ins.field_rb() as _)),
+            Argument::None,
+            Argument::None,
+        ],
+    };
+}
+fn basic_lvlxl(out: &mut ParsedIns, ins: Ins) {
+    *out = ParsedIns {
+        mnemonic: "lvlxl",
+        args: [
+            Argument::VR(VR(ins.field_vd() as _)),
+            Argument::GPR(GPR(ins.field_ra() as _)),
+            Argument::GPR(GPR(ins.field_rb() as _)),
+            Argument::None,
+            Argument::None,
+        ],
+    };
+}
+fn basic_lvrx(out: &mut ParsedIns, ins: Ins) {
+    *out = ParsedIns {
+        mnemonic: "lvrx",
+        args: [
+            Argument::VR(VR(ins.field_vd() as _)),
+            Argument::GPR(GPR(ins.field_ra() as _)),
+            Argument::GPR(GPR(ins.field_rb() as _)),
+            Argument::None,
+            Argument::None,
+        ],
+    };
+}
+fn basic_lvrxl(out: &mut ParsedIns, ins: Ins) {
+    *out = ParsedIns {
+        mnemonic: "lvrxl",
+        args: [
+            Argument::VR(VR(ins.field_vd() as _)),
+            Argument::GPR(GPR(ins.field_ra() as _)),
+            Argument::GPR(GPR(ins.field_rb() as _)),
+            Argument::None,
+            Argument::None,
+        ],
+    };
+}
 fn basic_lvsl(out: &mut ParsedIns, ins: Ins) {
     *out = ParsedIns {
         mnemonic: "lvsl",
@@ -9818,6 +9898,54 @@ fn basic_stvewx(out: &mut ParsedIns, ins: Ins) {
         ],
     };
 }
+fn basic_stvlx(out: &mut ParsedIns, ins: Ins) {
+    *out = ParsedIns {
+        mnemonic: "stvlx",
+        args: [
+            Argument::VR(VR(ins.field_vs() as _)),
+            Argument::GPR(GPR(ins.field_ra() as _)),
+            Argument::GPR(GPR(ins.field_rb() as _)),
+            Argument::None,
+            Argument::None,
+        ],
+    };
+}
+fn basic_stvlxl(out: &mut ParsedIns, ins: Ins) {
+    *out = ParsedIns {
+        mnemonic: "stvlxl",
+        args: [
+            Argument::VR(VR(ins.field_vs() as _)),
+            Argument::GPR(GPR(ins.field_ra() as _)),
+            Argument::GPR(GPR(ins.field_rb() as _)),
+            Argument::None,
+            Argument::None,
+        ],
+    };
+}
+fn basic_stvrx(out: &mut ParsedIns, ins: Ins) {
+    *out = ParsedIns {
+        mnemonic: "stvrx",
+        args: [
+            Argument::VR(VR(ins.field_vs() as _)),
+            Argument::GPR(GPR(ins.field_ra() as _)),
+            Argument::GPR(GPR(ins.field_rb() as _)),
+            Argument::None,
+            Argument::None,
+        ],
+    };
+}
+fn basic_stvrxl(out: &mut ParsedIns, ins: Ins) {
+    *out = ParsedIns {
+        mnemonic: "stvrxl",
+        args: [
+            Argument::VR(VR(ins.field_vs() as _)),
+            Argument::GPR(GPR(ins.field_ra() as _)),
+            Argument::GPR(GPR(ins.field_rb() as _)),
+            Argument::None,
+            Argument::None,
+        ],
+    };
+}
 fn basic_stvx(out: &mut ParsedIns, ins: Ins) {
     *out = ParsedIns {
         mnemonic: "stvx",
@@ -10739,7 +10867,7 @@ fn basic_mtfsfi(out: &mut ParsedIns, ins: Ins) {
 fn mnemonic_illegal(out: &mut ParsedIns, _ins: Ins) {
     *out = ParsedIns::new();
 }
-static BASIC_MNEMONICS: [MnemonicFunction; 460] = [
+static BASIC_MNEMONICS: [MnemonicFunction; 468] = [
     basic_tdi,
     basic_twi,
     basic_dcbz_l,
@@ -10889,8 +11017,8 @@ static BASIC_MNEMONICS: [MnemonicFunction; 460] = [
     basic_vxor,
     basic_lvewx128,
     basic_lvlx128,
-    basic_lvrx128,
     basic_lvlxl128,
+    basic_lvrx128,
     basic_lvrxl128,
     basic_lvsl128,
     basic_lvsr128,
@@ -10924,9 +11052,9 @@ static BASIC_MNEMONICS: [MnemonicFunction; 460] = [
     basic_vpkuhus128,
     basic_vpkuwum128,
     basic_vpkuwus128,
-    basic_vrlw128,
     basic_vsel128,
     basic_vslo128,
+    basic_vsro128,
     basic_vsubfp128,
     basic_vxor128,
     basic_vcfpsxws128,
@@ -10952,12 +11080,12 @@ static BASIC_MNEMONICS: [MnemonicFunction; 460] = [
     basic_vrfip128,
     basic_vrfiz128,
     basic_vrlimi128,
+    basic_vrlw128,
     basic_vrsqrtefp128,
     basic_vslw128,
     basic_vspltisw128,
     basic_vspltw128,
     basic_vsraw128,
-    basic_vsro128,
     basic_vsrw128,
     basic_vupkd3d128,
     basic_vupkhsb128,
@@ -11125,6 +11253,10 @@ static BASIC_MNEMONICS: [MnemonicFunction; 460] = [
     basic_lvebx,
     basic_lvehx,
     basic_lvewx,
+    basic_lvlx,
+    basic_lvlxl,
+    basic_lvrx,
+    basic_lvrxl,
     basic_lvsl,
     basic_lvsr,
     basic_lvx,
@@ -11132,6 +11264,10 @@ static BASIC_MNEMONICS: [MnemonicFunction; 460] = [
     basic_stvebx,
     basic_stvehx,
     basic_stvewx,
+    basic_stvlx,
+    basic_stvlxl,
+    basic_stvrx,
+    basic_stvrxl,
     basic_stvx,
     basic_stvxl,
     basic_lwz,
@@ -11205,7 +11341,7 @@ static BASIC_MNEMONICS: [MnemonicFunction; 460] = [
 pub fn parse_basic(out: &mut ParsedIns, ins: Ins) {
     BASIC_MNEMONICS.get(ins.op as usize).copied().unwrap_or(mnemonic_illegal)(out, ins)
 }
-static SIMPLIFIED_MNEMONICS: [MnemonicFunction; 460] = [
+static SIMPLIFIED_MNEMONICS: [MnemonicFunction; 468] = [
     simplified_tdi,
     simplified_twi,
     basic_dcbz_l,
@@ -11355,8 +11491,8 @@ static SIMPLIFIED_MNEMONICS: [MnemonicFunction; 460] = [
     basic_vxor,
     basic_lvewx128,
     basic_lvlx128,
-    basic_lvrx128,
     basic_lvlxl128,
+    basic_lvrx128,
     basic_lvrxl128,
     basic_lvsl128,
     basic_lvsr128,
@@ -11390,9 +11526,9 @@ static SIMPLIFIED_MNEMONICS: [MnemonicFunction; 460] = [
     basic_vpkuhus128,
     basic_vpkuwum128,
     basic_vpkuwus128,
-    basic_vrlw128,
     basic_vsel128,
     basic_vslo128,
+    basic_vsro128,
     basic_vsubfp128,
     basic_vxor128,
     basic_vcfpsxws128,
@@ -11418,12 +11554,12 @@ static SIMPLIFIED_MNEMONICS: [MnemonicFunction; 460] = [
     basic_vrfip128,
     basic_vrfiz128,
     basic_vrlimi128,
+    basic_vrlw128,
     basic_vrsqrtefp128,
     basic_vslw128,
     basic_vspltisw128,
     basic_vspltw128,
     basic_vsraw128,
-    basic_vsro128,
     basic_vsrw128,
     basic_vupkd3d128,
     basic_vupkhsb128,
@@ -11591,6 +11727,10 @@ static SIMPLIFIED_MNEMONICS: [MnemonicFunction; 460] = [
     basic_lvebx,
     basic_lvehx,
     basic_lvewx,
+    basic_lvlx,
+    basic_lvlxl,
+    basic_lvrx,
+    basic_lvrxl,
     basic_lvsl,
     basic_lvsr,
     basic_lvx,
@@ -11598,6 +11738,10 @@ static SIMPLIFIED_MNEMONICS: [MnemonicFunction; 460] = [
     basic_stvebx,
     basic_stvehx,
     basic_stvewx,
+    basic_stvlx,
+    basic_stvlxl,
+    basic_stvrx,
+    basic_stvrxl,
     basic_stvx,
     basic_stvxl,
     basic_lwz,
@@ -14291,7 +14435,11 @@ fn defs_lvewx128(out: &mut Arguments, ins: Ins) {
 }
 fn uses_lvewx128(out: &mut Arguments, ins: Ins) {
     *out = [
-        Argument::GPR(GPR(ins.field_ra() as _)),
+        if ins.field_ra() != 0 {
+            Argument::GPR(GPR(ins.field_ra() as _))
+        } else {
+            Argument::None
+        },
         Argument::GPR(GPR(ins.field_rb() as _)),
         Argument::None,
         Argument::None,
@@ -14309,25 +14457,11 @@ fn defs_lvlx128(out: &mut Arguments, ins: Ins) {
 }
 fn uses_lvlx128(out: &mut Arguments, ins: Ins) {
     *out = [
-        Argument::GPR(GPR(ins.field_ra() as _)),
-        Argument::GPR(GPR(ins.field_rb() as _)),
-        Argument::None,
-        Argument::None,
-        Argument::None,
-    ];
-}
-fn defs_lvrx128(out: &mut Arguments, ins: Ins) {
-    *out = [
-        Argument::VR(VR(ins.field_vds128() as _)),
-        Argument::None,
-        Argument::None,
-        Argument::None,
-        Argument::None,
-    ];
-}
-fn uses_lvrx128(out: &mut Arguments, ins: Ins) {
-    *out = [
-        Argument::GPR(GPR(ins.field_ra() as _)),
+        if ins.field_ra() != 0 {
+            Argument::GPR(GPR(ins.field_ra() as _))
+        } else {
+            Argument::None
+        },
         Argument::GPR(GPR(ins.field_rb() as _)),
         Argument::None,
         Argument::None,
@@ -14345,7 +14479,33 @@ fn defs_lvlxl128(out: &mut Arguments, ins: Ins) {
 }
 fn uses_lvlxl128(out: &mut Arguments, ins: Ins) {
     *out = [
-        Argument::GPR(GPR(ins.field_ra() as _)),
+        if ins.field_ra() != 0 {
+            Argument::GPR(GPR(ins.field_ra() as _))
+        } else {
+            Argument::None
+        },
+        Argument::GPR(GPR(ins.field_rb() as _)),
+        Argument::None,
+        Argument::None,
+        Argument::None,
+    ];
+}
+fn defs_lvrx128(out: &mut Arguments, ins: Ins) {
+    *out = [
+        Argument::VR(VR(ins.field_vds128() as _)),
+        Argument::None,
+        Argument::None,
+        Argument::None,
+        Argument::None,
+    ];
+}
+fn uses_lvrx128(out: &mut Arguments, ins: Ins) {
+    *out = [
+        if ins.field_ra() != 0 {
+            Argument::GPR(GPR(ins.field_ra() as _))
+        } else {
+            Argument::None
+        },
         Argument::GPR(GPR(ins.field_rb() as _)),
         Argument::None,
         Argument::None,
@@ -14363,7 +14523,11 @@ fn defs_lvrxl128(out: &mut Arguments, ins: Ins) {
 }
 fn uses_lvrxl128(out: &mut Arguments, ins: Ins) {
     *out = [
-        Argument::GPR(GPR(ins.field_ra() as _)),
+        if ins.field_ra() != 0 {
+            Argument::GPR(GPR(ins.field_ra() as _))
+        } else {
+            Argument::None
+        },
         Argument::GPR(GPR(ins.field_rb() as _)),
         Argument::None,
         Argument::None,
@@ -14381,7 +14545,11 @@ fn defs_lvsl128(out: &mut Arguments, ins: Ins) {
 }
 fn uses_lvsl128(out: &mut Arguments, ins: Ins) {
     *out = [
-        Argument::GPR(GPR(ins.field_ra() as _)),
+        if ins.field_ra() != 0 {
+            Argument::GPR(GPR(ins.field_ra() as _))
+        } else {
+            Argument::None
+        },
         Argument::GPR(GPR(ins.field_rb() as _)),
         Argument::None,
         Argument::None,
@@ -14399,7 +14567,11 @@ fn defs_lvsr128(out: &mut Arguments, ins: Ins) {
 }
 fn uses_lvsr128(out: &mut Arguments, ins: Ins) {
     *out = [
-        Argument::GPR(GPR(ins.field_ra() as _)),
+        if ins.field_ra() != 0 {
+            Argument::GPR(GPR(ins.field_ra() as _))
+        } else {
+            Argument::None
+        },
         Argument::GPR(GPR(ins.field_rb() as _)),
         Argument::None,
         Argument::None,
@@ -14417,7 +14589,11 @@ fn defs_lvx128(out: &mut Arguments, ins: Ins) {
 }
 fn uses_lvx128(out: &mut Arguments, ins: Ins) {
     *out = [
-        Argument::GPR(GPR(ins.field_ra() as _)),
+        if ins.field_ra() != 0 {
+            Argument::GPR(GPR(ins.field_ra() as _))
+        } else {
+            Argument::None
+        },
         Argument::GPR(GPR(ins.field_rb() as _)),
         Argument::None,
         Argument::None,
@@ -14435,7 +14611,11 @@ fn defs_lvxl128(out: &mut Arguments, ins: Ins) {
 }
 fn uses_lvxl128(out: &mut Arguments, ins: Ins) {
     *out = [
-        Argument::GPR(GPR(ins.field_ra() as _)),
+        if ins.field_ra() != 0 {
+            Argument::GPR(GPR(ins.field_ra() as _))
+        } else {
+            Argument::None
+        },
         Argument::GPR(GPR(ins.field_rb() as _)),
         Argument::None,
         Argument::None,
@@ -14444,65 +14624,93 @@ fn uses_lvxl128(out: &mut Arguments, ins: Ins) {
 }
 fn uses_stvewx128(out: &mut Arguments, ins: Ins) {
     *out = [
-        Argument::VR(VR(ins.field_vds128() as _)),
-        Argument::GPR(GPR(ins.field_ra() as _)),
+        if ins.field_ra() != 0 {
+            Argument::GPR(GPR(ins.field_ra() as _))
+        } else {
+            Argument::None
+        },
         Argument::GPR(GPR(ins.field_rb() as _)),
         Argument::None,
         Argument::None,
+        Argument::None,
     ];
 }
 fn uses_stvlx128(out: &mut Arguments, ins: Ins) {
     *out = [
-        Argument::VR(VR(ins.field_vds128() as _)),
-        Argument::GPR(GPR(ins.field_ra() as _)),
+        if ins.field_ra() != 0 {
+            Argument::GPR(GPR(ins.field_ra() as _))
+        } else {
+            Argument::None
+        },
         Argument::GPR(GPR(ins.field_rb() as _)),
         Argument::None,
         Argument::None,
+        Argument::None,
     ];
 }
 fn uses_stvlxl128(out: &mut Arguments, ins: Ins) {
     *out = [
-        Argument::VR(VR(ins.field_vds128() as _)),
-        Argument::GPR(GPR(ins.field_ra() as _)),
+        if ins.field_ra() != 0 {
+            Argument::GPR(GPR(ins.field_ra() as _))
+        } else {
+            Argument::None
+        },
         Argument::GPR(GPR(ins.field_rb() as _)),
         Argument::None,
         Argument::None,
+        Argument::None,
     ];
 }
 fn uses_stvrx128(out: &mut Arguments, ins: Ins) {
     *out = [
-        Argument::VR(VR(ins.field_vds128() as _)),
-        Argument::GPR(GPR(ins.field_ra() as _)),
+        if ins.field_ra() != 0 {
+            Argument::GPR(GPR(ins.field_ra() as _))
+        } else {
+            Argument::None
+        },
         Argument::GPR(GPR(ins.field_rb() as _)),
         Argument::None,
         Argument::None,
+        Argument::None,
     ];
 }
 fn uses_stvrxl128(out: &mut Arguments, ins: Ins) {
     *out = [
-        Argument::VR(VR(ins.field_vds128() as _)),
-        Argument::GPR(GPR(ins.field_ra() as _)),
+        if ins.field_ra() != 0 {
+            Argument::GPR(GPR(ins.field_ra() as _))
+        } else {
+            Argument::None
+        },
         Argument::GPR(GPR(ins.field_rb() as _)),
         Argument::None,
         Argument::None,
+        Argument::None,
     ];
 }
 fn uses_stvx128(out: &mut Arguments, ins: Ins) {
     *out = [
-        Argument::VR(VR(ins.field_vds128() as _)),
-        Argument::GPR(GPR(ins.field_ra() as _)),
+        if ins.field_ra() != 0 {
+            Argument::GPR(GPR(ins.field_ra() as _))
+        } else {
+            Argument::None
+        },
         Argument::GPR(GPR(ins.field_rb() as _)),
         Argument::None,
         Argument::None,
+        Argument::None,
     ];
 }
 fn uses_stvxl128(out: &mut Arguments, ins: Ins) {
     *out = [
-        Argument::VR(VR(ins.field_vds128() as _)),
-        Argument::GPR(GPR(ins.field_ra() as _)),
+        if ins.field_ra() != 0 {
+            Argument::GPR(GPR(ins.field_ra() as _))
+        } else {
+            Argument::None
+        },
         Argument::GPR(GPR(ins.field_rb() as _)),
         Argument::None,
         Argument::None,
+        Argument::None,
     ];
 }
 fn defs_vsldoi128(out: &mut Arguments, ins: Ins) {
@@ -14883,24 +15091,6 @@ fn uses_vpkuwus128(out: &mut Arguments, ins: Ins) {
         Argument::None,
     ];
 }
-fn defs_vrlw128(out: &mut Arguments, ins: Ins) {
-    *out = [
-        Argument::VR(VR(ins.field_vds128() as _)),
-        Argument::None,
-        Argument::None,
-        Argument::None,
-        Argument::None,
-    ];
-}
-fn uses_vrlw128(out: &mut Arguments, ins: Ins) {
-    *out = [
-        Argument::VR(VR(ins.field_va128() as _)),
-        Argument::VR(VR(ins.field_vb128() as _)),
-        Argument::None,
-        Argument::None,
-        Argument::None,
-    ];
-}
 fn defs_vsel128(out: &mut Arguments, ins: Ins) {
     *out = [
         Argument::VR(VR(ins.field_vds128() as _)),
@@ -14937,6 +15127,24 @@ fn uses_vslo128(out: &mut Arguments, ins: Ins) {
         Argument::None,
     ];
 }
+fn defs_vsro128(out: &mut Arguments, ins: Ins) {
+    *out = [
+        Argument::VR(VR(ins.field_vds128() as _)),
+        Argument::None,
+        Argument::None,
+        Argument::None,
+        Argument::None,
+    ];
+}
+fn uses_vsro128(out: &mut Arguments, ins: Ins) {
+    *out = [
+        Argument::VR(VR(ins.field_va128() as _)),
+        Argument::VR(VR(ins.field_vb128() as _)),
+        Argument::None,
+        Argument::None,
+        Argument::None,
+    ];
+}
 fn defs_vsubfp128(out: &mut Arguments, ins: Ins) {
     *out = [
         Argument::VR(VR(ins.field_vds128() as _)),
@@ -15273,8 +15481,8 @@ fn defs_vpkd3d128(out: &mut Arguments, ins: Ins) {
 fn uses_vpkd3d128(out: &mut Arguments, ins: Ins) {
     *out = [
         Argument::VR(VR(ins.field_vb128() as _)),
-        Argument::OpaqueU(OpaqueU(ins.field_ximm() as _)),
-        Argument::OpaqueU(OpaqueU(ins.field_yimm() as _)),
+        Argument::OpaqueU(OpaqueU(ins.field_d3dtype() as _)),
+        Argument::OpaqueU(OpaqueU(ins.field_vmask() as _)),
         Argument::OpaqueU(OpaqueU(ins.field_zimm() as _)),
         Argument::None,
     ];
@@ -15387,6 +15595,24 @@ fn uses_vrlimi128(out: &mut Arguments, ins: Ins) {
         Argument::None,
     ];
 }
+fn defs_vrlw128(out: &mut Arguments, ins: Ins) {
+    *out = [
+        Argument::VR(VR(ins.field_vds128() as _)),
+        Argument::None,
+        Argument::None,
+        Argument::None,
+        Argument::None,
+    ];
+}
+fn uses_vrlw128(out: &mut Arguments, ins: Ins) {
+    *out = [
+        Argument::VR(VR(ins.field_va128() as _)),
+        Argument::VR(VR(ins.field_vb128() as _)),
+        Argument::None,
+        Argument::None,
+        Argument::None,
+    ];
+}
 fn defs_vrsqrtefp128(out: &mut Arguments, ins: Ins) {
     *out = [
         Argument::VR(VR(ins.field_vds128() as _)),
@@ -15477,24 +15703,6 @@ fn uses_vsraw128(out: &mut Arguments, ins: Ins) {
         Argument::None,
     ];
 }
-fn defs_vsro128(out: &mut Arguments, ins: Ins) {
-    *out = [
-        Argument::VR(VR(ins.field_vds128() as _)),
-        Argument::None,
-        Argument::None,
-        Argument::None,
-        Argument::None,
-    ];
-}
-fn uses_vsro128(out: &mut Arguments, ins: Ins) {
-    *out = [
-        Argument::VR(VR(ins.field_va128() as _)),
-        Argument::VR(VR(ins.field_vb128() as _)),
-        Argument::None,
-        Argument::None,
-        Argument::None,
-    ];
-}
 fn defs_vsrw128(out: &mut Arguments, ins: Ins) {
     *out = [
         Argument::VR(VR(ins.field_vds128() as _)),
@@ -15524,8 +15732,8 @@ fn defs_vupkd3d128(out: &mut Arguments, ins: Ins) {
 }
 fn uses_vupkd3d128(out: &mut Arguments, ins: Ins) {
     *out = [
-        Argument::Uimm(Uimm(ins.field_vuimm() as _)),
         Argument::VR(VR(ins.field_vb128() as _)),
+        Argument::Uimm(Uimm(ins.field_vuimm() as _)),
         Argument::None,
         Argument::None,
         Argument::None,
@@ -18085,6 +18293,94 @@ fn uses_lvewx(out: &mut Arguments, ins: Ins) {
         Argument::None,
     ];
 }
+fn defs_lvlx(out: &mut Arguments, ins: Ins) {
+    *out = [
+        Argument::VR(VR(ins.field_vd() as _)),
+        Argument::None,
+        Argument::None,
+        Argument::None,
+        Argument::None,
+    ];
+}
+fn uses_lvlx(out: &mut Arguments, ins: Ins) {
+    *out = [
+        if ins.field_ra() != 0 {
+            Argument::GPR(GPR(ins.field_ra() as _))
+        } else {
+            Argument::None
+        },
+        Argument::GPR(GPR(ins.field_rb() as _)),
+        Argument::None,
+        Argument::None,
+        Argument::None,
+    ];
+}
+fn defs_lvlxl(out: &mut Arguments, ins: Ins) {
+    *out = [
+        Argument::VR(VR(ins.field_vd() as _)),
+        Argument::None,
+        Argument::None,
+        Argument::None,
+        Argument::None,
+    ];
+}
+fn uses_lvlxl(out: &mut Arguments, ins: Ins) {
+    *out = [
+        if ins.field_ra() != 0 {
+            Argument::GPR(GPR(ins.field_ra() as _))
+        } else {
+            Argument::None
+        },
+        Argument::GPR(GPR(ins.field_rb() as _)),
+        Argument::None,
+        Argument::None,
+        Argument::None,
+    ];
+}
+fn defs_lvrx(out: &mut Arguments, ins: Ins) {
+    *out = [
+        Argument::VR(VR(ins.field_vd() as _)),
+        Argument::None,
+        Argument::None,
+        Argument::None,
+        Argument::None,
+    ];
+}
+fn uses_lvrx(out: &mut Arguments, ins: Ins) {
+    *out = [
+        if ins.field_ra() != 0 {
+            Argument::GPR(GPR(ins.field_ra() as _))
+        } else {
+            Argument::None
+        },
+        Argument::GPR(GPR(ins.field_rb() as _)),
+        Argument::None,
+        Argument::None,
+        Argument::None,
+    ];
+}
+fn defs_lvrxl(out: &mut Arguments, ins: Ins) {
+    *out = [
+        Argument::VR(VR(ins.field_vd() as _)),
+        Argument::None,
+        Argument::None,
+        Argument::None,
+        Argument::None,
+    ];
+}
+fn uses_lvrxl(out: &mut Arguments, ins: Ins) {
+    *out = [
+        if ins.field_ra() != 0 {
+            Argument::GPR(GPR(ins.field_ra() as _))
+        } else {
+            Argument::None
+        },
+        Argument::GPR(GPR(ins.field_rb() as _)),
+        Argument::None,
+        Argument::None,
+        Argument::None,
+    ];
+}
 fn defs_lvsl(out: &mut Arguments, ins: Ins) {
     *out = [
         Argument::VR(VR(ins.field_vd() as _)),
@@ -18212,6 +18508,58 @@ fn uses_stvewx(out: &mut Arguments, ins: Ins) {
         Argument::None,
     ];
 }
+fn uses_stvlx(out: &mut Arguments, ins: Ins) {
+    *out = [
+        if ins.field_ra() != 0 {
+            Argument::GPR(GPR(ins.field_ra() as _))
+        } else {
+            Argument::None
+        },
+        Argument::GPR(GPR(ins.field_rb() as _)),
+        Argument::None,
+        Argument::None,
+        Argument::None,
+    ];
+}
+fn uses_stvlxl(out: &mut Arguments, ins: Ins) {
+    *out = [
+        if ins.field_ra() != 0 {
+            Argument::GPR(GPR(ins.field_ra() as _))
+        } else {
+            Argument::None
+        },
+        Argument::GPR(GPR(ins.field_rb() as _)),
+        Argument::None,
+        Argument::None,
+        Argument::None,
+    ];
+}
+fn uses_stvrx(out: &mut Arguments, ins: Ins) {
+    *out = [
+        if ins.field_ra() != 0 {
+            Argument::GPR(GPR(ins.field_ra() as _))
+        } else {
+            Argument::None
+        },
+        Argument::GPR(GPR(ins.field_rb() as _)),
+        Argument::None,
+        Argument::None,
+        Argument::None,
+    ];
+}
+fn uses_stvrxl(out: &mut Arguments, ins: Ins) {
+    *out = [
+        if ins.field_ra() != 0 {
+            Argument::GPR(GPR(ins.field_ra() as _))
+        } else {
+            Argument::None
+        },
+        Argument::GPR(GPR(ins.field_rb() as _)),
+        Argument::None,
+        Argument::None,
+        Argument::None,
+    ];
+}
 fn uses_stvx(out: &mut Arguments, ins: Ins) {
     *out = [
         if ins.field_ra() != 0 {
@@ -19385,7 +19733,7 @@ fn defs_mtfsfi(out: &mut Arguments, ins: Ins) {
 fn defs_uses_empty(out: &mut Arguments, _ins: Ins) {
     *out = EMPTY_ARGS;
 }
-static DEFS_FUNCTIONS: [DefsUsesFunction; 460] = [
+static DEFS_FUNCTIONS: [DefsUsesFunction; 468] = [
     defs_uses_empty,
     defs_uses_empty,
     defs_uses_empty,
@@ -19535,8 +19883,8 @@ static DEFS_FUNCTIONS: [DefsUsesFunction; 460] = [
     defs_vxor,
     defs_lvewx128,
     defs_lvlx128,
-    defs_lvrx128,
     defs_lvlxl128,
+    defs_lvrx128,
     defs_lvrxl128,
     defs_lvsl128,
     defs_lvsr128,
@@ -19570,9 +19918,9 @@ static DEFS_FUNCTIONS: [DefsUsesFunction; 460] = [
     defs_vpkuhus128,
     defs_vpkuwum128,
     defs_vpkuwus128,
-    defs_vrlw128,
     defs_vsel128,
     defs_vslo128,
+    defs_vsro128,
     defs_vsubfp128,
     defs_vxor128,
     defs_vcfpsxws128,
@@ -19598,12 +19946,12 @@ static DEFS_FUNCTIONS: [DefsUsesFunction; 460] = [
     defs_vrfip128,
     defs_vrfiz128,
     defs_vrlimi128,
+    defs_vrlw128,
     defs_vrsqrtefp128,
     defs_vslw128,
     defs_vspltisw128,
     defs_vspltw128,
     defs_vsraw128,
-    defs_vsro128,
     defs_vsrw128,
     defs_vupkd3d128,
     defs_vupkhsb128,
@@ -19771,6 +20119,10 @@ static DEFS_FUNCTIONS: [DefsUsesFunction; 460] = [
     defs_lvebx,
     defs_lvehx,
     defs_lvewx,
+    defs_lvlx,
+    defs_lvlxl,
+    defs_lvrx,
+    defs_lvrxl,
     defs_lvsl,
     defs_lvsr,
     defs_lvx,
@@ -19780,6 +20132,10 @@ static DEFS_FUNCTIONS: [DefsUsesFunction; 460] = [
     defs_uses_empty,
     defs_uses_empty,
     defs_uses_empty,
+    defs_uses_empty,
+    defs_uses_empty,
+    defs_uses_empty,
+    defs_uses_empty,
     defs_lwz,
     defs_lwzu,
     defs_lbz,
@@ -19851,7 +20207,7 @@ static DEFS_FUNCTIONS: [DefsUsesFunction; 460] = [
 pub fn parse_defs(out: &mut Arguments, ins: Ins) {
     DEFS_FUNCTIONS.get(ins.op as usize).copied().unwrap_or(defs_uses_empty)(out, ins)
 }
-static USES_FUNCTIONS: [DefsUsesFunction; 460] = [
+static USES_FUNCTIONS: [DefsUsesFunction; 468] = [
     uses_tdi,
     uses_twi,
     uses_dcbz_l,
@@ -20001,8 +20357,8 @@ static USES_FUNCTIONS: [DefsUsesFunction; 460] = [
     uses_vxor,
     uses_lvewx128,
     uses_lvlx128,
-    uses_lvrx128,
     uses_lvlxl128,
+    uses_lvrx128,
     uses_lvrxl128,
     uses_lvsl128,
     uses_lvsr128,
@@ -20036,9 +20392,9 @@ static USES_FUNCTIONS: [DefsUsesFunction; 460] = [
     uses_vpkuhus128,
     uses_vpkuwum128,
     uses_vpkuwus128,
-    uses_vrlw128,
     uses_vsel128,
     uses_vslo128,
+    uses_vsro128,
     uses_vsubfp128,
     uses_vxor128,
     uses_vcfpsxws128,
@@ -20064,12 +20420,12 @@ static USES_FUNCTIONS: [DefsUsesFunction; 460] = [
     uses_vrfip128,
     uses_vrfiz128,
     uses_vrlimi128,
+    uses_vrlw128,
     uses_vrsqrtefp128,
     uses_vslw128,
     uses_vspltisw128,
     uses_vspltw128,
     uses_vsraw128,
-    uses_vsro128,
     uses_vsrw128,
     uses_vupkd3d128,
     uses_vupkhsb128,
@@ -20237,6 +20593,10 @@ static USES_FUNCTIONS: [DefsUsesFunction; 460] = [
     uses_lvebx,
     uses_lvehx,
     uses_lvewx,
+    uses_lvlx,
+    uses_lvlxl,
+    uses_lvrx,
+    uses_lvrxl,
     uses_lvsl,
     uses_lvsr,
     uses_lvx,
@@ -20244,6 +20604,10 @@ static USES_FUNCTIONS: [DefsUsesFunction; 460] = [
     uses_stvebx,
     uses_stvehx,
     uses_stvewx,
+    uses_stvlx,
+    uses_stvlxl,
+    uses_stvrx,
+    uses_stvrxl,
     uses_stvx,
     uses_stvxl,
     uses_lwz,
diff --git a/disasm/tests/test_altivec.rs b/disasm/tests/test_altivec.rs
new file mode 100644
index 0000000..9cd617b
--- /dev/null
+++ b/disasm/tests/test_altivec.rs
@@ -0,0 +1,829 @@
+use ppc750cl::{Argument, Ins, InsIter, Opcode, GPR};
+
+macro_rules! assert_asm {
+    ($ins:ident, $disasm:literal) => {{
+        assert_eq!(format!("{}", $ins.simplified()), $disasm)
+    }};
+    ($code:literal, $disasm:literal) => {{
+        let ins = Ins::new($code);
+        assert_eq!(format!("{}", ins.simplified()), $disasm)
+    }};
+}
+
+macro_rules! assert_basic {
+    ($ins:ident, $disasm:literal) => {{
+        assert_eq!(format!("{}", $ins.basic_form()), $disasm)
+    }};
+    ($code:literal, $disasm:literal) => {{
+        let ins = Ins::new($code);
+        assert_eq!(format!("{}", ins.basic()), $disasm)
+    }};
+}
+
+#[test]
+fn test_vec_dss(){
+    assert_asm!(0x7C60066C, "dss 3");
+    assert_asm!(0x7E60066C, "dssall");
+}
+
+#[test]
+fn test_vec_dst(){
+    assert_asm!(0x7C6742AC, "dst r7, r8, 3");
+    assert_asm!(0x7E232AAC, "dstt r3, r5, 1");
+}
+
+#[test]
+fn test_vec_dstst(){
+    assert_asm!(0x7C44FAEC, "dstst r4, r31, 2");
+    assert_asm!(0x7E63DAEC, "dststt r3, r27, 3");
+}
+
+#[test]
+fn test_vec_lvebx(){
+    assert_asm!(0x7C64380E, "lvebx vr3, r4, r7");
+}
+
+#[test]
+fn test_vec_lvehx(){
+    assert_asm!(0x7CA8F84E, "lvehx vr5, r8, r31");
+}
+
+#[test]
+fn test_vec_lvewx(){
+    assert_asm!(0x7D09508E, "lvewx vr8, r9, r10");
+}
+
+#[test]
+fn test_vec_lvsl(){
+    assert_asm!(0x7CA6480C, "lvsl vr5, r6, r9");
+}
+
+#[test]
+fn test_vec_lvsr(){
+    assert_asm!(0x7C60284C, "lvsr vr3, r0, r5");
+}
+
+#[test]
+fn test_vec_lvx(){
+    assert_asm!(0x7CF2E8CE, "lvx vr7, r18, r29");
+}
+
+#[test]
+fn test_vec_lvxl(){
+    assert_asm!(0x7D17FACE, "lvxl vr8, r23, r31");
+}
+
+#[test]
+fn test_vec_mfvscr(){
+    assert_asm!(0x13E00604, "mfvscr vr31");
+}
+
+#[test]
+fn test_vec_mtvscr(){
+    assert_asm!(0x1000CE44, "mtvscr vr25");
+}
+
+#[test]
+fn test_vec_stvebx(){
+    assert_asm!(0x7CE3210E, "stvebx vr7, r3, r4");
+}
+
+#[test]
+fn test_vec_stvehx(){
+    assert_asm!(0x7F25514E, "stvehx vr25, r5, r10");
+}
+
+#[test]
+fn test_vec_stvewx(){
+    assert_asm!(0x7E08498E, "stvewx vr16, r8, r9");
+}
+
+#[test]
+fn test_vec_stvx(){
+    assert_asm!(0x7FE039CE, "stvx vr31, r0, r7");
+}
+
+#[test]
+fn test_vec_stvxl(){
+    assert_asm!(0x7E8EF3CE, "stvxl vr20, r14, r30");
+}
+
+#[test]
+fn test_vec_vaddcuw(){
+    assert_asm!(0x10A63980, "vaddcuw vr5, vr6, vr7");
+}
+
+#[test]
+fn test_vec_vaddfp(){
+    assert_asm!(0x13BEF80A, "vaddfp vr29, vr30, vr31");
+}
+
+#[test]
+fn test_vec_vaddsbs(){
+    assert_asm!(0x10035300, "vaddsbs vr0, vr3, vr10");
+}
+
+#[test]
+fn test_vec_vaddsws(){
+    assert_asm!(0x11043B80, "vaddsws vr8, vr4, vr7");
+}
+
+#[test]
+fn test_vec_vaddubm(){
+    assert_asm!(0x100CE000, "vaddubm vr0, vr12, vr28");
+}
+
+#[test]
+fn test_vec_vaddubs(){
+    assert_asm!(0x10AACA00, "vaddubs vr5, vr10, vr25");
+}
+
+#[test]
+fn test_vec_vadduhm(){
+    assert_asm!(0x1112E040, "vadduhm vr8, vr18, vr28");
+}
+
+#[test]
+fn test_vec_vadduhs(){
+    assert_asm!(0x1071EA40, "vadduhs vr3, vr17, vr29");
+}
+
+#[test]
+fn test_vec_vadduwm(){
+    assert_asm!(0x10D6F080, "vadduwm vr6, vr22, vr30");
+}
+
+#[test]
+fn test_vec_vadduws(){
+    assert_asm!(0x1109B280, "vadduws vr8, vr9, vr22");
+}
+
+#[test]
+fn test_vec_vand(){
+    assert_asm!(0x1156BC04, "vand vr10, vr22, vr23");
+}
+
+#[test]
+fn test_vec_vandc(){
+    assert_asm!(0x10F4F444, "vandc vr7, vr20, vr30");
+}
+
+#[test]
+fn test_vec_vavgsb(){
+    assert_asm!(0x10BC1D02, "vavgsb vr5, vr28, vr3");
+}
+
+#[test]
+fn test_vec_vavgsh(){
+    assert_asm!(0x106DBD42, "vavgsh vr3, vr13, vr23");
+}
+
+#[test]
+fn test_vec_vavgsw(){
+    assert_asm!(0x112CAD82, "vavgsw vr9, vr12, vr21");
+}
+
+#[test]
+fn test_vec_vavgub(){
+    assert_asm!(0x100FF402, "vavgub vr0, vr15, vr30");
+}
+
+#[test]
+fn test_vec_vavguh(){
+    assert_asm!(0x108EC442, "vavguh vr4, vr14, vr24");
+}
+
+#[test]
+fn test_vec_vavguw(){
+    assert_asm!(0x10674482, "vavguw vr3, vr7, vr8");
+}
+
+#[test]
+fn test_vec_vcfsx(){
+    assert_asm!(0x101D534A, "vcfsx vr0, vr10, 0x1d");
+}
+
+#[test]
+fn test_vec_vcfux(){
+    assert_asm!(0x10B03B0A, "vcfux vr5, vr7, 0x10");
+}
+
+#[test]
+fn test_vec_vcmpbfp(){
+    assert_asm!(0x106963C6, "vcmpbfp vr3, vr9, vr12");
+    assert_asm!(0x10E84FC6, "vcmpbfp. vr7, vr8, vr9");
+}
+
+#[test]
+fn test_vec_vcmpeqfp(){
+    assert_asm!(0x108640C6, "vcmpeqfp vr4, vr6, vr8");
+    assert_asm!(0x10A304C6, "vcmpeqfp. vr5, vr3, vr0");
+}
+
+#[test]
+fn test_vec_vcmpequb(){
+    assert_asm!(0x1011D806, "vcmpequb vr0, vr17, vr27");
+    assert_asm!(0x10649C06, "vcmpequb. vr3, vr4, vr19");
+}
+
+#[test]
+fn test_vec_vcmpequh(){
+    assert_asm!(0x10A86046, "vcmpequh vr5, vr8, vr12");
+    assert_asm!(0x10E60446, "vcmpequh. vr7, vr6, vr0");
+}
+
+#[test]
+fn test_vec_vcmpequw(){
+    assert_asm!(0x10664086, "vcmpequw vr3, vr6, vr8");
+    assert_asm!(0x10A85486, "vcmpequw. vr5, vr8, vr10");
+}
+
+#[test]
+fn test_vec_vcmpgefp(){
+    assert_asm!(0x100329C6, "vcmpgefp vr0, vr3, vr5");
+    assert_asm!(0x108545C6, "vcmpgefp. vr4, vr5, vr8");
+}
+
+#[test]
+fn test_vec_vcmpgtfp(){
+    assert_asm!(0x10A0CAC6, "vcmpgtfp vr5, vr0, vr25");
+    assert_asm!(0x10E3A6C6, "vcmpgtfp. vr7, vr3, vr20");
+}
+
+#[test]
+fn test_vec_vcmpgtsb(){
+    assert_asm!(0x10602306, "vcmpgtsb vr3, vr0, vr4");
+    assert_asm!(0x10E88706, "vcmpgtsb. vr7, vr8, vr16");
+}
+
+#[test]
+fn test_vec_vcmpgtsh(){
+    assert_asm!(0x10A69B46, "vcmpgtsh vr5, vr6, vr19");
+    assert_asm!(0x1192C746, "vcmpgtsh. vr12, vr18, vr24");
+}
+
+#[test]
+fn test_vec_vcmpgtsw(){
+    assert_asm!(0x1140F386, "vcmpgtsw vr10, vr0, vr30");
+    assert_asm!(0x1297DF86, "vcmpgtsw. vr20, vr23, vr27");
+}
+
+#[test]
+fn test_vec_vcmpgtub(){
+    assert_asm!(0x10A88206, "vcmpgtub vr5, vr8, vr16");
+    assert_asm!(0x13CAA606, "vcmpgtub. vr30, vr10, vr20");
+}
+
+#[test]
+fn test_vec_vcmpgtuh(){
+    assert_asm!(0x101BFA46, "vcmpgtuh vr0, vr27, vr31");
+    assert_asm!(0x10853646, "vcmpgtuh. vr4, vr5, vr6");
+}
+
+#[test]
+fn test_vec_vcmpgtuw(){
+    assert_asm!(0x1070D286, "vcmpgtuw vr3, vr16, vr26");
+    assert_asm!(0x10FAFE86, "vcmpgtuw. vr7, vr26, vr31");
+}
+
+#[test]
+fn test_vec_vctsxs(){
+    assert_asm!(0x10743BCA, "vctsxs vr3, vr7, 0x14");
+}
+
+#[test]
+fn test_vec_vctuxs(){
+    assert_asm!(0x10AB638A, "vctuxs vr5, vr12, 0xb");
+}
+
+#[test]
+fn test_vec_vexptefp(){
+    assert_asm!(0x10E0518A, "vexptefp vr7, vr10");
+}
+
+#[test]
+fn test_vec_vlogefp(){
+    assert_asm!(0x100031CA, "vlogefp vr0, vr6");
+}
+
+#[test]
+fn test_vec_vmaddfp(){
+    assert_asm!(0x1003396E, "vmaddfp vr0, vr3, vr5, vr7");
+}
+
+#[test]
+fn test_vec_vmaxfp(){
+    assert_asm!(0x10C84C0A, "vmaxfp vr6, vr8, vr9");
+}
+
+#[test]
+fn test_vec_vmaxsb(){
+    assert_asm!(0x100AB102, "vmaxsb vr0, vr10, vr22");
+}
+
+#[test]
+fn test_vec_vmaxsh(){
+    assert_asm!(0x1298E142, "vmaxsh vr20, vr24, vr28");
+}
+
+#[test]
+fn test_vec_vmaxsw(){
+    assert_asm!(0x13DF6182, "vmaxsw vr30, vr31, vr12");
+}
+
+#[test]
+fn test_vec_vmaxub(){
+    assert_asm!(0x1198F002, "vmaxub vr12, vr24, vr30");
+}
+
+#[test]
+fn test_vec_vmaxuh(){
+    assert_asm!(0x1236D842, "vmaxuh vr17, vr22, vr27");
+}
+
+#[test]
+fn test_vec_vmaxuw(){
+    assert_asm!(0x114CC082, "vmaxuw vr10, vr12, vr24");
+}
+
+#[test]
+fn test_vec_vmhaddshs(){
+    assert_asm!(0x10A63A20, "vmhaddshs vr5, vr6, vr7, vr8");
+}
+
+#[test]
+fn test_vec_vmhraddshs(){
+    assert_asm!(0x112A63A1, "vmhraddshs vr9, vr10, vr12, vr14");
+}
+
+#[test]
+fn test_vec_vminfp(){
+    assert_asm!(0x106AAC4A, "vminfp vr3, vr10, vr21");
+}
+
+#[test]
+fn test_vec_vminsb(){
+    assert_asm!(0x10643B02, "vminsb vr3, vr4, vr7");
+}
+
+#[test]
+fn test_vec_vminsh(){
+    assert_asm!(0x10E9B342, "vminsh vr7, vr9, vr22");
+}
+
+#[test]
+fn test_vec_vminsw(){
+    assert_asm!(0x118F9382, "vminsw vr12, vr15, vr18");
+}
+
+#[test]
+fn test_vec_vminub(){
+    assert_asm!(0x108ED202, "vminub vr4, vr14, vr26");
+}
+
+#[test]
+fn test_vec_vminuh(){
+    assert_asm!(0x11F19A42, "vminuh vr15, vr17, vr19");
+}
+
+#[test]
+fn test_vec_vminuw(){
+    assert_asm!(0x1254F282, "vminuw vr18, vr20, vr30");
+}
+
+#[test]
+fn test_vec_vmladduhm(){
+    assert_asm!(0x10608762, "vmladduhm vr3, vr0, vr16, vr29");
+}
+
+#[test]
+fn test_vec_vmrghb(){
+    assert_asm!(0x10F4A80C, "vmrghb vr7, vr20, vr21");
+}
+
+#[test]
+fn test_vec_vmrghh(){
+    assert_asm!(0x110AC84C, "vmrghh vr8, vr10, vr25");
+}
+
+#[test]
+fn test_vec_vmrghw(){
+    assert_asm!(0x1198E08C, "vmrghw vr12, vr24, vr28");
+}
+
+#[test]
+fn test_vec_vmrglb(){
+    assert_asm!(0x1299F10C, "vmrglb vr20, vr25, vr30");
+}
+
+#[test]
+fn test_vec_vmrglh(){
+    assert_asm!(0x131CF94C, "vmrglh vr24, vr28, vr31");
+}
+
+#[test]
+fn test_vec_vmrglw(){
+    assert_asm!(0x13DF018C, "vmrglw vr30, vr31, vr0");
+}
+
+#[test]
+fn test_vec_vmsummbm(){
+    assert_asm!(0x10044325, "vmsummbm vr0, vr4, vr8, vr12");
+}
+
+#[test]
+fn test_vec_vmsumshm(){
+    assert_asm!(0x1114DFE8, "vmsumshm vr8, vr20, vr27, vr31");
+}
+
+#[test]
+fn test_vec_vmsumshs(){
+    assert_asm!(0x1150ADE9, "vmsumshs vr10, vr16, vr21, vr23");
+}
+
+#[test]
+fn test_vec_vmsumubm(){
+    assert_asm!(0x1198D7A4, "vmsumubm vr12, vr24, vr26, vr30");
+}
+
+#[test]
+fn test_vec_vmsumuhm(){
+    assert_asm!(0x13C503E6, "vmsumuhm vr30, vr5, vr0, vr15");
+}
+
+#[test]
+fn test_vec_vmsumuhs(){
+    assert_asm!(0x10032167, "vmsumuhs vr0, vr3, vr4, vr5");
+}
+
+#[test]
+fn test_vec_vmulesb(){
+    assert_asm!(0x110EC308, "vmulesb vr8, vr14, vr24");
+}
+
+#[test]
+fn test_vec_vmulesh(){
+    assert_asm!(0x10602B48, "vmulesh vr3, vr0, vr5");
+}
+
+#[test]
+fn test_vec_vmuleub(){
+    assert_asm!(0x10076208, "vmuleub vr0, vr7, vr12");
+}
+
+#[test]
+fn test_vec_vmuleuh(){
+    assert_asm!(0x1200FA48, "vmuleuh vr16, vr0, vr31");
+}
+
+#[test]
+fn test_vec_vmulosb(){
+    assert_asm!(0x11E01908, "vmulosb vr15, vr0, vr3");
+}
+
+#[test]
+fn test_vec_vmulosh(){
+    assert_asm!(0x10685148, "vmulosh vr3, vr8, vr10");
+}
+
+#[test]
+fn test_vec_vmuloub(){
+    assert_asm!(0x10854008, "vmuloub vr4, vr5, vr8");
+}
+
+#[test]
+fn test_vec_vmulouh(){
+    assert_asm!(0x10A70048, "vmulouh vr5, vr7, vr0");
+}
+
+#[test]
+fn test_vec_vnmsubfp(){
+    assert_asm!(0x1060F42F, "vnmsubfp vr3, vr0, vr16, vr30");
+}
+
+#[test]
+fn test_vec_vnor(){
+    assert_asm!(0x10605504, "vnor vr3, vr0, vr10");
+    assert_asm!(0x10884504, "vnot vr4, vr8");
+}
+
+#[test]
+fn test_vec_vor(){
+    assert_asm!(0x100D7C84, "vor vr0, vr13, vr15");
+    assert_asm!(0x1077BC84, "vmr vr3, vr23");
+}
+
+#[test]
+fn test_vec_vperm(){
+    assert_asm!(0x10a5302b, "vperm vr5, vr5, vr6, vr0");
+}
+
+#[test]
+fn test_vec_vpkpx(){
+    assert_asm!(0x10AFE30E, "vpkpx vr5, vr15, vr28");
+}
+
+#[test]
+fn test_vec_vpkshss(){
+    assert_asm!(0x1006498E, "vpkshss vr0, vr6, vr9");
+}
+
+#[test]
+fn test_vec_vpkshus(){
+    assert_asm!(0x1220990E, "vpkshus vr17, vr0, vr19");
+}
+
+#[test]
+fn test_vec_vpkswss(){
+    assert_asm!(0x1253A1CE, "vpkswss vr18, vr19, vr20");
+}
+
+#[test]
+fn test_vec_vpkswus(){
+    assert_asm!(0x128AF14E, "vpkswus vr20, vr10, vr30");
+}
+
+#[test]
+fn test_vec_vpkuhum(){
+    assert_asm!(0x10BBA00E, "vpkuhum vr5, vr27, vr20");
+}
+
+#[test]
+fn test_vec_vpkuhus(){
+    assert_asm!(0x11AE788E, "vpkuhus vr13, vr14, vr15");
+}
+
+#[test]
+fn test_vec_vpkuwum(){
+    assert_asm!(0x114B604E, "vpkuwum vr10, vr11, vr12");
+}
+
+#[test]
+fn test_vec_vpkuwus(){
+    assert_asm!(0x1176F8CE, "vpkuwus vr11, vr22, vr31");
+}
+
+#[test]
+fn test_vec_vrefp(){
+    assert_asm!(0x1180C10A, "vrefp vr12, vr24");
+}
+
+#[test]
+fn test_vec_vrfim(){
+    assert_asm!(0x1240F2CA, "vrfim vr18, vr30");
+}
+
+#[test]
+fn test_vec_vrfin(){
+    assert_asm!(0x1140620A, "vrfin vr10, vr12");
+}
+
+#[test]
+fn test_vec_vrfip(){
+    assert_asm!(0x10E08A8A, "vrfip vr7, vr17");
+}
+
+#[test]
+fn test_vec_vrfiz(){
+    assert_asm!(0x1000A24A, "vrfiz vr0, vr20");
+}
+
+#[test]
+fn test_vec_vrlb(){
+    assert_asm!(0x10EF8804, "vrlb vr7, vr15, vr17");
+}
+
+#[test]
+fn test_vec_vrlh(){
+    assert_asm!(0x12129844, "vrlh vr16, vr18, vr19");
+}
+
+#[test]
+fn test_vec_vrlw(){
+    assert_asm!(0x11540084, "vrlw vr10, vr20, vr0");
+}
+
+#[test]
+fn test_vec_vrsqrtefp(){
+    assert_asm!(0x1060794A, "vrsqrtefp vr3, vr15");
+}
+
+#[test]
+fn test_vec_vsel(){
+    assert_asm!(0x100329AA, "vsel vr0, vr3, vr5, vr6");
+}
+
+#[test]
+fn test_vec_vsl(){
+    assert_asm!(0x108CC1C4, "vsl vr4, vr12, vr24");
+}
+
+#[test]
+fn test_vec_vslb(){
+    assert_asm!(0x114E9104, "vslb vr10, vr14, vr18");
+}
+
+#[test]
+fn test_vec_vsldoi(){
+    assert_asm!(0x10601B6C, "vsldoi vr3, vr0, vr3, 13");
+}
+
+#[test]
+fn test_vec_vslh(){
+    assert_asm!(0x10AFC144, "vslh vr5, vr15, vr24");
+}
+
+#[test]
+fn test_vec_vslo(){
+    assert_asm!(0x10F1DC0C, "vslo vr7, vr17, vr27");
+}
+
+#[test]
+fn test_vec_vslw(){
+    assert_asm!(0x11128184, "vslw vr8, vr18, vr16");
+}
+
+#[test]
+fn test_vec_vspltb(){
+    assert_asm!(0x115C620C, "vspltb vr10, vr12, 0x1c");
+}
+
+#[test]
+fn test_vec_vsplth(){
+    assert_asm!(0x11947A4C, "vsplth vr12, vr15, 0x14");
+}
+
+#[test]
+fn test_vec_vspltisb(){
+    assert_asm!(0x1076030C, "vspltisb vr3, -0xa");
+}
+
+#[test]
+fn test_vec_vspltish(){
+    assert_asm!(0x11CE034C, "vspltish vr14, 0xe");
+}
+
+#[test]
+fn test_vec_vspltisw(){
+    assert_asm!(0x124C038C, "vspltisw vr18, 0xc");
+}
+
+#[test]
+fn test_vec_vspltw(){
+    assert_asm!(0x1018528C, "vspltw vr0, vr10, 0x18");
+}
+
+#[test]
+fn test_vec_vsr(){
+    assert_asm!(0x116C6AC4, "vsr vr11, vr12, vr13");
+}
+
+#[test]
+fn test_vec_vsrab(){
+    assert_asm!(0x11D09304, "vsrab vr14, vr16, vr18");
+}
+
+#[test]
+fn test_vec_vsrah(){
+    assert_asm!(0x10E8C344, "vsrah vr7, vr8, vr24");
+}
+
+#[test]
+fn test_vec_vsraw(){
+    assert_asm!(0x112CAB84, "vsraw vr9, vr12, vr21");
+}
+
+#[test]
+fn test_vec_vsrb(){
+    assert_asm!(0x1112D204, "vsrb vr8, vr18, vr26");
+}
+
+#[test]
+fn test_vec_vsrh(){
+    assert_asm!(0x114C8244, "vsrh vr10, vr12, vr16");
+}
+
+#[test]
+fn test_vec_vsro(){
+    assert_asm!(0x118F9C4C, "vsro vr12, vr15, vr19");
+}
+
+#[test]
+fn test_vec_vsrw(){
+    assert_asm!(0x100EA284, "vsrw vr0, vr14, vr20");
+}
+
+#[test]
+fn test_vec_vsubcuw(){
+    assert_asm!(0x10AF8580, "vsubcuw vr5, vr15, vr16");
+}
+
+#[test]
+fn test_vec_vsubfp(){
+    assert_asm!(0x1080584A, "vsubfp vr4, vr0, vr11");
+}
+
+#[test]
+fn test_vec_vsubsbs(){
+    assert_asm!(0x10D2BF00, "vsubsbs vr6, vr18, vr23");
+}
+
+#[test]
+fn test_vec_vsubshs(){
+    assert_asm!(0x10F16740, "vsubshs vr7, vr17, vr12");
+}
+
+#[test]
+fn test_vec_vsubsws(){
+    assert_asm!(0x118D5780, "vsubsws vr12, vr13, vr10");
+}
+
+#[test]
+fn test_vec_vsububm(){
+    assert_asm!(0x11402C00, "vsububm vr10, vr0, vr5");
+}
+
+#[test]
+fn test_vec_vsububs(){
+    assert_asm!(0x10033600, "vsububs vr0, vr3, vr6");
+}
+
+#[test]
+fn test_vec_vsubuhm(){
+    assert_asm!(0x10EB6C40, "vsubuhm vr7, vr11, vr13");
+}
+
+#[test]
+fn test_vec_vsubuhs(){
+    assert_asm!(0x110A6640, "vsubuhs vr8, vr10, vr12");
+}
+
+#[test]
+fn test_vec_vsubuwm(){
+    assert_asm!(0x112BDC80, "vsubuwm vr9, vr11, vr27");
+}
+
+#[test]
+fn test_vec_vsubuws(){
+    assert_asm!(0x1149AE80, "vsubuws vr10, vr9, vr21");
+}
+
+#[test]
+fn test_vec_vsumsws(){
+    assert_asm!(0x116C6F88, "vsumsws vr11, vr12, vr13");
+}
+
+#[test]
+fn test_vec_vsum2sws(){
+    assert_asm!(0x11909688, "vsum2sws vr12, vr16, vr18");
+}
+
+#[test]
+fn test_vec_vsum4sbs(){
+    assert_asm!(0x11B19708, "vsum4sbs vr13, vr17, vr18");
+}
+
+#[test]
+fn test_vec_vsum4shs(){
+    assert_asm!(0x1296C648, "vsum4shs vr20, vr22, vr24");
+}
+
+#[test]
+fn test_vec_vsum4ubs(){
+    assert_asm!(0x12F8CE08, "vsum4ubs vr23, vr24, vr25");
+}
+
+#[test]
+fn test_vec_vupkhpx(){
+    assert_asm!(0x10A0434E, "vupkhpx vr5, vr8");
+}
+
+#[test]
+fn test_vec_vupkhsb(){
+    assert_asm!(0x10001A0E, "vupkhsb vr0, vr3");
+}
+
+#[test]
+fn test_vec_vupkhsh(){
+    assert_asm!(0x11806A4E, "vupkhsh vr12, vr13");
+}
+
+#[test]
+fn test_vec_vupklpx(){
+    assert_asm!(0x108083CE, "vupklpx vr4, vr16");
+}
+
+#[test]
+fn test_vec_vupklsb(){
+    assert_asm!(0x11407A8E, "vupklsb vr10, vr15");
+}
+
+#[test]
+fn test_vec_vupklsh(){
+    assert_asm!(0x1180C2CE, "vupklsh vr12, vr24");
+}
+
+#[test]
+fn test_vec_vxor(){
+    assert_asm!(0x10654CC4, "vxor vr3, vr5, vr9");
+}
\ No newline at end of file
diff --git a/disasm/tests/test_vmx.rs b/disasm/tests/test_vmx.rs
new file mode 100644
index 0000000..5d61db1
--- /dev/null
+++ b/disasm/tests/test_vmx.rs
@@ -0,0 +1,401 @@
+use ppc750cl::{Argument, Ins, InsIter, Opcode, GPR};
+
+macro_rules! assert_asm {
+    ($ins:ident, $disasm:literal) => {{
+        assert_eq!(format!("{}", $ins.simplified()), $disasm)
+    }};
+    ($code:literal, $disasm:literal) => {{
+        let ins = Ins::new($code);
+        assert_eq!(format!("{}", ins.simplified()), $disasm)
+    }};
+}
+
+macro_rules! assert_basic {
+    ($ins:ident, $disasm:literal) => {{
+        assert_eq!(format!("{}", $ins.basic_form()), $disasm)
+    }};
+    ($code:literal, $disasm:literal) => {{
+        let ins = Ins::new($code);
+        assert_eq!(format!("{}", ins.basic()), $disasm)
+    }};
+}
+
+#[test]
+fn test_vmx_lvewx128(){
+    assert_asm!(0x1243388F, "lvewx128 vr114, r3, r7");
+}
+
+#[test]
+fn test_vmx_lvlx128(){
+    assert_asm!(0x1085440F, "lvlx128 vr100, r5, r8");
+}
+
+#[test]
+fn test_vmx_lvrx128(){
+    assert_asm!(0x108EE44B, "lvrx128 vr68, r14, r28");
+}
+
+#[test]
+fn test_vmx_lvlxl128(){
+    assert_asm!(0x1105FE0B, "lvlxl128 vr72, r5, r31");
+}
+
+#[test]
+fn test_vmx_lvrxl128(){
+    assert_asm!(0x12A01E4B, "lvrxl128 vr85, r0, r3");
+}
+
+#[test]
+fn test_vmx_lvsl128(){
+    assert_asm!(0x138AF00B, "lvsl128 vr92, r10, r30");
+}
+
+#[test]
+fn test_vmx_lvsr128(){
+    assert_asm!(0x1016C04F, "lvsr128 vr96, r22, r24");
+}
+
+#[test]
+fn test_vmx_lvx128(){
+    assert_asm!(0x120938CF, "lvx128 vr112, r9, r7");
+}
+
+#[test]
+fn test_vmx_lvxl128(){
+    assert_asm!(0x12C322CF, "lvxl128 vr118, r3, r4");
+}
+
+#[test]
+fn test_vmx_stvewx128(){
+    assert_asm!(0x131BF98F, "stvewx128 vr120, r27, r31");
+}
+
+#[test]
+fn test_vmx_stvlx128(){
+    assert_asm!(0x12602D0B, "stvlx128 vr83, r0, r5");
+}
+
+#[test]
+fn test_vmx_stvlxl128(){
+    assert_asm!(0x12C3A70B, "stvlxl128 vr86, r3, r20");
+}
+
+#[test]
+fn test_vmx_stvrx128(){
+    assert_asm!(0x10B8F54B, "stvrx128 vr69, r24, r30");
+}
+
+#[test]
+fn test_vmx_stvrxl128(){
+    assert_asm!(0x10C7074B, "stvrxl128 vr70, r7, r0");
+}
+
+#[test]
+fn test_vmx_stvx128(){
+    assert_asm!(0x130341C3, "stvx128 vr24, r3, r8");
+}
+
+#[test]
+fn test_vmx_stvxl128(){
+    assert_asm!(0x13E553C3, "stvxl128 vr31, r5, r10");
+}
+
+#[test]
+fn test_vmx_vaddfp128(){
+    assert_asm!(0x151E301B, "vaddfp128 vr72, vr30, vr102");
+}
+
+#[test]
+fn test_vmx_vand128(){
+    assert_asm!(0x16900E12, "vand128 vr20, vr80, vr65");
+}
+
+#[test]
+fn test_vmx_vandc128(){
+    assert_asm!(0x15EBFE52, "vandc128 vr15, vr75, vr95");
+}
+
+#[test]
+fn test_vmx_vcfpsxws128(){
+    assert_asm!(0x1A42D23B, "vcfpsxws128 vr82, vr122, 0x2");
+}
+
+#[test]
+fn test_vmx_vcfpuxws128(){
+    assert_asm!(0x1BEACA78, "vcfpuxws128 vr95, vr25, 0xa");
+}
+
+#[test]
+fn test_vmx_vcmpbfp128(){
+    assert_asm!(0x1BA5598E, "vcmpbfp128 vr125, vr5, vr75");
+    assert_asm!(0x198D79C2, "vcmpbfp128. vr12, vr13, vr79");
+}
+
+#[test]
+fn test_vmx_vcmpeqfp128(){
+    assert_asm!(0x1800D80B, "vcmpeqfp128 vr64, vr0, vr123");
+    assert_asm!(0x1ACD1C43, "vcmpeqfp128. vr22, vr77, vr99");
+}
+
+#[test]
+fn test_vmx_vcmpequw128(){
+    assert_asm!(0x18D0D60A, "vcmpequw128 vr70, vr80, vr90");
+    assert_asm!(0x18800A40, "vcmpequw128. vr4, vr0, vr1");
+}
+
+#[test]
+fn test_vmx_vcmpgefp128(){
+    assert_asm!(0x1A8A1483, "vcmpgefp128 vr20, vr74, vr98");
+    assert_asm!(0x18EB7CEF, "vcmpgefp128. vr103, vr107, vr111");
+}
+
+#[test]
+fn test_vmx_vcmpgtfp128(){
+    assert_asm!(0x1BD48102, "vcmpgtfp128 vr30, vr20, vr80");
+    assert_asm!(0x1B586D68, "vcmpgtfp128. vr90, vr120, vr13");
+}
+
+#[test]
+fn test_vmx_vcsxwfp128(){
+    assert_asm!(0x18749ABC, "vcsxwfp128 vr99, vr19, -0xc");
+}
+
+#[test]
+fn test_vmx_vcuxwfp128(){
+    assert_asm!(0x1A6D1AF8, "vcuxwfp128 vr83, vr3, 0xd");
+}
+
+#[test]
+fn test_vmx_vexptefp128(){
+    assert_asm!(0x198056B0, "vexptefp128 vr12, vr10");
+}
+
+#[test]
+fn test_vmx_vlogefp128(){
+    assert_asm!(0x1900FEFB, "vlogefp128 vr72, vr127");
+}
+
+#[test]
+fn test_vmx_vmaddcfp128(){
+    assert_asm!(0x163B1912, "vmaddcfp128 vr17, vr27, vr67");
+}
+
+#[test]
+fn test_vmx_vmaddfp128(){
+    assert_asm!(0x16B3ECFB, "vmaddfp128 vr85, vr115, vr125");
+}
+
+#[test]
+fn test_vmx_vmaxfp128(){
+    assert_asm!(0x1B274683, "vmaxfp128 vr25, vr71, vr104");
+}
+
+#[test]
+fn test_vmx_vminfp128(){
+    assert_asm!(0x1BE012C0, "vminfp128 vr31, vr0, vr2");
+}
+
+#[test]
+fn test_vmx_vmrghw128(){
+    assert_asm!(0x18CA730B, "vmrghw128 vr70, vr10, vr110");
+}
+
+#[test]
+fn test_vmx_vmrglw128(){
+    assert_asm!(0x1BD2D743, "vmrglw128 vr30, vr82, vr122");
+}
+
+#[test]
+fn test_vmx_vmsum3fp128(){
+    assert_asm!(0x14FBF993, "vmsum3fp128 vr7, vr27, vr127");
+}
+
+#[test]
+fn test_vmx_vmsum4fp128(){
+    assert_asm!(0x14A869D0, "vmsum4fp128 vr5, vr8, vr13");
+}
+
+#[test]
+fn test_vmx_vmulfp128(){
+    assert_asm!(0x1498DCBF, "vmulfp128 vr100, vr120, vr123");
+}
+
+#[test]
+fn test_vmx_vnmsubfp128(){
+    assert_asm!(0x17DBCD53, "vnmsubfp128 vr30, vr91, vr121");
+}
+
+#[test]
+fn test_vmx_vnor128(){
+    assert_asm!(0x176A6290, "vnor128 vr27, vr10, vr12");
+}
+
+#[test]
+fn test_vmx_vor128(){
+    assert_asm!(0x17EC3ADC, "vor128 vr127, vr12, vr7");
+}
+
+#[test]
+fn test_vmx_vperm128(){
+    assert_asm!(0x1661158F, "vperm128 vr115, vr65, vr98, vr6");
+}
+
+#[test]
+fn test_vmx_vpermwi128(){
+    assert_asm!(0x19C342DE, "vpermwi128 vr110, vr72, 99");
+}
+
+#[test]
+fn test_vmx_vpkd3d128(){
+    assert_asm!(0x1935DEDC, "vpkd3d128 vr105, vr27, 5, 1, 3");
+}
+
+#[test]
+fn test_vmx_vpkshss128(){
+    assert_asm!(0x16C0F62B, "vpkshss128 vr86, vr96, vr126");
+}
+
+#[test]
+fn test_vmx_vpkshus128(){
+    assert_asm!(0x153D6E48, "vpkshus128 vr73, vr93, vr13");
+}
+
+#[test]
+fn test_vmx_vpkswss128(){
+    assert_asm!(0x16FE7280, "vpkswss128 vr23, vr30, vr14");
+}
+
+#[test]
+fn test_vmx_vpkswus128(){
+    assert_asm!(0x161836C3, "vpkswus128 vr16, vr88, vr102");
+}
+
+#[test]
+fn test_vmx_vpkuhum128(){
+    assert_asm!(0x14E3BF02, "vpkuhum128 vr7, vr67, vr87");
+}
+
+#[test]
+fn test_vmx_vpkuhus128(){
+    assert_asm!(0x1600A348, "vpkuhus128 vr80, vr0, vr20");
+}
+
+#[test]
+fn test_vmx_vpkuwum128(){
+    assert_asm!(0x16EACB83, "vpkuwum128 vr23, vr10, vr121");
+}
+
+#[test]
+fn test_vmx_vpkuwus128(){
+    assert_asm!(0x17E72FC3, "vpkuwus128 vr31, vr71, vr101");
+}
+
+#[test]
+fn test_vmx_vrefp128(){
+    assert_asm!(0x1800F638, "vrefp128 vr64, vr30");
+}
+
+#[test]
+fn test_vmx_vrfim128(){
+    assert_asm!(0x18802B30, "vrfim128 vr4, vr5");
+}
+
+#[test]
+fn test_vmx_vrfin128(){
+    assert_asm!(0x1A200B73, "vrfin128 vr17, vr97");
+}
+
+#[test]
+fn test_vmx_vrfip128(){
+    assert_asm!(0x1B605BB2, "vrfip128 vr27, vr75");
+}
+
+#[test]
+fn test_vmx_vrfiz128(){
+    assert_asm!(0x1A8053F0, "vrfiz128 vr20, vr10");
+}
+
+#[test]
+fn test_vmx_vrlimi128(){
+    assert_asm!(0x18796798, "vrlimi128 vr67, vr12, 0x19, 2")
+}
+
+#[test]
+fn test_vmx_vrlw128(){
+    assert_asm!(0x1B002050, "vrlw128 vr24, vr0, vr4");
+}
+
+#[test]
+fn test_vmx_vrsqrtefp128(){
+    assert_asm!(0x19800673, "vrsqrtefp128 vr12, vr96");
+}
+
+#[test]
+fn test_vmx_vsel128(){
+    assert_asm!(0x146CDF5A, "vsel128 vr67, vr76, vr91");
+}
+
+#[test]
+fn test_vmx_vsldoi128(){
+    assert_asm!(0x130BFF30, "vsldoi128 vr24, vr107, vr31, 12");
+}
+
+#[test]
+fn test_vmx_vslo128(){
+    assert_asm!(0x14E08B90, "vslo128 vr7, vr0, vr17");
+}
+
+#[test]
+fn test_vmx_vslw128(){
+    assert_asm!(0x1A1AC0D2, "vslw128 vr16, vr26, vr88");
+}
+
+#[test]
+fn test_vmx_vspltisw128(){
+    assert_asm!(0x1B68A772, "vspltisw128 vr27, vr84, 0x8");
+}
+
+#[test]
+fn test_vmx_vspltw128(){
+    assert_asm!(0x1996EF32, "vspltw128 vr12, vr93, 0x16");
+}
+
+#[test]
+fn test_vmx_vsraw128(){
+    assert_asm!(0x19B71950, "vsraw128 vr13, vr23, vr3");
+}
+
+#[test]
+fn test_vmx_vsro128(){
+    assert_asm!(0x17C3E3D3, "vsro128 vr30, vr3, vr124");
+}
+
+#[test]
+fn test_vmx_vsrw128(){
+    assert_asm!(0x1B9271D3, "vsrw128 vr28, vr18, vr110");
+}
+
+#[test]
+fn test_vmx_vsubfp128(){
+    assert_asm!(0x17692C50, "vsubfp128 vr27, vr73, vr5");
+}
+
+#[test]
+fn test_vmx_vupkd3d128(){
+    assert_asm!(0x19FECFF0, "vupkd3d128 vr15, vr25, 0x1e");
+}
+
+#[test]
+fn test_vmx_vupkhsb128(){
+    assert_asm!(0x1B60FB83, "vupkhsb128 vr27, vr127");
+}
+
+#[test]
+fn test_vmx_vupklsb128(){
+    assert_asm!(0x1A00A3C3, "vupklsb128 vr16, vr116");
+}
+
+#[test]
+fn test_vmx_vxor128(){
+    assert_asm!(0x17E3EF32, "vxor128 vr31, vr99, vr93");
+}
\ No newline at end of file
diff --git a/isa.yaml b/isa.yaml
index 3ebb96f..c5072df 100644
--- a/isa.yaml
+++ b/isa.yaml
@@ -258,17 +258,17 @@ fields:
     arg: OpaqueU
     desc: VMX128 Permutation
     bits: 23..26,11..16
-  - name: Ximm
+  - name: D3DType
     arg: OpaqueU
-    desc: unknown immediate
+    desc: the packed data type
     bits: 11..14
-  - name: Yimm
+  - name: VMASK
     arg: OpaqueU
-    desc: unknown immediate
+    desc: the pack mask
     bits: 14..16
   - name: Zimm
     arg: OpaqueU
-    desc: unknown immediate
+    desc: amount to rotate/shift left
     bits: 24..26
 
 modifiers:
@@ -2234,6 +2234,38 @@ opcodes:
     defs: [ vD ]
     uses: [ rA.nz, rB ]
 
+  - name: lvlx
+    desc: Load Vector Left Indexed
+    bitmask: 0xfc0007ff
+    pattern: 0x7c00040e
+    args: [ vD, rA, rB ]
+    defs: [ vD ]
+    uses: [ rA.nz, rB ]
+
+  - name: lvlxl
+    desc: Load Vector Left Indexed Last
+    bitmask: 0xfc0007ff
+    pattern: 0x7c00060e
+    args: [ vD, rA, rB ]
+    defs: [ vD ]
+    uses: [ rA.nz, rB ]
+
+  - name: lvrx
+    desc: Load Vector Right Indexed
+    bitmask: 0xfc0007ff
+    pattern: 0x7c00044e
+    args: [ vD, rA, rB ]
+    defs: [ vD ]
+    uses: [ rA.nz, rB ]
+
+  - name: lvrxl
+    desc: Load Vector Right Indexed Last
+    bitmask: 0xfc0007ff
+    pattern: 0x7c00064e
+    args: [ vD, rA, rB ]
+    defs: [ vD ]
+    uses: [ rA.nz, rB ]
+
   - name: lvsl
     desc: Load Vector for Shift Left
     bitmask: 0xfc0007ff
@@ -2301,6 +2333,34 @@ opcodes:
     args: [ vS, rA, rB ]
     uses: [ rA.nz, rB ]
 
+  - name: stvlx
+    desc: Store Vector Left Indexed
+    bitmask: 0xfc0007ff
+    pattern: 0x7c00050e
+    args: [ vS, rA, rB ]
+    uses: [ rA.nz, rB ]
+
+  - name: stvlxl
+    desc: Store Vector Left Indexed Last
+    bitmask: 0xfc0007ff
+    pattern: 0x7c00070e
+    args: [ vS, rA, rB ]
+    uses: [ rA.nz, rB ]
+
+  - name: stvrx
+    desc: Store Vector Right Indexed
+    bitmask: 0xfc0007ff
+    pattern: 0x7c00054e
+    args: [ vS, rA, rB ]
+    uses: [ rA.nz, rB ]
+    
+  - name: stvrxl
+    desc: Store Vector Right Indexed Last
+    bitmask: 0xfc0007ff
+    pattern: 0x7c00074e
+    args: [ vS, rA, rB ]
+    uses: [ rA.nz, rB ]
+
   - name: stvx
     desc: Store Vector Indexed
     bitmask: 0xfc0007ff
@@ -3466,13 +3526,14 @@ opcodes:
 
 # VMX128 exclusives
 # found here: https://github.com/xenia-project/xenia/blob/master/docs/ppc/vmx128.txt
+# and here: https://github.com/kakaroto/ps3ida/blob/master/plugins/PPCAltivec/src/main.cpp
   - name: lvewx128
     desc: Load Vector128 Element Word Indexed
     bitmask: 0xfc0007f3
     pattern: 0x10000083
     args: [ VDS128, rA, rB ]
     defs: [ VDS128 ]
-    uses: [ rA, rB ]
+    uses: [ rA.nz, rB ]
 
   - name: lvlx128
     desc: Load Vector128 Left Indexed
@@ -3480,15 +3541,7 @@ opcodes:
     pattern: 0x10000403
     args: [ VDS128, rA, rB ]
     defs: [ VDS128 ]
-    uses: [ rA, rB ]
-
-  - name: lvrx128
-    desc: Load Vector128 Right Indexed
-    bitmask: 0xfc0007f3
-    pattern: 0x10000443
-    args: [ VDS128, rA, rB ]
-    defs: [ VDS128 ]
-    uses: [ rA, rB ]
+    uses: [ rA.nz, rB ]
 
   - name: lvlxl128
     desc: Load Vector128 Left Indexed LRU
@@ -3496,7 +3549,15 @@ opcodes:
     pattern: 0x10000603
     args: [ VDS128, rA, rB ]
     defs: [ VDS128 ]
-    uses: [ rA, rB ]
+    uses: [ rA.nz, rB ]
+
+  - name: lvrx128
+    desc: Load Vector128 Right Indexed
+    bitmask: 0xfc0007f3
+    pattern: 0x10000443
+    args: [ VDS128, rA, rB ]
+    defs: [ VDS128 ]
+    uses: [ rA.nz, rB ]
 
   - name: lvrxl128
     desc: Load Vector128 Right Indexed LRU
@@ -3504,7 +3565,7 @@ opcodes:
     pattern: 0x10000643
     args: [ VDS128, rA, rB ]
     defs: [ VDS128 ]
-    uses: [ rA, rB ]
+    uses: [ rA.nz, rB ]
 
   - name: lvsl128
     desc: Load Vector128 for Shift Left
@@ -3512,7 +3573,7 @@ opcodes:
     pattern: 0x10000003
     args: [ VDS128, rA, rB ]
     defs: [ VDS128 ]
-    uses: [ rA, rB ]
+    uses: [ rA.nz, rB ]
 
   - name: lvsr128
     desc: Load Vector128 for Shift Right
@@ -3520,7 +3581,7 @@ opcodes:
     pattern: 0x10000043
     args: [ VDS128, rA, rB ]
     defs: [ VDS128 ]
-    uses: [ rA, rB ]
+    uses: [ rA.nz, rB ]
 
   - name: lvx128
     desc: Load Vector128 Indexed
@@ -3528,7 +3589,7 @@ opcodes:
     pattern: 0x100000C3
     args: [ VDS128, rA, rB ]
     defs: [ VDS128 ]
-    uses: [ rA, rB ]
+    uses: [ rA.nz, rB ]
 
   - name: lvxl128
     desc: Load Vector128 Indexed LRU
@@ -3536,56 +3597,56 @@ opcodes:
     pattern: 0x100002C3
     args: [ VDS128, rA, rB ]
     defs: [ VDS128 ]
-    uses: [ rA, rB ]
+    uses: [ rA.nz, rB ]
 
   - name: stvewx128
     desc: Store Vector128 Element Word Indexed
     bitmask: 0xfc0007f3
-    pattern: 0x10000303
+    pattern: 0x10000183
     args: [ VDS128, rA, rB ]
-    uses: [ VDS128, rA, rB ]
+    uses: [ rA.nz, rB ]
 
   - name: stvlx128
     desc: Store Vector128 Left Indexed
     bitmask: 0xfc0007f3
     pattern: 0x10000503
     args: [ VDS128, rA, rB ]
-    uses: [ VDS128, rA, rB ]
+    uses: [ rA.nz, rB ]
 
   - name: stvlxl128
     desc: Store Vector128 Left Indexed LRU
     bitmask: 0xfc0007f3
     pattern: 0x10000703
     args: [ VDS128, rA, rB ]
-    uses: [ VDS128, rA, rB ]
+    uses: [ rA.nz, rB ]
 
   - name: stvrx128
     desc: Store Vector128 Right Indexed
     bitmask: 0xfc0007f3
     pattern: 0x10000543
     args: [ VDS128, rA, rB ]
-    uses: [ VDS128, rA, rB ]
+    uses: [ rA.nz, rB ]
 
   - name: stvrxl128
     desc: Store Vector128 Right Indexed LRU
     bitmask: 0xfc0007f3
     pattern: 0x10000743
     args: [ VDS128, rA, rB ]
-    uses: [ VDS128, rA, rB ]
+    uses: [ rA.nz, rB ]
 
   - name: stvx128
     desc: Store Vector128 Indexed
     bitmask: 0xfc0007f3
     pattern: 0x100001C3
     args: [ VDS128, rA, rB ]
-    uses: [ VDS128, rA, rB ]
+    uses: [ rA.nz, rB ]
 
   - name: stvxl128
     desc: Store Vector128 Indexed LRU
     bitmask: 0xfc0007f3
     pattern: 0x100003C3
     args: [ VDS128, rA, rB ]
-    uses: [ VDS128, rA, rB ]
+    uses: [ rA.nz, rB ]
 
   - name: vaddfp128
     desc: Vector128 Add Floating Point
@@ -3606,7 +3667,7 @@ opcodes:
   - name: vandc128
     desc: Vector128 Logical AND with Complement
     bitmask: 0xfc0003d0
-    pattern: 0x14000290
+    pattern: 0x14000250
     args: [ VDS128, VA128, VB128 ]
     defs: [ VDS128 ]
     uses: [ VA128, VB128 ]
@@ -3820,9 +3881,9 @@ opcodes:
     desc: Vector128 Pack D3Dtype, Rotate Left Immediate and Mask Insert
     bitmask: 0xfc000730
     pattern: 0x18000610
-    args: [ VDS128, VB128, Ximm, Yimm, Zimm ]
+    args: [ VDS128, VB128, D3DType, VMASK, Zimm ]
     defs: [ VDS128 ]
-    uses: [ VB128, Ximm, Yimm, Zimm ]
+    uses: [ VB128, D3DType, VMASK, Zimm ]
 
   - name: vpkshss128
     desc: Vector128 Pack Signed Half Word Signed Saturate
@@ -3939,7 +4000,7 @@ opcodes:
   - name: vrlw128
     desc: Vector128 Rotate Left Word
     bitmask: 0xfc0003d0
-    pattern: 0x14000050
+    pattern: 0x18000050
     args: [ VDS128, VA128, VB128 ]
     defs: [ VDS128 ]
     uses: [ VA128, VB128 ]
@@ -4011,7 +4072,7 @@ opcodes:
   - name: vsro128
     desc: Vector128 Shift Right Octet
     bitmask: 0xfc0003d0
-    pattern: 0x180003d0
+    pattern: 0x140003d0
     args: [ VDS128, VA128, VB128 ]
     defs: [ VDS128 ]
     uses: [ VA128, VB128 ]
@@ -4036,9 +4097,9 @@ opcodes:
     desc: Vector128 Unpack D3Dtype
     bitmask: 0xfc0007f0
     pattern: 0x180007f0
-    args: [ VDS128, vuimm, VB128 ]
+    args: [ VDS128, VB128, vuimm ]
     defs: [ VDS128 ]
-    uses: [ vuimm, VB128 ]
+    uses: [ VB128, vuimm ]
 
   - name: vupkhsb128
     desc: Vector128 Unpack High Signed Byte
@@ -4738,7 +4799,7 @@ mnemonics:
     condition: ds_A == 0
   - name: dssall
     opcode: dss
-    condition: ds_A == 1 && STRM == 0
+    condition: ds_A == 1
   - name: vnot
     opcode: vnor
     args: [ vD, vA ]
@@ -4747,3 +4808,16 @@ mnemonics:
     opcode: vor
     args: [ vD, vA ]
     condition: vB == vA
+
+# missing instructions (there seem to be no documentation on these anywhere)
+# vctsxs128
+# vcfpsxws
+# vctuxs128
+# vcfpuxws
+# vcsxwfp
+# vcfux128
+# vcuxwfp
+# vdot3fp
+# vdot4fp
+# vupkhsh128
+# vupklsh128
\ No newline at end of file