diff --git a/disasm/src/generated.rs b/disasm/src/generated.rs
index 4006744..5becd08 100644
--- a/disasm/src/generated.rs
+++ b/disasm/src/generated.rs
@@ -2075,7 +2075,6 @@ impl Ins {
             ],
             Opcode::PsMr => vec![
                 Field::frD(FPR(((self.code >> 21u8) & 0x1f) as _)),
-                Field::frA(FPR(((self.code >> 16u8) & 0x1f) as _)),
                 Field::frB(FPR(((self.code >> 11u8) & 0x1f) as _)),
             ],
             Opcode::PsMsub => vec![
diff --git a/disasm/tests/test_disasm.rs b/disasm/tests/test_disasm.rs
index 02dc22c..e0df349 100644
--- a/disasm/tests/test_disasm.rs
+++ b/disasm/tests/test_disasm.rs
@@ -709,6 +709,11 @@ fn test_ins_ps_merge11() {
     assert_asm!(0x10AA14E0, "ps_merge11 f5, f10, f2");
 }
 
+#[test]
+fn test_ins_ps_mr() {
+    assert_asm!(0x10200090, "ps_mr f1, f0");
+}
+
 #[test]
 fn test_ins_ps_msub() {
     assert_asm!(0x10A53778, "ps_msub f5, f5, f29, f6");
diff --git a/isa.yaml b/isa.yaml
index 00a459c..c39f470 100644
--- a/isa.yaml
+++ b/isa.yaml
@@ -1450,7 +1450,7 @@ opcodes:
     desc: Paired Single Move Register
     bitmask: 0xfc1f07fe
     pattern: 0x10000090
-    args: [ frD, frA, frB ]
+    args: [ frD, frB ]
     defs: [ frD ]
     uses: [ frB ]