mirror of https://github.com/PrimeDecomp/prime.git
121 lines
5.3 KiB
ArmAsm
121 lines
5.3 KiB
ArmAsm
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.include "macros.inc"
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.section .text, "ax"
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.global nextafter
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nextafter:
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/* 80394958 003918B8 94 21 FF E0 */ stwu r1, -0x20(r1)
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/* 8039495C 003918BC 3C 00 7F F0 */ lis r0, 0x7ff0
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/* 80394960 003918C0 D8 21 00 08 */ stfd f1, 8(r1)
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/* 80394964 003918C4 80 81 00 08 */ lwz r4, 8(r1)
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/* 80394968 003918C8 D8 41 00 10 */ stfd f2, 0x10(r1)
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/* 8039496C 003918CC 54 85 00 7E */ clrlwi r5, r4, 1
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/* 80394970 003918D0 80 E1 00 0C */ lwz r7, 0xc(r1)
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/* 80394974 003918D4 80 61 00 10 */ lwz r3, 0x10(r1)
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/* 80394978 003918D8 7C 05 00 00 */ cmpw r5, r0
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/* 8039497C 003918DC 81 01 00 14 */ lwz r8, 0x14(r1)
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/* 80394980 003918E0 54 66 00 7E */ clrlwi r6, r3, 1
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/* 80394984 003918E4 41 80 00 10 */ blt lbl_80394994
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/* 80394988 003918E8 3C 05 80 10 */ addis r0, r5, 0x8010
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/* 8039498C 003918EC 7C 00 3B 79 */ or. r0, r0, r7
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/* 80394990 003918F0 40 82 00 1C */ bne lbl_803949AC
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lbl_80394994:
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/* 80394994 003918F4 3C 00 7F F0 */ lis r0, 0x7ff0
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/* 80394998 003918F8 7C 06 00 00 */ cmpw r6, r0
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/* 8039499C 003918FC 41 80 00 20 */ blt lbl_803949BC
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/* 803949A0 00391900 3C 06 80 10 */ addis r0, r6, 0x8010
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/* 803949A4 00391904 7C 00 43 79 */ or. r0, r0, r8
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/* 803949A8 00391908 41 82 00 14 */ beq lbl_803949BC
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lbl_803949AC:
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/* 803949AC 0039190C C8 21 00 08 */ lfd f1, 8(r1)
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/* 803949B0 00391910 C8 01 00 10 */ lfd f0, 0x10(r1)
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/* 803949B4 00391914 FC 21 00 2A */ fadd f1, f1, f0
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/* 803949B8 00391918 48 00 01 1C */ b lbl_80394AD4
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lbl_803949BC:
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/* 803949BC 0039191C C8 21 00 08 */ lfd f1, 8(r1)
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/* 803949C0 00391920 C8 01 00 10 */ lfd f0, 0x10(r1)
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/* 803949C4 00391924 FC 01 00 00 */ fcmpu cr0, f1, f0
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/* 803949C8 00391928 40 82 00 08 */ bne lbl_803949D0
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/* 803949CC 0039192C 48 00 01 08 */ b lbl_80394AD4
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lbl_803949D0:
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/* 803949D0 00391930 7C A0 3B 79 */ or. r0, r5, r7
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/* 803949D4 00391934 40 82 00 34 */ bne lbl_80394A08
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/* 803949D8 00391938 54 63 00 00 */ rlwinm r3, r3, 0, 0, 0
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/* 803949DC 0039193C 38 00 00 01 */ li r0, 1
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/* 803949E0 00391940 90 61 00 08 */ stw r3, 8(r1)
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/* 803949E4 00391944 90 01 00 0C */ stw r0, 0xc(r1)
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/* 803949E8 00391948 C8 01 00 08 */ lfd f0, 8(r1)
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/* 803949EC 0039194C FC 20 00 32 */ fmul f1, f0, f0
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/* 803949F0 00391950 FC 01 00 00 */ fcmpu cr0, f1, f0
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/* 803949F4 00391954 D8 21 00 10 */ stfd f1, 0x10(r1)
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/* 803949F8 00391958 40 82 00 08 */ bne lbl_80394A00
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/* 803949FC 0039195C 48 00 00 D8 */ b lbl_80394AD4
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lbl_80394A00:
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/* 80394A00 00391960 FC 20 00 90 */ fmr f1, f0
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/* 80394A04 00391964 48 00 00 D0 */ b lbl_80394AD4
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lbl_80394A08:
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/* 80394A08 00391968 2C 04 00 00 */ cmpwi r4, 0
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/* 80394A0C 0039196C 41 80 00 3C */ blt lbl_80394A48
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/* 80394A10 00391970 7C 04 18 00 */ cmpw r4, r3
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/* 80394A14 00391974 41 81 00 10 */ bgt lbl_80394A24
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/* 80394A18 00391978 40 82 00 20 */ bne lbl_80394A38
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/* 80394A1C 0039197C 7C 07 40 40 */ cmplw r7, r8
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/* 80394A20 00391980 40 81 00 18 */ ble lbl_80394A38
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lbl_80394A24:
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/* 80394A24 00391984 28 07 00 00 */ cmplwi r7, 0
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/* 80394A28 00391988 40 82 00 08 */ bne lbl_80394A30
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/* 80394A2C 0039198C 38 84 FF FF */ addi r4, r4, -1
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lbl_80394A30:
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/* 80394A30 00391990 38 E7 FF FF */ addi r7, r7, -1
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/* 80394A34 00391994 48 00 00 50 */ b lbl_80394A84
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lbl_80394A38:
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/* 80394A38 00391998 34 E7 00 01 */ addic. r7, r7, 1
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/* 80394A3C 0039199C 40 82 00 48 */ bne lbl_80394A84
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/* 80394A40 003919A0 38 84 00 01 */ addi r4, r4, 1
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/* 80394A44 003919A4 48 00 00 40 */ b lbl_80394A84
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lbl_80394A48:
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/* 80394A48 003919A8 2C 03 00 00 */ cmpwi r3, 0
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/* 80394A4C 003919AC 40 80 00 18 */ bge lbl_80394A64
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/* 80394A50 003919B0 7C 04 18 00 */ cmpw r4, r3
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/* 80394A54 003919B4 41 81 00 10 */ bgt lbl_80394A64
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/* 80394A58 003919B8 40 82 00 20 */ bne lbl_80394A78
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/* 80394A5C 003919BC 7C 07 40 40 */ cmplw r7, r8
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/* 80394A60 003919C0 40 81 00 18 */ ble lbl_80394A78
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lbl_80394A64:
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/* 80394A64 003919C4 28 07 00 00 */ cmplwi r7, 0
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/* 80394A68 003919C8 40 82 00 08 */ bne lbl_80394A70
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/* 80394A6C 003919CC 38 84 FF FF */ addi r4, r4, -1
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lbl_80394A70:
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/* 80394A70 003919D0 38 E7 FF FF */ addi r7, r7, -1
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/* 80394A74 003919D4 48 00 00 10 */ b lbl_80394A84
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lbl_80394A78:
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/* 80394A78 003919D8 34 E7 00 01 */ addic. r7, r7, 1
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/* 80394A7C 003919DC 40 82 00 08 */ bne lbl_80394A84
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/* 80394A80 003919E0 38 84 00 01 */ addi r4, r4, 1
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lbl_80394A84:
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/* 80394A84 003919E4 54 83 00 56 */ rlwinm r3, r4, 0, 1, 0xb
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/* 80394A88 003919E8 3C 00 7F F0 */ lis r0, 0x7ff0
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/* 80394A8C 003919EC 7C 03 00 00 */ cmpw r3, r0
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/* 80394A90 003919F0 41 80 00 0C */ blt lbl_80394A9C
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/* 80394A94 003919F4 FC 21 08 2A */ fadd f1, f1, f1
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/* 80394A98 003919F8 48 00 00 3C */ b lbl_80394AD4
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lbl_80394A9C:
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/* 80394A9C 003919FC 3C 00 00 10 */ lis r0, 0x10
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/* 80394AA0 00391A00 7C 03 00 00 */ cmpw r3, r0
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/* 80394AA4 00391A04 40 80 00 24 */ bge lbl_80394AC8
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/* 80394AA8 00391A08 FC 01 00 72 */ fmul f0, f1, f1
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/* 80394AAC 00391A0C FC 00 08 00 */ fcmpu cr0, f0, f1
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/* 80394AB0 00391A10 D8 01 00 10 */ stfd f0, 0x10(r1)
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/* 80394AB4 00391A14 41 82 00 14 */ beq lbl_80394AC8
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/* 80394AB8 00391A18 90 81 00 10 */ stw r4, 0x10(r1)
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/* 80394ABC 00391A1C 90 E1 00 14 */ stw r7, 0x14(r1)
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/* 80394AC0 00391A20 C8 21 00 10 */ lfd f1, 0x10(r1)
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/* 80394AC4 00391A24 48 00 00 10 */ b lbl_80394AD4
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lbl_80394AC8:
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/* 80394AC8 00391A28 90 81 00 08 */ stw r4, 8(r1)
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/* 80394ACC 00391A2C 90 E1 00 0C */ stw r7, 0xc(r1)
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/* 80394AD0 00391A30 C8 21 00 08 */ lfd f1, 8(r1)
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lbl_80394AD4:
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/* 80394AD4 00391A34 38 21 00 20 */ addi r1, r1, 0x20
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/* 80394AD8 00391A38 4E 80 00 20 */ blr
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