mirror of https://github.com/PrimeDecomp/prime.git
90 lines
3.8 KiB
ArmAsm
90 lines
3.8 KiB
ArmAsm
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.include "macros.inc"
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.section .text, "ax" # 0x80003640 - 0x803CB1C0
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.global __dv__FRC9CVector2ii
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__dv__FRC9CVector2ii:
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/* 8031424C 003111AC 94 21 FF F0 */ stwu r1, -0x10(r1)
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/* 80314250 003111B0 7C 08 02 A6 */ mflr r0
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/* 80314254 003111B4 90 01 00 14 */ stw r0, 0x14(r1)
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/* 80314258 003111B8 80 C4 00 00 */ lwz r6, 0(r4)
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/* 8031425C 003111BC 80 04 00 04 */ lwz r0, 4(r4)
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/* 80314260 003111C0 7C 86 2B D6 */ divw r4, r6, r5
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/* 80314264 003111C4 7C A0 2B D6 */ divw r5, r0, r5
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/* 80314268 003111C8 48 00 00 E5 */ bl __ct__9CVector2iFii
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/* 8031426C 003111CC 80 01 00 14 */ lwz r0, 0x14(r1)
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/* 80314270 003111D0 7C 08 03 A6 */ mtlr r0
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/* 80314274 003111D4 38 21 00 10 */ addi r1, r1, 0x10
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/* 80314278 003111D8 4E 80 00 20 */ blr
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.global __ml__FRC9CVector2ii
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__ml__FRC9CVector2ii:
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/* 8031427C 003111DC 94 21 FF F0 */ stwu r1, -0x10(r1)
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/* 80314280 003111E0 7C 08 02 A6 */ mflr r0
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/* 80314284 003111E4 90 01 00 14 */ stw r0, 0x14(r1)
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/* 80314288 003111E8 80 C4 00 00 */ lwz r6, 0(r4)
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/* 8031428C 003111EC 80 04 00 04 */ lwz r0, 4(r4)
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/* 80314290 003111F0 7C 85 31 D6 */ mullw r4, r5, r6
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/* 80314294 003111F4 7C A5 01 D6 */ mullw r5, r5, r0
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/* 80314298 003111F8 48 00 00 B5 */ bl __ct__9CVector2iFii
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/* 8031429C 003111FC 80 01 00 14 */ lwz r0, 0x14(r1)
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/* 803142A0 00311200 7C 08 03 A6 */ mtlr r0
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/* 803142A4 00311204 38 21 00 10 */ addi r1, r1, 0x10
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/* 803142A8 00311208 4E 80 00 20 */ blr
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.global __eq__FRC9CVector2iRC9CVector2i
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__eq__FRC9CVector2iRC9CVector2i:
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/* 803142AC 0031120C 80 A3 00 00 */ lwz r5, 0(r3)
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/* 803142B0 00311210 38 C0 00 00 */ li r6, 0
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/* 803142B4 00311214 80 04 00 00 */ lwz r0, 0(r4)
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/* 803142B8 00311218 7C 05 00 00 */ cmpw r5, r0
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/* 803142BC 0031121C 40 82 00 18 */ bne lbl_803142D4
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/* 803142C0 00311220 80 63 00 04 */ lwz r3, 4(r3)
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/* 803142C4 00311224 80 04 00 04 */ lwz r0, 4(r4)
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/* 803142C8 00311228 7C 03 00 00 */ cmpw r3, r0
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/* 803142CC 0031122C 40 82 00 08 */ bne lbl_803142D4
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/* 803142D0 00311230 38 C0 00 01 */ li r6, 1
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lbl_803142D4:
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/* 803142D4 00311234 7C C3 33 78 */ mr r3, r6
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/* 803142D8 00311238 4E 80 00 20 */ blr
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.global __mi__FRC9CVector2iRC9CVector2i
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__mi__FRC9CVector2iRC9CVector2i:
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/* 803142DC 0031123C 94 21 FF F0 */ stwu r1, -0x10(r1)
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/* 803142E0 00311240 7C 08 02 A6 */ mflr r0
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/* 803142E4 00311244 90 01 00 14 */ stw r0, 0x14(r1)
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/* 803142E8 00311248 80 E5 00 00 */ lwz r7, 0(r5)
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/* 803142EC 0031124C 80 C4 00 00 */ lwz r6, 0(r4)
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/* 803142F0 00311250 80 04 00 04 */ lwz r0, 4(r4)
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/* 803142F4 00311254 80 A5 00 04 */ lwz r5, 4(r5)
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/* 803142F8 00311258 7C 87 30 50 */ subf r4, r7, r6
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/* 803142FC 0031125C 7C A5 00 50 */ subf r5, r5, r0
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/* 80314300 00311260 48 00 00 4D */ bl __ct__9CVector2iFii
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/* 80314304 00311264 80 01 00 14 */ lwz r0, 0x14(r1)
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/* 80314308 00311268 7C 08 03 A6 */ mtlr r0
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/* 8031430C 0031126C 38 21 00 10 */ addi r1, r1, 0x10
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/* 80314310 00311270 4E 80 00 20 */ blr
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.global __pl__FRC9CVector2iRC9CVector2i
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__pl__FRC9CVector2iRC9CVector2i:
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/* 80314314 00311274 94 21 FF F0 */ stwu r1, -0x10(r1)
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/* 80314318 00311278 7C 08 02 A6 */ mflr r0
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/* 8031431C 0031127C 90 01 00 14 */ stw r0, 0x14(r1)
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/* 80314320 00311280 80 E5 00 00 */ lwz r7, 0(r5)
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/* 80314324 00311284 81 04 00 00 */ lwz r8, 0(r4)
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/* 80314328 00311288 80 C4 00 04 */ lwz r6, 4(r4)
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/* 8031432C 0031128C 80 05 00 04 */ lwz r0, 4(r5)
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/* 80314330 00311290 7C 88 3A 14 */ add r4, r8, r7
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/* 80314334 00311294 7C A6 02 14 */ add r5, r6, r0
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/* 80314338 00311298 48 00 00 15 */ bl __ct__9CVector2iFii
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/* 8031433C 0031129C 80 01 00 14 */ lwz r0, 0x14(r1)
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/* 80314340 003112A0 7C 08 03 A6 */ mtlr r0
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/* 80314344 003112A4 38 21 00 10 */ addi r1, r1, 0x10
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/* 80314348 003112A8 4E 80 00 20 */ blr
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.global __ct__9CVector2iFii
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__ct__9CVector2iFii:
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/* 8031434C 003112AC 90 83 00 00 */ stw r4, 0(r3)
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/* 80314350 003112B0 90 A3 00 04 */ stw r5, 4(r3)
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/* 80314354 003112B4 4E 80 00 20 */ blr
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