mirror of https://github.com/PrimeDecomp/prime.git
71 lines
2.8 KiB
ArmAsm
71 lines
2.8 KiB
ArmAsm
.include "macros.inc"
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.section .sbss
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.balign 8
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.global lbl_805A99D8
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lbl_805A99D8:
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.skip 0x8
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.section .text, "ax"
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.global __close_console
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__close_console:
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/* 80391274 0038E1D4 38 60 00 00 */ li r3, 0
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/* 80391278 0038E1D8 4E 80 00 20 */ blr
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.global __write_console
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__write_console:
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/* 8039127C 0038E1DC 94 21 FF E0 */ stwu r1, -0x20(r1)
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/* 80391280 0038E1E0 7C 08 02 A6 */ mflr r0
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/* 80391284 0038E1E4 90 01 00 24 */ stw r0, 0x24(r1)
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/* 80391288 0038E1E8 93 E1 00 1C */ stw r31, 0x1c(r1)
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/* 8039128C 0038E1EC 7C DF 33 78 */ mr r31, r6
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/* 80391290 0038E1F0 93 C1 00 18 */ stw r30, 0x18(r1)
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/* 80391294 0038E1F4 7C BE 2B 78 */ mr r30, r5
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/* 80391298 0038E1F8 93 A1 00 14 */ stw r29, 0x14(r1)
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/* 8039129C 0038E1FC 7C 9D 23 78 */ mr r29, r4
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/* 803912A0 0038E200 93 81 00 10 */ stw r28, 0x10(r1)
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/* 803912A4 0038E204 7C 7C 1B 78 */ mr r28, r3
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/* 803912A8 0038E208 38 60 00 00 */ li r3, 0
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/* 803912AC 0038E20C 80 0D AE 18 */ lwz r0, lbl_805A99D8@sda21(r13)
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/* 803912B0 0038E210 2C 00 00 00 */ cmpwi r0, 0
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/* 803912B4 0038E214 40 82 00 20 */ bne lbl_803912D4
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/* 803912B8 0038E218 3C 60 00 01 */ lis r3, 0x0000E100@ha
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/* 803912BC 0038E21C 38 63 E1 00 */ addi r3, r3, 0x0000E100@l
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/* 803912C0 0038E220 48 03 06 31 */ bl InitializeUART
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/* 803912C4 0038E224 2C 03 00 00 */ cmpwi r3, 0
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/* 803912C8 0038E228 40 82 00 0C */ bne lbl_803912D4
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/* 803912CC 0038E22C 38 00 00 01 */ li r0, 1
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/* 803912D0 0038E230 90 0D AE 18 */ stw r0, lbl_805A99D8@sda21(r13)
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lbl_803912D4:
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/* 803912D4 0038E234 2C 03 00 00 */ cmpwi r3, 0
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/* 803912D8 0038E238 41 82 00 0C */ beq lbl_803912E4
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/* 803912DC 0038E23C 38 60 00 01 */ li r3, 1
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/* 803912E0 0038E240 48 00 00 40 */ b lbl_80391320
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lbl_803912E4:
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/* 803912E4 0038E244 80 9E 00 00 */ lwz r4, 0(r30)
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/* 803912E8 0038E248 7F A3 EB 78 */ mr r3, r29
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/* 803912EC 0038E24C 48 03 06 75 */ bl WriteUARTN
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/* 803912F0 0038E250 2C 03 00 00 */ cmpwi r3, 0
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/* 803912F4 0038E254 41 82 00 14 */ beq lbl_80391308
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/* 803912F8 0038E258 38 00 00 00 */ li r0, 0
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/* 803912FC 0038E25C 38 60 00 01 */ li r3, 1
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/* 80391300 0038E260 90 1E 00 00 */ stw r0, 0(r30)
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/* 80391304 0038E264 48 00 00 1C */ b lbl_80391320
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lbl_80391308:
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/* 80391308 0038E268 7F 83 E3 78 */ mr r3, r28
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/* 8039130C 0038E26C 7F A4 EB 78 */ mr r4, r29
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/* 80391310 0038E270 7F C5 F3 78 */ mr r5, r30
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/* 80391314 0038E274 7F E6 FB 78 */ mr r6, r31
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/* 80391318 0038E278 4B C7 23 39 */ bl __TRK_write_console
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/* 8039131C 0038E27C 38 60 00 00 */ li r3, 0
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lbl_80391320:
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/* 80391320 0038E280 80 01 00 24 */ lwz r0, 0x24(r1)
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/* 80391324 0038E284 83 E1 00 1C */ lwz r31, 0x1c(r1)
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/* 80391328 0038E288 83 C1 00 18 */ lwz r30, 0x18(r1)
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/* 8039132C 0038E28C 83 A1 00 14 */ lwz r29, 0x14(r1)
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/* 80391330 0038E290 83 81 00 10 */ lwz r28, 0x10(r1)
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/* 80391334 0038E294 7C 08 03 A6 */ mtlr r0
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/* 80391338 0038E298 38 21 00 20 */ addi r1, r1, 0x20
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/* 8039133C 0038E29C 4E 80 00 20 */ blr
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