mirror of https://github.com/PrimeDecomp/prime.git
105 lines
4.3 KiB
ArmAsm
105 lines
4.3 KiB
ArmAsm
.include "macros.inc"
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.section .init, "ax" # 0x80003100 - 0x80005620
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.global memset
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memset:
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/* 800033A8 000003A8 94 21 FF F0 */ stwu r1, -0x10(r1)
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/* 800033AC 000003AC 7C 08 02 A6 */ mflr r0
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/* 800033B0 000003B0 90 01 00 14 */ stw r0, 0x14(r1)
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/* 800033B4 000003B4 93 E1 00 0C */ stw r31, 0xc(r1)
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/* 800033B8 000003B8 7C 7F 1B 78 */ mr r31, r3
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/* 800033BC 000003BC 48 00 00 1D */ bl __fill_mem
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/* 800033C0 000003C0 80 01 00 14 */ lwz r0, 0x14(r1)
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/* 800033C4 000003C4 7F E3 FB 78 */ mr r3, r31
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/* 800033C8 000003C8 83 E1 00 0C */ lwz r31, 0xc(r1)
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/* 800033CC 000003CC 7C 08 03 A6 */ mtlr r0
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/* 800033D0 000003D0 38 21 00 10 */ addi r1, r1, 0x10
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/* 800033D4 000003D4 4E 80 00 20 */ blr
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.global __fill_mem
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__fill_mem:
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/* 800033D8 000003D8 28 05 00 20 */ cmplwi r5, 0x20
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/* 800033DC 000003DC 54 84 06 3E */ clrlwi r4, r4, 0x18
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/* 800033E0 000003E0 38 C3 FF FF */ addi r6, r3, -1
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/* 800033E4 000003E4 7C 87 23 78 */ mr r7, r4
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/* 800033E8 000003E8 41 80 00 90 */ blt lbl_80003478
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/* 800033EC 000003EC 7C C0 30 F8 */ nor r0, r6, r6
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/* 800033F0 000003F0 54 03 07 BF */ clrlwi. r3, r0, 0x1e
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/* 800033F4 000003F4 41 82 00 14 */ beq lbl_80003408
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/* 800033F8 000003F8 7C A3 28 50 */ subf r5, r3, r5
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lbl_800033FC:
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/* 800033FC 000003FC 34 63 FF FF */ addic. r3, r3, -1
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/* 80003400 00000400 9C E6 00 01 */ stbu r7, 1(r6)
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/* 80003404 00000404 40 82 FF F8 */ bne lbl_800033FC
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lbl_80003408:
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/* 80003408 00000408 28 07 00 00 */ cmplwi r7, 0
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/* 8000340C 0000040C 41 82 00 1C */ beq lbl_80003428
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/* 80003410 00000410 54 E3 C0 0E */ slwi r3, r7, 0x18
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/* 80003414 00000414 54 E0 80 1E */ slwi r0, r7, 0x10
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/* 80003418 00000418 54 E4 40 2E */ slwi r4, r7, 8
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/* 8000341C 0000041C 7C 60 03 78 */ or r0, r3, r0
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/* 80003420 00000420 7C 80 03 78 */ or r0, r4, r0
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/* 80003424 00000424 7C E7 03 78 */ or r7, r7, r0
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lbl_80003428:
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/* 80003428 00000428 54 A3 D9 7F */ rlwinm. r3, r5, 0x1b, 5, 0x1f
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/* 8000342C 0000042C 38 86 FF FD */ addi r4, r6, -3
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/* 80003430 00000430 41 82 00 2C */ beq lbl_8000345C
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lbl_80003434:
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/* 80003434 00000434 90 E4 00 04 */ stw r7, 4(r4)
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/* 80003438 00000438 34 63 FF FF */ addic. r3, r3, -1
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/* 8000343C 0000043C 90 E4 00 08 */ stw r7, 8(r4)
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/* 80003440 00000440 90 E4 00 0C */ stw r7, 0xc(r4)
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/* 80003444 00000444 90 E4 00 10 */ stw r7, 0x10(r4)
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/* 80003448 00000448 90 E4 00 14 */ stw r7, 0x14(r4)
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/* 8000344C 0000044C 90 E4 00 18 */ stw r7, 0x18(r4)
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/* 80003450 00000450 90 E4 00 1C */ stw r7, 0x1c(r4)
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/* 80003454 00000454 94 E4 00 20 */ stwu r7, 0x20(r4)
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/* 80003458 00000458 40 82 FF DC */ bne lbl_80003434
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lbl_8000345C:
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/* 8000345C 0000045C 54 A3 F7 7F */ rlwinm. r3, r5, 0x1e, 0x1d, 0x1f
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/* 80003460 00000460 41 82 00 10 */ beq lbl_80003470
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lbl_80003464:
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/* 80003464 00000464 34 63 FF FF */ addic. r3, r3, -1
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/* 80003468 00000468 94 E4 00 04 */ stwu r7, 4(r4)
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/* 8000346C 0000046C 40 82 FF F8 */ bne lbl_80003464
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lbl_80003470:
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/* 80003470 00000470 38 C4 00 03 */ addi r6, r4, 3
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/* 80003474 00000474 54 A5 07 BE */ clrlwi r5, r5, 0x1e
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lbl_80003478:
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/* 80003478 00000478 28 05 00 00 */ cmplwi r5, 0
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/* 8000347C 0000047C 4D 82 00 20 */ beqlr
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lbl_80003480:
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/* 80003480 00000480 34 A5 FF FF */ addic. r5, r5, -1
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/* 80003484 00000484 9C E6 00 01 */ stbu r7, 1(r6)
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/* 80003488 00000488 40 82 FF F8 */ bne lbl_80003480
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/* 8000348C 0000048C 4E 80 00 20 */ blr
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.global memcpy
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memcpy:
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/* 80003490 00000490 7C 04 18 40 */ cmplw r4, r3
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/* 80003494 00000494 41 80 00 28 */ blt lbl_800034BC
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/* 80003498 00000498 38 84 FF FF */ addi r4, r4, -1
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/* 8000349C 0000049C 38 C3 FF FF */ addi r6, r3, -1
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/* 800034A0 000004A0 38 A5 00 01 */ addi r5, r5, 1
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/* 800034A4 000004A4 48 00 00 0C */ b lbl_800034B0
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lbl_800034A8:
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/* 800034A8 000004A8 8C 04 00 01 */ lbzu r0, 1(r4)
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/* 800034AC 000004AC 9C 06 00 01 */ stbu r0, 1(r6)
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lbl_800034B0:
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/* 800034B0 000004B0 34 A5 FF FF */ addic. r5, r5, -1
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/* 800034B4 000004B4 40 82 FF F4 */ bne lbl_800034A8
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/* 800034B8 000004B8 4E 80 00 20 */ blr
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lbl_800034BC:
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/* 800034BC 000004BC 7C 84 2A 14 */ add r4, r4, r5
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/* 800034C0 000004C0 7C C3 2A 14 */ add r6, r3, r5
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/* 800034C4 000004C4 38 A5 00 01 */ addi r5, r5, 1
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/* 800034C8 000004C8 48 00 00 0C */ b lbl_800034D4
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lbl_800034CC:
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/* 800034CC 000004CC 8C 04 FF FF */ lbzu r0, -1(r4)
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/* 800034D0 000004D0 9C 06 FF FF */ stbu r0, -1(r6)
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lbl_800034D4:
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/* 800034D4 000004D4 34 A5 FF FF */ addic. r5, r5, -1
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/* 800034D8 000004D8 40 82 FF F4 */ bne lbl_800034CC
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/* 800034DC 000004DC 4E 80 00 20 */ blr
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