mirror of https://github.com/PrimeDecomp/prime.git
53 lines
2.1 KiB
ArmAsm
53 lines
2.1 KiB
ArmAsm
.include "macros.inc"
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.section .data
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.balign 8
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.global __vt__16CArchMsgParmNull
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__vt__16CArchMsgParmNull:
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# ROM: 0x3D6E70
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.4byte 0
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.4byte 0
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.4byte __dt__16CArchMsgParmNullFv
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.4byte 0
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.section .text, "ax"
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.global __dt__16CArchMsgParmNullFv
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__dt__16CArchMsgParmNullFv:
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/* 800516C8 0004E628 94 21 FF F0 */ stwu r1, -0x10(r1)
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/* 800516CC 0004E62C 7C 08 02 A6 */ mflr r0
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/* 800516D0 0004E630 90 01 00 14 */ stw r0, 0x14(r1)
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/* 800516D4 0004E634 93 E1 00 0C */ stw r31, 0xc(r1)
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/* 800516D8 0004E638 7C 7F 1B 79 */ or. r31, r3, r3
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/* 800516DC 0004E63C 41 82 00 30 */ beq lbl_8005170C
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/* 800516E0 0004E640 3C 60 80 3E */ lis r3, __vt__16CArchMsgParmNull@ha
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/* 800516E4 0004E644 38 03 9E 70 */ addi r0, r3, __vt__16CArchMsgParmNull@l
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/* 800516E8 0004E648 90 1F 00 00 */ stw r0, 0(r31)
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/* 800516EC 0004E64C 41 82 00 10 */ beq lbl_800516FC
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/* 800516F0 0004E650 3C 60 80 3E */ lis r3, __vt__24IArchitectureMessageParm@ha
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/* 800516F4 0004E654 38 03 8E 9C */ addi r0, r3, __vt__24IArchitectureMessageParm@l
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/* 800516F8 0004E658 90 1F 00 00 */ stw r0, 0(r31)
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lbl_800516FC:
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/* 800516FC 0004E65C 7C 80 07 35 */ extsh. r0, r4
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/* 80051700 0004E660 40 81 00 0C */ ble lbl_8005170C
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/* 80051704 0004E664 7F E3 FB 78 */ mr r3, r31
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/* 80051708 0004E668 48 2C 42 29 */ bl Free__7CMemoryFPCv
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lbl_8005170C:
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/* 8005170C 0004E66C 80 01 00 14 */ lwz r0, 0x14(r1)
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/* 80051710 0004E670 7F E3 FB 78 */ mr r3, r31
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/* 80051714 0004E674 83 E1 00 0C */ lwz r31, 0xc(r1)
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/* 80051718 0004E678 7C 08 03 A6 */ mtlr r0
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/* 8005171C 0004E67C 38 21 00 10 */ addi r1, r1, 0x10
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/* 80051720 0004E680 4E 80 00 20 */ blr
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.global __ct__16CArchMsgParmNullFv
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__ct__16CArchMsgParmNullFv:
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/* 80051724 0004E684 3C A0 80 3E */ lis r5, __vt__24IArchitectureMessageParm@ha
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/* 80051728 0004E688 3C 80 80 3E */ lis r4, __vt__16CArchMsgParmNull@ha
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/* 8005172C 0004E68C 38 A5 8E 9C */ addi r5, r5, __vt__24IArchitectureMessageParm@l
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/* 80051730 0004E690 90 A3 00 00 */ stw r5, 0(r3)
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/* 80051734 0004E694 38 04 9E 70 */ addi r0, r4, __vt__16CArchMsgParmNull@l
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/* 80051738 0004E698 90 03 00 00 */ stw r0, 0(r3)
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/* 8005173C 0004E69C 4E 80 00 20 */ blr
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