mirror of https://git.wuffs.org/MWCC
1041 lines
38 KiB
C
1041 lines
38 KiB
C
#include "compiler/Operands.h"
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#include "compiler/CError.h"
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#include "compiler/CMachine.h"
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#include "compiler/CParser.h"
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#include "compiler/CodeGen.h"
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#include "compiler/CompilerTools.h"
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#include "compiler/PCode.h"
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#include "compiler/PCodeInfo.h"
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#include "compiler/PCodeUtilities.h"
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#include "compiler/RegisterInfo.h"
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#include "compiler/Registers.h"
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#include "compiler/StackFrame.h"
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#include "compiler/TOC.h"
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#include "compiler/enode.h"
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#include "compiler/objects.h"
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unsigned long long uns_to_float_cc = 0x4330000000000000;
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unsigned long long int_to_float_cc = 0x4330000080000000;
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Float one_point_zero = {1.0};
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void load_immediate(short reg, SInt32 value) {
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short tmpreg = reg;
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short tmpreg2;
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if (!FITS_IN_SHORT(value)) {
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if (copts.optimizationlevel > 1 && value)
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tmpreg = used_virtual_registers[RegClass_GPR]++;
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emitpcode(PC_LIS, tmpreg2 = tmpreg, 0, (short) HIGH_PART(value));
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if (LOW_PART(value))
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emitpcode(PC_ADDI, reg, tmpreg2, 0, LOW_PART(value));
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} else {
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emitpcode(PC_LI, reg, value);
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}
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}
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static void set_op_flags(Operand *op, ENode *expr) {
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CError_ASSERT(118, op);
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if (expr) {
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if (expr->type == EINTCONST) {
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op->flags = 0;
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if (expr->flags & ENODE_FLAG_VOLATILE)
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op->flags |= OpndFlags_Volatile;
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if (expr->flags & ENODE_FLAG_CONST)
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op->flags |= OpndFlags_Const;
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} else {
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op->flags = CParserIsVolatileExpr(expr) ? OpndFlags_Volatile : 0;
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op->flags |= CParserIsConstExpr(expr) ? OpndFlags_Const : 0;
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}
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} else {
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op->flags = 0;
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}
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}
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void symbol_operand(Operand *op, Object *obj) {
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memclrw(op, sizeof(Operand));
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op->optype = OpndType_Symbol;
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op->object = obj;
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}
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void indirect(Operand *op, ENode *expr) {
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switch (op->optype) {
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case OpndType_GPRPair:
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CError_FATAL(163);
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case OpndType_CRField:
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case OpndType_IndirectGPR_ImmOffset:
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case OpndType_IndirectGPR_Indexed:
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case OpndType_IndirectSymbol:
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if (op->optype)
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Coerce_to_register(op, TYPE(&void_ptr), 0);
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case OpndType_GPR:
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op->immOffset = 0;
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op->object = NULL;
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case OpndType_GPR_ImmOffset:
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op->optype = OpndType_IndirectGPR_ImmOffset;
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set_op_flags(op, expr);
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break;
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case OpndType_GPR_Indexed:
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op->optype = OpndType_IndirectGPR_Indexed;
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set_op_flags(op, expr);
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break;
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case OpndType_Absolute:
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if (FITS_IN_SHORT(op->immediate)) {
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op->reg = 0;
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op->immOffset = op->immediate;
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} else {
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emitpcode(PC_LIS, op->reg = used_virtual_registers[RegClass_GPR]++, 0, (short) HIGH_PART(op->immediate));
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op->immOffset = LOW_PART(op->immediate);
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}
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op->object = NULL;
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op->optype = OpndType_IndirectGPR_ImmOffset;
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set_op_flags(op, expr);
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break;
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case OpndType_Symbol:
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op->optype = OpndType_IndirectSymbol;
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set_op_flags(op, expr);
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break;
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default:
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CError_FATAL(215);
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}
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}
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#define COMBO_OP(a, b) (b + (a * 11))
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void combine(Operand *opA, Operand *opB, short output_reg, Operand *opOut) {
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Operand *tmp_op;
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int tmp;
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if (opA->optype == OpndType_Symbol || opA->optype == OpndType_IndirectSymbol)
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coerce_to_addressable(opA);
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if (opB->optype == OpndType_Symbol || opB->optype == OpndType_IndirectSymbol)
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coerce_to_addressable(opB);
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switch (COMBO_OP(opA->optype, opB->optype)) {
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case COMBO_OP(OpndType_GPR, OpndType_GPR):
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opOut->optype = OpndType_GPR_Indexed;
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opOut->reg = opA->reg;
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opOut->regOffset = opB->reg;
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break;
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case COMBO_OP(OpndType_GPR_ImmOffset, OpndType_GPR_ImmOffset):
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if (FITS_IN_SHORT(opA->immOffset + opB->immOffset) && (!opA->object || !opB->object)) {
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opB->immOffset += opA->immOffset;
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if (!opB->object)
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opB->object = opA->object;
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} else {
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tmp = (output_reg && (output_reg != opB->reg)) ? output_reg : used_virtual_registers[RegClass_GPR]++;
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add_immediate(tmp, opA->reg, opA->object, opA->immOffset);
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opA->reg = tmp;
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}
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case COMBO_OP(OpndType_GPR, OpndType_GPR_ImmOffset):
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tmp_op = opA;
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opA = opB;
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opB = tmp_op;
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case COMBO_OP(OpndType_GPR_ImmOffset, OpndType_GPR):
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if (opA->reg == _FP_ || opA->reg == _CALLER_SP_) {
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opOut->optype = OpndType_GPR_Indexed;
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opOut->reg = (output_reg && (output_reg != opB->reg)) ? output_reg : used_virtual_registers[RegClass_GPR]++;
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opOut->regOffset = opB->reg;
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add_immediate(opOut->reg, opA->reg, opA->object, LOW_PART(opA->immOffset));
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} else if (opB->reg == _FP_ || opB->reg == _CALLER_SP_) {
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opOut->optype = OpndType_GPR_Indexed;
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opOut->reg = (output_reg && (output_reg != opA->reg)) ? output_reg : used_virtual_registers[RegClass_GPR]++;
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opOut->regOffset = opA->reg;
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add_immediate(opOut->reg, opB->reg, opA->object, LOW_PART(opA->immOffset));
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} else if (opA->object) {
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opOut->optype = OpndType_GPR_Indexed;
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opOut->reg = (output_reg && (output_reg != opB->reg)) ? output_reg : used_virtual_registers[RegClass_GPR]++;
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opOut->regOffset = opB->reg;
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add_immediate(opOut->reg, opA->reg, opA->object, LOW_PART(opA->immOffset));
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} else {
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opOut->optype = OpndType_GPR_ImmOffset;
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opOut->reg = output_reg ? output_reg : used_virtual_registers[RegClass_GPR]++;
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opOut->immOffset = opA->immOffset;
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opOut->object = opA->object;
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emitpcode(PC_ADD, opOut->reg, opA->reg, opB->reg);
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}
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break;
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case COMBO_OP(OpndType_GPR, OpndType_GPR_Indexed):
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tmp_op = opA;
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opA = opB;
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opB = tmp_op;
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case COMBO_OP(OpndType_GPR_Indexed, OpndType_GPR):
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opOut->optype = OpndType_GPR_Indexed;
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opOut->reg = opA->reg;
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opOut->regOffset = (output_reg && (output_reg != opA->reg)) ? output_reg : used_virtual_registers[RegClass_GPR]++;
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emitpcode(PC_ADD, opOut->regOffset, opA->regOffset, opB->reg);
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break;
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case COMBO_OP(OpndType_GPR_ImmOffset, OpndType_GPR_Indexed):
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tmp_op = opA;
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opA = opB;
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opB = tmp_op;
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case COMBO_OP(OpndType_GPR_Indexed, OpndType_GPR_ImmOffset):
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if (opB->object) {
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opOut->optype = OpndType_GPR_Indexed;
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opOut->reg = (output_reg && (output_reg != opB->reg)) ? output_reg
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: used_virtual_registers[RegClass_GPR]++;
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opOut->regOffset = used_virtual_registers[RegClass_GPR]++;
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emitpcode(PC_ADD, opOut->reg, opA->reg, opA->regOffset);
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add_immediate(opOut->regOffset, opB->reg, opB->object, opB->immOffset);
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} else {
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opOut->optype = OpndType_GPR_ImmOffset;
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opOut->immOffset = opB->immOffset;
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opOut->object = opB->object;
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opOut->reg = (output_reg && (output_reg != opB->reg)) ? output_reg
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: used_virtual_registers[RegClass_GPR]++;
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emitpcode(PC_ADD, opOut->reg, opA->reg, opA->regOffset);
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emitpcode(PC_ADD, opOut->reg, opOut->reg, opB->reg);
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}
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break;
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case COMBO_OP(OpndType_GPR_Indexed, OpndType_GPR_Indexed):
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opOut->optype = OpndType_GPR_Indexed;
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opOut->reg = opA->reg;
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opOut->regOffset = (output_reg && (output_reg != opA->regOffset)) ? output_reg
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: used_virtual_registers[RegClass_GPR]++;
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emitpcode(PC_ADD, opOut->regOffset, opB->reg, opB->regOffset);
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emitpcode(PC_ADD, opOut->regOffset, opOut->regOffset, opA->regOffset);
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break;
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case COMBO_OP(OpndType_GPR_ImmOffset, OpndType_Absolute):
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tmp_op = opA;
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opA = opB;
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opB = tmp_op;
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case COMBO_OP(OpndType_Absolute, OpndType_GPR_ImmOffset):
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if (!opB->object) {
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opOut->optype = OpndType_GPR_ImmOffset;
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opOut->reg = opB->reg;
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opOut->immOffset = opB->immOffset;
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opOut->object = opB->object;
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if (FITS_IN_SHORT(opOut->immOffset + opA->immediate)) {
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opOut->immOffset += opA->immediate;
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} else {
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opOut->reg = output_reg ? output_reg : used_virtual_registers[RegClass_GPR]++;
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if (!HIGH_PART(opA->immediate)) {
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emitpcode(PC_ADDI, opOut->reg, opB->reg, 0, LOW_PART(opA->immediate));
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} else {
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emitpcode(PC_ADDIS, opOut->reg, opB->reg, 0, (short) HIGH_PART(opA->immediate));
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if (FITS_IN_SHORT(opOut->immOffset + LOW_PART(opA->immediate))) {
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opOut->immOffset += LOW_PART(opA->immediate);
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} else {
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emitpcode(PC_ADDI, opOut->reg, opOut->reg, 0, LOW_PART(opA->immediate));
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}
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}
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}
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break;
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} else if (opB->object->datatype == DLOCAL && can_add_displ_to_local(opB->object, opB->immOffset + opA->immediate)) {
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opOut->optype = OpndType_GPR_ImmOffset;
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opOut->object = opB->object;
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opOut->reg = opB->reg;
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opOut->immOffset = LOW_PART(opB->immOffset + opA->immediate);
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break;
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} else {
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opOut->reg = output_reg ? output_reg : used_virtual_registers[RegClass_GPR]++;
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add_immediate(opOut->reg, opB->reg, opB->object, opB->immOffset);
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opB->optype = OpndType_GPR;
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opB->reg = opOut->reg;
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tmp_op = opA;
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opA = opB;
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opB = tmp_op;
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}
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case COMBO_OP(OpndType_GPR, OpndType_Absolute):
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tmp_op = opA;
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opA = opB;
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opB = tmp_op;
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case COMBO_OP(OpndType_Absolute, OpndType_GPR):
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opOut->optype = (opA->immediate != 0) ? OpndType_GPR_ImmOffset : OpndType_GPR;
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opOut->immOffset = LOW_PART(opA->immediate);
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opOut->object = NULL;
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if (FITS_IN_SHORT(opA->immediate)) {
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opOut->reg = opB->reg;
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} else {
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opOut->reg = output_reg ? output_reg : used_virtual_registers[RegClass_GPR]++;
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emitpcode(PC_ADDIS, opOut->reg, opB->reg, 0, (short) HIGH_PART(opA->immediate));
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}
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break;
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case COMBO_OP(OpndType_GPR_Indexed, OpndType_Absolute):
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tmp_op = opA;
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opA = opB;
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opB = tmp_op;
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case COMBO_OP(OpndType_Absolute, OpndType_GPR_Indexed):
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opOut->optype = OpndType_GPR_Indexed;
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opOut->reg = opB->reg;
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opOut->regOffset = (output_reg && (output_reg != opB->reg)) ? output_reg : used_virtual_registers[RegClass_GPR]++;
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if (!HIGH_PART(opA->immediate)) {
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emitpcode(PC_ADDI, opOut->regOffset, opB->regOffset, 0, LOW_PART(opA->immediate));
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} else {
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emitpcode(PC_ADDIS, opOut->regOffset, opB->regOffset, 0, (short) HIGH_PART(opA->immediate));
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if (LOW_PART(opA->immediate))
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emitpcode(PC_ADDI, opOut->regOffset, opOut->regOffset, 0, LOW_PART(opA->immediate));
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}
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break;
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case COMBO_OP(OpndType_Absolute, OpndType_Absolute):
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opOut->optype = OpndType_Absolute;
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opOut->immediate = opA->immediate + opB->immediate;
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break;
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default:
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CError_FATAL(415);
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}
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}
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void coerce_to_addressable(Operand *op) {
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UInt32 offset;
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short reg;
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short flag;
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short tmp;
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Object *obj;
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flag = 0;
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obj = op->object;
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tmp = 0;
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switch (op->optype) {
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case OpndType_GPR:
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case OpndType_GPR_ImmOffset:
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case OpndType_GPR_Indexed:
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case OpndType_GPRPair:
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case OpndType_Absolute:
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case OpndType_VR:
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case OpndType_CRField:
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case OpndType_IndirectGPR_ImmOffset:
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case OpndType_IndirectGPR_Indexed:
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break;
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case OpndType_IndirectSymbol:
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flag = 1;
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case OpndType_Symbol:
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if (obj->datatype == DLOCAL) {
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if (!local_is_16bit_offset(obj)) {
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reg = used_virtual_registers[RegClass_GPR]++;
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op_absolute_ha(reg, local_base_register(obj), obj, 0, 1);
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op->optype = OpndType_GPR_ImmOffset;
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op->reg = reg;
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op->object = obj;
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} else {
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op->optype = OpndType_GPR_ImmOffset;
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op->reg = local_base_register(obj);
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op->object = obj;
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}
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} else if (obj->datatype == DABSOLUTE) {
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offset = obj->u.address;
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if (FITS_IN_SHORT(offset)) {
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op->reg = 0;
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op->immOffset = obj->u.address;
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} else {
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emitpcode(PC_LIS, op->reg = used_virtual_registers[RegClass_GPR]++, 0, (short) HIGH_PART(offset));
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op->immOffset = LOW_PART(obj->u.address);
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}
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op->object = obj;
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op->optype = OpndType_GPR_ImmOffset;
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} else {
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if (copts.codegen_pic)
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tmp = pic_base_reg;
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reg = used_virtual_registers[RegClass_GPR]++;
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op_absolute_ha(reg, tmp, obj, 0, 1);
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op->optype = OpndType_GPR_ImmOffset;
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op->reg = reg;
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}
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if (flag) {
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if (op->optype == OpndType_GPR_ImmOffset) {
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op->optype = OpndType_IndirectGPR_ImmOffset;
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} else {
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CError_FATAL(563);
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}
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}
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break;
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default:
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CError_FATAL(581);
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}
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}
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void Coerce_to_register(Operand *op, Type *type, short output_reg) {
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SInt32 offset;
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Opcode opcode;
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short reg;
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short tmp;
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short cond_neg;
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short cond;
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short bit_offset;
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short bit_size;
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if (TYPE_IS_8BYTES(type)) {
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coerce_to_register_pair(op, type, output_reg, 0);
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return;
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}
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coerce_to_addressable(op);
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switch (op->optype) {
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case OpndType_GPRPair:
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return;
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case OpndType_GPR:
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return;
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case OpndType_GPR_ImmOffset:
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reg = output_reg ? output_reg : used_virtual_registers[RegClass_GPR]++;
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add_immediate(reg, op->reg, op->object, op->immOffset);
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break;
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case OpndType_GPR_Indexed:
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reg = output_reg ? output_reg : used_virtual_registers[RegClass_GPR]++;
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emitpcode(PC_ADD, reg, op->reg, op->regOffset);
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break;
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case OpndType_Absolute:
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reg = output_reg ? output_reg : used_virtual_registers[RegClass_GPR]++;
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offset = op->immediate;
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if (FITS_IN_SHORT(offset)) {
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emitpcode(PC_LI, reg, offset);
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} else {
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tmp = reg;
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if (copts.optimizationlevel > 1 && offset)
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tmp = used_virtual_registers[RegClass_GPR]++;
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emitpcode(PC_LIS, tmp, 0, (short) HIGH_PART(offset));
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if (LOW_PART(offset))
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emitpcode(PC_ADDI, reg, tmp, 0, LOW_PART(offset));
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}
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break;
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case OpndType_IndirectGPR_ImmOffset:
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reg = output_reg ? output_reg : used_virtual_registers[RegClass_GPR]++;
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opcode = PC_LWZ;
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if (IS_TYPE_INT(type) || IS_TYPE_ENUM(type)) {
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switch (type->size) {
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case 1:
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opcode = PC_LBZ;
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break;
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case 2:
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if (is_unsigned(type))
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opcode = PC_LHZ;
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else
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opcode = PC_LHA;
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break;
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}
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} else {
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CError_ASSERT(680, IS_TYPE_POINTER(type) || IS_TYPE_4BYTES_MEMBERPOINTER(type));
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}
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load_store_register(opcode, reg, op->reg, op->object, op->immOffset);
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setpcodeflags(op->flags);
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break;
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case OpndType_IndirectGPR_Indexed:
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reg = output_reg ? output_reg : used_virtual_registers[RegClass_GPR]++;
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opcode = PC_LWZX;
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if (IS_TYPE_INT(type) || IS_TYPE_ENUM(type)) {
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switch (type->size) {
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case 1:
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opcode = PC_LBZX;
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break;
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case 2:
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if (is_unsigned(type))
|
|
opcode = PC_LHZX;
|
|
else
|
|
opcode = PC_LHAX;
|
|
break;
|
|
}
|
|
} else {
|
|
CError_ASSERT(724, IS_TYPE_POINTER(type) || IS_TYPE_4BYTES_MEMBERPOINTER(type));
|
|
}
|
|
emitpcode(opcode, reg, op->reg, op->regOffset);
|
|
setpcodeflags(op->flags);
|
|
break;
|
|
case OpndType_CRField:
|
|
cond_neg = 0;
|
|
cond = 0;
|
|
reg = output_reg ? output_reg : used_virtual_registers[RegClass_GPR]++;
|
|
emitpcode(PC_MFCR, tmp = reg);
|
|
switch (op->regOffset) {
|
|
case ENOTEQU:
|
|
cond_neg = 1;
|
|
case EEQU:
|
|
cond = 2;
|
|
break;
|
|
case EGREATEREQU:
|
|
cond_neg = 1;
|
|
case ELESS:
|
|
cond = 0;
|
|
break;
|
|
case ELESSEQU:
|
|
cond_neg = 1;
|
|
case EGREATER:
|
|
cond = 1;
|
|
break;
|
|
default:
|
|
CError_FATAL(758);
|
|
}
|
|
bit_offset = cond + (op->reg << 2);
|
|
bit_size = 1;
|
|
emitpcode(PC_RLWINM, tmp, tmp, (bit_size + bit_offset) & 31, 32 - bit_size, 31);
|
|
if (cond_neg)
|
|
emitpcode(PC_XORI, tmp, tmp, 1);
|
|
break;
|
|
default:
|
|
CError_FATAL(769);
|
|
}
|
|
|
|
op->optype = OpndType_GPR;
|
|
op->reg = reg;
|
|
}
|
|
|
|
void coerce_to_register_pair(Operand *op, Type *type, short output_reg, short output_regHi) {
|
|
SInt32 offset;
|
|
short reg;
|
|
short regHi;
|
|
short tmp1;
|
|
short tmp2;
|
|
|
|
regHi = -1;
|
|
|
|
CError_ASSERT(794, TYPE_IS_8BYTES(type) || (IS_TYPE_STRUCT(type) && type->size == 8));
|
|
|
|
coerce_to_addressable(op);
|
|
switch (op->optype) {
|
|
case OpndType_GPRPair:
|
|
if (output_reg && !output_regHi)
|
|
output_regHi = used_virtual_registers[RegClass_GPR]++;
|
|
if (output_regHi && !output_reg)
|
|
output_reg = used_virtual_registers[RegClass_GPR]++;
|
|
if (op->reg != output_reg || op->regHi != output_regHi) {
|
|
tmp1 = output_reg ? output_reg : op->reg;
|
|
tmp2 = output_regHi ? output_regHi : op->regHi;
|
|
if (tmp1 != op->reg) {
|
|
if (tmp1 == op->regHi) {
|
|
CError_ASSERT(818, tmp1 != tmp2);
|
|
emitpcode(PC_MR, tmp2, op->regHi);
|
|
emitpcode(PC_MR, tmp1, op->reg);
|
|
} else {
|
|
emitpcode(PC_MR, tmp1, op->reg);
|
|
if (op->regHi != tmp2)
|
|
emitpcode(PC_MR, tmp2, op->regHi);
|
|
}
|
|
} else if (tmp2 != op->regHi) {
|
|
if (tmp2 == op->reg) {
|
|
CError_ASSERT(832, tmp1 != tmp2);
|
|
emitpcode(PC_MR, tmp1, op->reg);
|
|
emitpcode(PC_MR, tmp2, op->regHi);
|
|
} else {
|
|
emitpcode(PC_MR, tmp2, op->regHi);
|
|
if (op->reg != tmp1)
|
|
emitpcode(PC_MR, tmp1, op->reg);
|
|
}
|
|
}
|
|
}
|
|
reg = op->reg;
|
|
regHi = op->regHi;
|
|
break;
|
|
case OpndType_GPR:
|
|
CError_FATAL(849);
|
|
break;
|
|
case OpndType_GPR_ImmOffset:
|
|
CError_FATAL(852);
|
|
break;
|
|
case OpndType_GPR_Indexed:
|
|
CError_FATAL(855);
|
|
break;
|
|
case OpndType_Absolute:
|
|
reg = output_reg ? output_reg : used_virtual_registers[RegClass_GPR]++;
|
|
offset = op->immediate;
|
|
if (FITS_IN_SHORT(offset)) {
|
|
emitpcode(PC_LI, reg, offset);
|
|
} else {
|
|
tmp1 = reg;
|
|
if (copts.optimizationlevel > 1 && offset)
|
|
tmp1 = used_virtual_registers[RegClass_GPR]++;
|
|
emitpcode(PC_LIS, tmp1, 0, (short) HIGH_PART(offset));
|
|
if (LOW_PART(offset))
|
|
emitpcode(PC_ADDI, reg, tmp1, 0, LOW_PART(offset));
|
|
}
|
|
regHi = output_regHi ? output_regHi : used_virtual_registers[RegClass_GPR]++;
|
|
if (is_unsigned(type) || offset >= 0)
|
|
load_immediate(regHi, 0);
|
|
else
|
|
load_immediate(regHi, -1);
|
|
break;
|
|
case OpndType_IndirectGPR_ImmOffset:
|
|
reg = output_reg ? output_reg : used_virtual_registers[RegClass_GPR]++;
|
|
regHi = output_regHi ? output_regHi : used_virtual_registers[RegClass_GPR]++;
|
|
if (op->reg == regHi) {
|
|
if (op->reg == reg) {
|
|
CError_FATAL(887);
|
|
} else {
|
|
load_store_register(PC_LWZ, reg, op->reg, op->object, op->immOffset + low_offset);
|
|
setpcodeflags(op->flags);
|
|
load_store_register(PC_LWZ, regHi, op->reg, op->object, op->immOffset + high_offset);
|
|
setpcodeflags(op->flags);
|
|
}
|
|
} else {
|
|
load_store_register(PC_LWZ, regHi, op->reg, op->object, op->immOffset + high_offset);
|
|
setpcodeflags(op->flags);
|
|
load_store_register(PC_LWZ, reg, op->reg, op->object, op->immOffset + low_offset);
|
|
setpcodeflags(op->flags);
|
|
}
|
|
break;
|
|
case OpndType_IndirectGPR_Indexed:
|
|
reg = output_reg ? output_reg : used_virtual_registers[RegClass_GPR]++;
|
|
regHi = output_regHi ? output_regHi : used_virtual_registers[RegClass_GPR]++;
|
|
emitpcode(PC_ADD, reg, op->reg, op->regOffset);
|
|
load_store_register(PC_LWZ, regHi, reg, NULL, high_offset);
|
|
setpcodeflags(op->flags);
|
|
load_store_register(PC_LWZ, reg, reg, NULL, low_offset);
|
|
setpcodeflags(op->flags);
|
|
break;
|
|
default:
|
|
CError_FATAL(912);
|
|
}
|
|
|
|
if (regHi == -1) {
|
|
CError_FATAL(916);
|
|
} else {
|
|
op->optype = OpndType_GPRPair;
|
|
op->reg = reg;
|
|
op->regHi = regHi;
|
|
}
|
|
}
|
|
|
|
void Coerce_to_fp_register(Operand *op, Type *type, short output_reg) {
|
|
short reg;
|
|
|
|
coerce_to_addressable(op);
|
|
|
|
switch (op->optype) {
|
|
case OpndType_FPR:
|
|
reg = op->reg;
|
|
break;
|
|
case OpndType_IndirectGPR_ImmOffset:
|
|
reg = output_reg ? output_reg : used_virtual_registers[RegClass_FPR]++;
|
|
load_store_register((type->size == 4) ? PC_LFS : PC_LFD, reg, op->reg, op->object, op->immOffset);
|
|
setpcodeflags(op->flags);
|
|
break;
|
|
case OpndType_IndirectGPR_Indexed:
|
|
reg = output_reg ? output_reg : used_virtual_registers[RegClass_FPR]++;
|
|
emitpcode((type->size == 4) ? PC_LFSX : PC_LFDX, reg, op->reg, op->regOffset, 0, 0x390);
|
|
setpcodeflags(op->flags);
|
|
break;
|
|
default:
|
|
CError_FATAL(986);
|
|
}
|
|
|
|
op->optype = OpndType_FPR;
|
|
op->reg = reg;
|
|
}
|
|
|
|
void Coerce_to_v_register(Operand *op, Type *type, short output_reg) {
|
|
short reg;
|
|
|
|
coerce_to_addressable(op);
|
|
|
|
switch (op->optype) {
|
|
case OpndType_VR:
|
|
reg = op->reg;
|
|
break;
|
|
case OpndType_IndirectGPR_ImmOffset:
|
|
reg = output_reg ? output_reg : used_virtual_registers[RegClass_VR]++;
|
|
load_store_register(PC_LVX, reg, op->reg, op->object, op->immOffset);
|
|
setpcodeflags(op->flags);
|
|
break;
|
|
case OpndType_IndirectGPR_Indexed:
|
|
reg = output_reg ? output_reg : used_virtual_registers[RegClass_VR]++;
|
|
emitpcode(PC_LVX, reg, op->reg, op->regOffset);
|
|
setpcodeflags(op->flags);
|
|
break;
|
|
case OpndType_Absolute:
|
|
reg = output_reg ? output_reg : used_virtual_registers[RegClass_VR]++;
|
|
switch (TYPE_STRUCT(type)->stype) {
|
|
case STRUCT_VECTOR_UCHAR:
|
|
case STRUCT_VECTOR_SCHAR:
|
|
case STRUCT_VECTOR_BCHAR:
|
|
emitpcode(PC_VSPLTISB, reg, op->immediate);
|
|
break;
|
|
case STRUCT_VECTOR_USHORT:
|
|
case STRUCT_VECTOR_SSHORT:
|
|
case STRUCT_VECTOR_BSHORT:
|
|
case STRUCT_VECTOR_PIXEL:
|
|
emitpcode(PC_VSPLTISH, reg, op->immediate);
|
|
break;
|
|
case STRUCT_VECTOR_UINT:
|
|
case STRUCT_VECTOR_SINT:
|
|
case STRUCT_VECTOR_BINT:
|
|
case STRUCT_VECTOR_FLOAT:
|
|
emitpcode(PC_VSPLTISW, reg, op->immediate);
|
|
break;
|
|
default:
|
|
CError_FATAL(1049);
|
|
}
|
|
op->optype = OpndType_VR;
|
|
op->reg = reg;
|
|
setpcodeflags(op->flags);
|
|
break;
|
|
default:
|
|
CError_FATAL(1059);
|
|
}
|
|
|
|
op->optype = OpndType_VR;
|
|
op->reg = reg;
|
|
}
|
|
|
|
void store(short reg, Operand *op, Type *type) {
|
|
Opcode opcode;
|
|
|
|
coerce_to_addressable(op);
|
|
switch (op->optype) {
|
|
case OpndType_IndirectGPR_ImmOffset:
|
|
opcode = PC_STW;
|
|
if (IS_TYPE_INT(type) || IS_TYPE_ENUM(type)) {
|
|
switch (type->size) {
|
|
case 1:
|
|
opcode = PC_STB;
|
|
break;
|
|
case 2:
|
|
opcode = PC_STH;
|
|
break;
|
|
}
|
|
} else {
|
|
CError_ASSERT(1171, IS_TYPE_POINTER(type) || IS_TYPE_4BYTES_MEMBERPOINTER(type));
|
|
}
|
|
load_store_register(opcode, reg, op->reg, op->object, op->immOffset);
|
|
setpcodeflags(op->flags);
|
|
break;
|
|
case OpndType_IndirectGPR_Indexed:
|
|
opcode = PC_STWX;
|
|
if (IS_TYPE_INT(type) || IS_TYPE_ENUM(type)) {
|
|
switch (type->size) {
|
|
case 1:
|
|
opcode = PC_STBX;
|
|
break;
|
|
case 2:
|
|
opcode = PC_STHX;
|
|
break;
|
|
}
|
|
} else {
|
|
CError_ASSERT(1188, IS_TYPE_POINTER(type) || IS_TYPE_4BYTES_MEMBERPOINTER(type));
|
|
}
|
|
emitpcode(opcode, reg, op->reg, op->regOffset);
|
|
setpcodeflags(op->flags);
|
|
break;
|
|
default:
|
|
CError_FATAL(1193);
|
|
}
|
|
}
|
|
|
|
void store_pair(short reg, short regHi, Operand *op, Type *type) {
|
|
short tmp;
|
|
|
|
CError_ASSERT(1208, TYPE_IS_8BYTES(type));
|
|
|
|
coerce_to_addressable(op);
|
|
switch (op->optype) {
|
|
case OpndType_IndirectGPR_ImmOffset:
|
|
load_store_register(PC_STW, reg, op->reg, op->object, op->immOffset + low_offset);
|
|
setpcodeflags(op->flags);
|
|
load_store_register(PC_STW, regHi, op->reg, op->object, op->immOffset + high_offset);
|
|
setpcodeflags(op->flags);
|
|
break;
|
|
case OpndType_IndirectGPR_Indexed:
|
|
tmp = used_virtual_registers[RegClass_GPR]++;
|
|
emitpcode(PC_ADD, tmp, op->reg, op->regOffset);
|
|
load_store_register(PC_STW, reg, tmp, NULL, low_offset);
|
|
setpcodeflags(op->flags);
|
|
load_store_register(PC_STW, regHi, tmp, NULL, high_offset);
|
|
setpcodeflags(op->flags);
|
|
break;
|
|
default:
|
|
CError_FATAL(1228);
|
|
}
|
|
}
|
|
|
|
void store_fp(short reg, Operand *op, Type *type) {
|
|
coerce_to_addressable(op);
|
|
switch (op->optype) {
|
|
case OpndType_IndirectGPR_ImmOffset:
|
|
load_store_register((type->size == 4) ? PC_STFS : PC_STFD, reg, op->reg, op->object, op->immOffset);
|
|
setpcodeflags(op->flags);
|
|
break;
|
|
case OpndType_IndirectGPR_Indexed:
|
|
emitpcode((type->size == 4) ? PC_STFSX : PC_STFDX, reg, op->reg, op->regOffset);
|
|
setpcodeflags(op->flags);
|
|
break;
|
|
default:
|
|
CError_FATAL(1259);
|
|
}
|
|
}
|
|
|
|
void store_v(short reg, Operand *op, Type *tstruct) {
|
|
coerce_to_addressable(op);
|
|
switch (op->optype) {
|
|
case OpndType_IndirectGPR_ImmOffset:
|
|
load_store_register(PC_STVX, reg, op->reg, op->object, op->immOffset);
|
|
setpcodeflags(op->flags);
|
|
break;
|
|
case OpndType_IndirectGPR_Indexed:
|
|
emitpcode(PC_STVX, reg, op->reg, op->regOffset);
|
|
setpcodeflags(op->flags);
|
|
break;
|
|
default:
|
|
CError_FATAL(1283);
|
|
}
|
|
}
|
|
|
|
static Boolean last_matches_rlwinm_or_exts(Operand *op, short opcode, short b, short c) {
|
|
PCode *pc;
|
|
|
|
if (pclastblock->pcodeCount <= 0)
|
|
return 0;
|
|
|
|
pc = pclastblock->lastPCode;
|
|
if (pc->args[0].kind != PCOp_REGISTER || pc->args[0].arg != RegClass_GPR || pc->args[0].data.reg.reg != op->reg)
|
|
return 0;
|
|
|
|
if (pc->op != opcode && (opcode != PC_EXTSH || pc->op != PC_EXTSB))
|
|
return 0;
|
|
|
|
if (opcode == PC_RLWINM) {
|
|
if (pc->args[2].data.imm.value != 0 || pc->args[3].data.imm.value != b || pc->args[4].data.imm.value != c)
|
|
return 0;
|
|
}
|
|
|
|
return 1;
|
|
}
|
|
|
|
void extend32(Operand *op, Type *type, short output_reg) {
|
|
int r28;
|
|
int reg;
|
|
|
|
r28 = op->optype >= OpndType_IndirectGPR_ImmOffset;
|
|
if (op->optype != OpndType_GPR)
|
|
Coerce_to_register(op, type, output_reg);
|
|
|
|
switch (type->size) {
|
|
case 1:
|
|
if (is_unsigned(type)) {
|
|
if (r28)
|
|
return;
|
|
if (last_matches_rlwinm_or_exts(op, PC_RLWINM, 24, 31))
|
|
return;
|
|
reg = output_reg ? output_reg : used_virtual_registers[RegClass_GPR]++;
|
|
emitpcode(PC_RLWINM, reg, op->reg, 0, 24, 31);
|
|
} else {
|
|
reg = output_reg ? output_reg : used_virtual_registers[RegClass_GPR]++;
|
|
if (last_matches_rlwinm_or_exts(op, PC_EXTSB, 0, 0))
|
|
return;
|
|
emitpcode(PC_EXTSB, reg, op->reg);
|
|
}
|
|
break;
|
|
case 2:
|
|
if (r28)
|
|
return;
|
|
if (is_unsigned(type)) {
|
|
if (last_matches_rlwinm_or_exts(op, PC_RLWINM, 16, 31))
|
|
return;
|
|
reg = output_reg ? output_reg : used_virtual_registers[RegClass_GPR]++;
|
|
emitpcode(PC_RLWINM, reg, op->reg, 0, 16, 31);
|
|
} else {
|
|
if (last_matches_rlwinm_or_exts(op, PC_EXTSH, 0, 0))
|
|
return;
|
|
reg = output_reg ? output_reg : used_virtual_registers[RegClass_GPR]++;
|
|
emitpcode(PC_EXTSH, reg, op->reg);
|
|
}
|
|
break;
|
|
default:
|
|
CError_FATAL(1389);
|
|
}
|
|
|
|
op->optype = OpndType_GPR;
|
|
op->reg = reg;
|
|
}
|
|
|
|
void extend64(Operand *op, Type *type, short output_reg, short output_regHi) {
|
|
short tmp;
|
|
short regHi;
|
|
|
|
if (op->optype != OpndType_GPR)
|
|
Coerce_to_register(op, type, output_reg);
|
|
|
|
regHi = output_regHi ? output_regHi : used_virtual_registers[RegClass_GPR]++;
|
|
if (regHi == op->reg) {
|
|
tmp = output_reg ? output_reg : used_virtual_registers[RegClass_GPR]++;
|
|
emitpcode(PC_MR, tmp, op->reg);
|
|
op->reg = tmp;
|
|
}
|
|
|
|
if (is_unsigned(type))
|
|
load_immediate(regHi, 0);
|
|
else
|
|
emitpcode(PC_SRAWI, regHi, op->reg, 31);
|
|
|
|
op->optype = OpndType_GPRPair;
|
|
op->regHi = regHi;
|
|
}
|
|
|
|
void load_floating_constant(short reg, Type *type, Float *data) {
|
|
Object *object;
|
|
Object *indObject;
|
|
Operand op1;
|
|
Operand op2;
|
|
Operand op3;
|
|
SInt32 offset = 0;
|
|
|
|
memclrw(&op1, sizeof(Operand));
|
|
|
|
object = CreateFloatConst(type, data, &offset);
|
|
indObject = createIndirect(object, 0, 1);
|
|
|
|
if (indObject) {
|
|
symbol_operand(&op1, indObject);
|
|
indirect(&op1, NULL);
|
|
} else {
|
|
symbol_operand(&op1, object);
|
|
}
|
|
|
|
if (offset) {
|
|
op2 = op1;
|
|
memclrw(&op3, sizeof(Operand));
|
|
op3.optype = OpndType_Absolute;
|
|
op3.immediate = offset;
|
|
if (op2.optype != OpndType_GPR)
|
|
Coerce_to_register(&op2, TYPE(&void_ptr), 0);
|
|
combine(&op2, &op3, 0, &op1);
|
|
}
|
|
|
|
indirect(&op1, NULL);
|
|
if (op1.optype != OpndType_FPR)
|
|
Coerce_to_fp_register(&op1, type, reg);
|
|
}
|
|
|
|
void convert_integer_to_floating(Operand *op, Boolean is_single, short output_reg) {
|
|
Operand temp_op;
|
|
Float d;
|
|
int const_reg;
|
|
int tmp_reg;
|
|
int work_reg;
|
|
int result_reg;
|
|
Opcode opcode;
|
|
|
|
symbol_operand(&temp_op, maketemporary(TYPE(&stdouble)));
|
|
coerce_to_addressable(&temp_op);
|
|
d.value = *((double *) &int_to_float_cc);
|
|
|
|
const_reg = used_virtual_registers[RegClass_FPR]++;
|
|
load_floating_constant(const_reg, TYPE(&stdouble), &d);
|
|
|
|
tmp_reg = used_virtual_registers[RegClass_GPR]++;
|
|
emitpcode(PC_XORIS, tmp_reg, op->reg, 0x8000);
|
|
load_store_register(PC_STW, tmp_reg, temp_op.reg, temp_op.object, low_offset);
|
|
|
|
emitpcode(PC_LIS, tmp_reg = used_virtual_registers[RegClass_GPR]++, 0, 0x4330);
|
|
load_store_register(PC_STW, tmp_reg, temp_op.reg, temp_op.object, high_offset);
|
|
|
|
load_store_register(PC_LFD, work_reg = used_virtual_registers[RegClass_FPR]++, temp_op.reg, temp_op.object, 0);
|
|
|
|
result_reg = output_reg ? output_reg : used_virtual_registers[RegClass_FPR]++;
|
|
if (is_single != 0)
|
|
opcode = PC_FSUBS;
|
|
else
|
|
opcode = PC_FSUB;
|
|
emitpcode(opcode, result_reg, work_reg, const_reg);
|
|
|
|
op->optype = OpndType_FPR;
|
|
op->reg = result_reg;
|
|
}
|
|
|
|
void convert_unsigned_to_floating(Operand *op, Boolean is_single, short output_reg) {
|
|
Operand temp_op;
|
|
Float d;
|
|
int const_reg;
|
|
int tmp_reg;
|
|
int work_reg;
|
|
int result_reg;
|
|
Opcode opcode;
|
|
|
|
symbol_operand(&temp_op, maketemporary(TYPE(&stdouble)));
|
|
coerce_to_addressable(&temp_op);
|
|
d.value = *((double *) &uns_to_float_cc);
|
|
|
|
const_reg = used_virtual_registers[RegClass_FPR]++;
|
|
load_floating_constant(const_reg, TYPE(&stdouble), &d);
|
|
|
|
load_store_register(PC_STW, op->reg, temp_op.reg, temp_op.object, low_offset);
|
|
|
|
emitpcode(PC_LIS, tmp_reg = used_virtual_registers[RegClass_GPR]++, 0, 0x4330);
|
|
load_store_register(PC_STW, tmp_reg, temp_op.reg, temp_op.object, high_offset);
|
|
|
|
load_store_register(PC_LFD, work_reg = used_virtual_registers[RegClass_FPR]++, temp_op.reg, temp_op.object, 0);
|
|
|
|
result_reg = output_reg ? output_reg : used_virtual_registers[RegClass_FPR]++;
|
|
if (is_single != 0)
|
|
opcode = PC_FSUBS;
|
|
else
|
|
opcode = PC_FSUB;
|
|
emitpcode(opcode, result_reg, work_reg, const_reg);
|
|
|
|
op->optype = OpndType_FPR;
|
|
op->reg = result_reg;
|
|
}
|
|
|
|
void convert_floating_to_integer(Operand *op, short output_reg) {
|
|
Operand temp_op;
|
|
int tmp_reg;
|
|
int result_reg;
|
|
|
|
symbol_operand(&temp_op, maketemporary(TYPE(&stdouble)));
|
|
coerce_to_addressable(&temp_op);
|
|
|
|
tmp_reg = used_virtual_registers[RegClass_FPR]++;
|
|
emitpcode(PC_FCTIWZ, tmp_reg, op->reg);
|
|
load_store_register(PC_STFD, tmp_reg, temp_op.reg, temp_op.object, 0);
|
|
|
|
result_reg = output_reg ? output_reg : used_virtual_registers[RegClass_GPR]++;
|
|
load_store_register(PC_LWZ, result_reg, temp_op.reg, temp_op.object, low_offset);
|
|
|
|
op->optype = OpndType_GPR;
|
|
op->reg = result_reg;
|
|
}
|
|
|
|
void convert_floating_to_unsigned(Operand *op, short output_reg) {
|
|
static UInt32 used_regs[RegClassMax] = {0, 0, 0, 2, 0};
|
|
|
|
if (op->reg != 1)
|
|
emitpcode(PC_FMR, 1, op->reg);
|
|
|
|
branch_subroutine(rt_cvt_fp2unsigned, 0, used_regs);
|
|
|
|
op->optype = OpndType_GPR;
|
|
op->reg = used_virtual_registers[RegClass_GPR]++;
|
|
emitpcode(PC_MR, op->reg, 3);
|
|
}
|
|
|
|
void extract_bitfield(Operand *input_op, TypeBitfield *tbitfield, short output_reg, Operand *output_op) {
|
|
int r27;
|
|
int offset;
|
|
int tmp_reg;
|
|
int output;
|
|
|
|
offset = tbitfield->unkB;
|
|
output = output_reg ? output_reg : used_virtual_registers[RegClass_GPR]++;
|
|
r27 = tbitfield->unkA + (32 - (tbitfield->bitfieldtype->size * 8));
|
|
if (is_unsigned(tbitfield->bitfieldtype)) {
|
|
emitpcode(PC_RLWINM, output, input_op->reg, (r27 + offset) & 31, 32 - offset, 31);
|
|
} else if (r27 == 0) {
|
|
emitpcode(PC_SRAWI, output, input_op->reg, 32 - offset);
|
|
} else {
|
|
tmp_reg = used_virtual_registers[RegClass_GPR]++;
|
|
emitpcode(PC_RLWINM, tmp_reg, input_op->reg, r27 & 31, 0, offset);
|
|
emitpcode(PC_SRAWI, output, tmp_reg, 32 - offset);
|
|
}
|
|
|
|
output_op->optype = OpndType_GPR;
|
|
output_op->reg = output;
|
|
}
|
|
|
|
void insert_bitfield(short reg, Operand *op, TypeBitfield *tbitfield) {
|
|
int offset = tbitfield->unkB;
|
|
int r7 = tbitfield->unkA + (32 - (tbitfield->bitfieldtype->size * 8));
|
|
emitpcode(PC_RLWIMI, op->reg, reg, 32 - (r7 + offset), r7, r7 + offset - 1);
|
|
}
|
|
|
|
void load_address(short dest_reg, Operand *op) {
|
|
coerce_to_addressable(op);
|
|
if (op->optype == OpndType_IndirectGPR_ImmOffset) {
|
|
if (!op->immOffset && !op->object) {
|
|
if (op->reg != dest_reg)
|
|
emitpcode(PC_MR, dest_reg, op->reg);
|
|
} else {
|
|
add_immediate(dest_reg, op->reg, op->object, (SInt16) op->immOffset);
|
|
}
|
|
} else if (op->optype == OpndType_IndirectGPR_Indexed) {
|
|
emitpcode(PC_ADD, dest_reg, op->reg, op->regOffset);
|
|
} else {
|
|
CError_FATAL(1849);
|
|
}
|
|
}
|