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tint/spir-v backend: emit OpSRem instead of OpSMod for remainder

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operation

Bug: tint:1802
Change-Id: I690ef658874ba8d0d9cd8efa2a91324db175650b
Reviewed-on: https://dawn-review.googlesource.com/c/dawn/+/118100
Commit-Queue: Antonio Maiorano <amaiorano@google.com>
Reviewed-by: David Neto <dneto@google.com>
Kokoro: Ben Clayton <bclayton@google.com>
Reviewed-by: Ben Clayton <bclayton@google.com>
This commit is contained in:
Antonio Maiorano
2023-01-31 19:09:05 +00:00
committed by Dawn LUCI CQ
parent 18204a71c3
commit 635c5d0f04
23 changed files with 23 additions and 35 deletions
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2
test/tint/expressions/binary/mod_by_zero/by_constant/scalar-scalar/i32.wgsl.expected.spvasm
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@@ -30,7 +30,7 @@
%15 = OpLogicalAnd %bool %12 %14
%16 = OpLogicalOr %bool %9 %15
%7 = OpSelect %int %16 %int_1 %rhs
%18 = OpSMod %int %lhs %7
%18 = OpSRem %int %lhs %7
OpReturnValue %18
OpFunctionEnd
%f = OpFunction %void None %19

2
test/tint/expressions/binary/mod_by_zero/by_constant/scalar-vec3/i32.wgsl.expected.spvasm
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@@ -40,7 +40,7 @@
%20 = OpLogicalAnd %v3bool %16 %19
%21 = OpLogicalOr %v3bool %11 %20
%9 = OpSelect %v3int %21 %23 %rhs
%24 = OpSMod %v3int %8 %9
%24 = OpSRem %v3int %8 %9
OpReturnValue %24
OpFunctionEnd
%f = OpFunction %void None %25

2
test/tint/expressions/binary/mod_by_zero/by_constant/vec3-scalar/i32.wgsl.expected.spvasm
View File

@@ -40,7 +40,7 @@
%20 = OpLogicalAnd %v3bool %16 %19
%21 = OpLogicalOr %v3bool %11 %20
%9 = OpSelect %v3int %21 %23 %8
%24 = OpSMod %v3int %lhs %9
%24 = OpSRem %v3int %lhs %9
OpReturnValue %24
OpFunctionEnd
%f = OpFunction %void None %25

2
test/tint/expressions/binary/mod_by_zero/by_constant/vec3-vec3/i32.wgsl.expected.spvasm
View File

@@ -41,7 +41,7 @@
%19 = OpLogicalAnd %v3bool %15 %18
%20 = OpLogicalOr %v3bool %10 %19
%8 = OpSelect %v3int %20 %22 %rhs
%23 = OpSMod %v3int %lhs %8
%23 = OpSRem %v3int %lhs %8
OpReturnValue %23
OpFunctionEnd
%f = OpFunction %void None %24