spirv-reader: CFG tests: make valid SPIR-V
Bug: tint:765 Change-Id: I84ea018478feafc4a5c03052832acae8cf3f15b9 Reviewed-on: https://dawn-review.googlesource.com/c/tint/+/49940 Commit-Queue: David Neto <dneto@google.com> Reviewed-by: Alan Baker <alanbaker@google.com>
This commit is contained in:
David Neto
Commit Bot service account
parent
74490e118e
commit
6732e8561c
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@ -46,6 +46,8 @@ std::string CommonTypes() {
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return R"(
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OpCapability Shader
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OpMemoryModel Logical Simple
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OpEntryPoint Fragment %100 "main"
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OpExecutionMode %100 OriginUpperLeft
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OpName %var "var"
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@ -1078,13 +1080,17 @@ TEST_F(SpvParserCFGTest, ComputeBlockOrder_ReorderSequence) {
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%100 = OpFunction %void None %voidfn
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%10 = OpLabel
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OpBranch %20
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OpSelectionMerge %99 None
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OpBranchConditional %cond %20 %30
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%30 = OpLabel
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OpReturn
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%20 = OpLabel
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OpBranch %30 ; backtrack
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OpBranch %30 ; backtrack, but does dominate %30
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%99 = OpLabel
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OpReturn
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OpFunctionEnd
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)"));
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@ -1093,7 +1099,7 @@ TEST_F(SpvParserCFGTest, ComputeBlockOrder_ReorderSequence) {
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fe.RegisterBasicBlocks();
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fe.ComputeBlockOrderAndPositions();
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EXPECT_THAT(fe.block_order(), ElementsAre(10, 20, 30));
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EXPECT_THAT(fe.block_order(), ElementsAre(10, 20, 30, 99));
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const auto* bi10 = fe.GetBlockInfo(10);
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ASSERT_NE(bi10, nullptr);
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@ -1104,6 +1110,9 @@ TEST_F(SpvParserCFGTest, ComputeBlockOrder_ReorderSequence) {
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const auto* bi30 = fe.GetBlockInfo(30);
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ASSERT_NE(bi30, nullptr);
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EXPECT_EQ(bi30->pos, 2u);
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const auto* bi99 = fe.GetBlockInfo(99);
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ASSERT_NE(bi99, nullptr);
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EXPECT_EQ(bi99->pos, 3u);
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}
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TEST_F(SpvParserCFGTest, ComputeBlockOrder_DupConditionalBranch) {
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@ -1114,12 +1123,12 @@ TEST_F(SpvParserCFGTest, ComputeBlockOrder_DupConditionalBranch) {
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OpSelectionMerge %99 None
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OpBranchConditional %cond %20 %20
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%99 = OpLabel
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OpReturn
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%20 = OpLabel
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OpBranch %99
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%99 = OpLabel
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OpReturn
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OpFunctionEnd
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)"));
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ASSERT_TRUE(p->BuildAndParseInternalModuleExceptFunctions()) << p->error();
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@ -1138,15 +1147,15 @@ TEST_F(SpvParserCFGTest, ComputeBlockOrder_RespectConditionalBranchOrder) {
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OpSelectionMerge %99 None
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OpBranchConditional %cond %20 %30
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%99 = OpLabel
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OpReturn
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%30 = OpLabel
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OpReturn
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%20 = OpLabel
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OpBranch %99
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%99 = OpLabel ; dominated by %20, so follow %20
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OpReturn
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OpFunctionEnd
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)"));
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ASSERT_TRUE(p->BuildAndParseInternalModuleExceptFunctions()) << p->error();
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@ -1299,7 +1308,9 @@ TEST_F(SpvParserCFGTest, ComputeBlockOrder_RespectSwitchCaseFallthrough) {
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%10 = OpLabel
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OpSelectionMerge %99 None
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OpSwitch %selector %99 20 %20 30 %30 40 %40 50 %50
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; SPIR-V validation requires a fallthrough destination to immediately
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; follow the source. So %20 -> %40, %30 -> %50
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OpSwitch %selector %99 20 %20 40 %40 30 %30 50 %50
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%50 = OpLabel
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OpBranch %99
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@ -1373,9 +1384,6 @@ TEST_F(SpvParserCFGTest,
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OpSelectionMerge %99 None
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OpSwitch %selector %80 20 %20 30 %30
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%99 = OpLabel
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OpReturn
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%20 = OpLabel
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OpBranch %80 ; fallthrough to default
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@ -1385,6 +1393,9 @@ TEST_F(SpvParserCFGTest,
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%30 = OpLabel
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OpBranch %99
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%99 = OpLabel ; dominated by %30, so follow %30
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OpReturn
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OpFunctionEnd
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)";
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auto p = parser(test::Assemble(assembly));
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@ -1432,6 +1443,9 @@ TEST_F(SpvParserCFGTest,
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EXPECT_THAT(fe.block_order(), ElementsAre(10, 50, 40, 20, 30, 99))
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<< assembly;
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// We're deliberately testing a case that SPIR-V doesn't allow.
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p->DeliberatelyInvalidSpirv();
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}
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TEST_F(SpvParserCFGTest,
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@ -1441,7 +1455,9 @@ TEST_F(SpvParserCFGTest,
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%10 = OpLabel
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OpSelectionMerge %99 None
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OpSwitch %selector %99 20 %20 30 %30 40 %40 50 %50
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; SPIR-V validation requires a fallthrough destination to immediately
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; follow the source. So %20 -> %40
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OpSwitch %selector %99 20 %20 40 %40 30 %30 50 %50
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%99 = OpLabel
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OpReturn
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@ -1641,22 +1657,22 @@ TEST_F(SpvParserCFGTest, ComputeBlockOrder_Nest_IfBreak_In_SwitchCase) {
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OpSelectionMerge %49 None
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OpBranchConditional %cond %99 %40 ; break-if
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%49 = OpLabel
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OpBranch %99
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%40 = OpLabel
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OpBranch %49
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%49 = OpLabel
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OpBranch %99
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%50 = OpLabel
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OpSelectionMerge %79 None
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OpBranchConditional %cond %60 %99 ; break-unless
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%79 = OpLabel
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OpBranch %99
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%60 = OpLabel
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OpBranch %79
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%79 = OpLabel ; dominated by 60, so must follow 60
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OpBranch %99
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OpFunctionEnd
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)";
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auto p = parser(test::Assemble(assembly));
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@ -2184,6 +2200,11 @@ TEST_F(SpvParserCFGTest, ComputeBlockOrder_Loop_Body_Switch_CaseBreaks) {
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EXPECT_THAT(fe.block_order(), ElementsAre(10, 20, 30, 45, 40, 49, 50, 99))
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<< assembly;
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// Fails SPIR-V validation:
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// Branch from block 40 to block 99 is an invalid exit from construct starting
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// at block 30; branch bypasses merge block 49
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p->DeliberatelyInvalidSpirv();
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}
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TEST_F(SpvParserCFGTest, ComputeBlockOrder_Loop_Body_Switch_CaseContinues) {
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@ -2240,6 +2261,7 @@ TEST_F(SpvParserCFGTest, ComputeBlockOrder_Loop_BodyHasSwitchContinueBreak) {
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OpBranchConditional %cond %30 %99
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%30 = OpLabel
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; OpSwitch must be preceded by a selection merge
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OpSwitch %selector %99 50 %50 ; default is break, 50 is continue
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%40 = OpLabel
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@ -2254,12 +2276,10 @@ TEST_F(SpvParserCFGTest, ComputeBlockOrder_Loop_BodyHasSwitchContinueBreak) {
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OpFunctionEnd
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)";
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auto p = parser(test::Assemble(assembly));
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ASSERT_TRUE(p->BuildAndParseInternalModuleExceptFunctions()) << p->error();
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auto fe = p->function_emitter(100);
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fe.RegisterBasicBlocks();
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fe.ComputeBlockOrderAndPositions();
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EXPECT_THAT(fe.block_order(), ElementsAre(10, 20, 30, 50, 99));
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EXPECT_FALSE(p->Parse());
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EXPECT_FALSE(p->success());
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EXPECT_THAT(p->error(),
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HasSubstr("OpSwitch must be preceeded by an OpSelectionMerge"));
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}
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TEST_F(SpvParserCFGTest, ComputeBlockOrder_Loop_Continue_Sequence) {
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@ -2414,7 +2434,9 @@ TEST_F(SpvParserCFGTest, ComputeBlockOrder_Loop_Continue_SwitchBreak) {
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OpBranch %50
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%50 = OpLabel
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OpSwitch %selector %20 99 %99 ; yes, this is obtuse but valid
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; Updated SPIR-V rule:
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; OpSwitch must be preceded by a selection.
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OpSwitch %selector %20 99 %99
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%99 = OpLabel
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OpReturn
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@ -2422,12 +2444,10 @@ TEST_F(SpvParserCFGTest, ComputeBlockOrder_Loop_Continue_SwitchBreak) {
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OpFunctionEnd
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)";
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auto p = parser(test::Assemble(assembly));
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ASSERT_TRUE(p->BuildAndParseInternalModuleExceptFunctions()) << p->error();
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auto fe = p->function_emitter(100);
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fe.RegisterBasicBlocks();
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fe.ComputeBlockOrderAndPositions();
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EXPECT_THAT(fe.block_order(), ElementsAre(10, 20, 30, 50, 99));
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EXPECT_FALSE(p->Parse());
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EXPECT_FALSE(p->success());
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EXPECT_THAT(p->error(),
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HasSubstr("OpSwitch must be preceeded by an OpSelectionMerge"));
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}
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TEST_F(SpvParserCFGTest, ComputeBlockOrder_Loop_Loop) {
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@ -2653,6 +2673,11 @@ TEST_F(SpvParserCFGTest, ComputeBlockOrder_Loop_Loop_InnerContinueContinues) {
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EXPECT_THAT(fe.block_order(),
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ElementsAre(10, 20, 30, 35, 37, 40, 49, 50, 99));
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p->DeliberatelyInvalidSpirv();
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// SPIR-V validation fails:
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// block <ID> 40[%40] exits the continue headed by <ID> 40[%40], but not
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// via a structured exit"
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}
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TEST_F(SpvParserCFGTest, ComputeBlockOrder_Loop_Loop_SwitchBackedgeBreakContinue) {
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@ -2703,6 +2728,11 @@ TEST_F(SpvParserCFGTest, ComputeBlockOrder_Loop_Loop_SwitchBackedgeBreakContinue
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EXPECT_THAT(fe.block_order(),
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ElementsAre(10, 20, 30, 35, 37, 40, 49, 50, 99));
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p->DeliberatelyInvalidSpirv();
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// SPIR-V validation fails:
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// block <ID> 40[%40] exits the continue headed by <ID> 40[%40], but not
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// via a structured exit"
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}
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TEST_F(SpvParserCFGTest, VerifyHeaderContinueMergeOrder_Selection_Good) {
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@ -3178,7 +3208,7 @@ TEST_F(SpvParserCFGTest,
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%20 = OpLabel
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OpLoopMerge %99 %20 None
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OpBranchConditional %cond %30 %99
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OpBranch %30
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%30 = OpLabel
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OpBranch %40
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@ -3187,7 +3217,7 @@ TEST_F(SpvParserCFGTest,
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OpBranch %50
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%50 = OpLabel
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OpBranch %20
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OpBranchConditional %cond %20 %99
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%99 = OpLabel
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OpReturn
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@ -3487,7 +3517,7 @@ TEST_F(SpvParserCFGTest, LabelControlFlowConstructs_Nest_Loop_Loop) {
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%20 = OpLabel
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OpLoopMerge %89 %50 None
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OpBranchConditional %cond %30 %99
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OpBranchConditional %cond %30 %89
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%30 = OpLabel ; single block loop
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OpLoopMerge %40 %30 None
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@ -3650,7 +3680,7 @@ TEST_F(SpvParserCFGTest, LabelControlFlowConstructs_Nest_If_SingleBlockLoop) {
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%20 = OpLabel
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OpLoopMerge %89 %20 None
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OpBranchConditional %cond %20 %99
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OpBranchConditional %cond %20 %89
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%89 = OpLabel
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OpBranch %99
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@ -3702,7 +3732,7 @@ TEST_F(SpvParserCFGTest, LabelControlFlowConstructs_Nest_If_MultiBlockLoop) {
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OpBranch %20
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%89 = OpLabel ; merge for the loop
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OpBranch %20
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OpBranch %99
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%99 = OpLabel ; merge for the if
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OpReturn
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@ -4050,6 +4080,9 @@ TEST_F(SpvParserCFGTest, FindSwitchCaseHeaders_CaseCanBeSwitchMerge) {
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fe.RegisterMerges();
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fe.LabelControlFlowConstructs();
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EXPECT_TRUE(fe.FindSwitchCaseHeaders());
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// TODO(crbug.com/tint/774) Re-enable after codegen bug fixed.
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p->DeliberatelyInvalidSpirv();
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}
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TEST_F(SpvParserCFGTest, FindSwitchCaseHeaders_CaseCantEscapeSwitch) {
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@ -7493,6 +7526,10 @@ TEST_F(SpvParserCFGTest, ClassifyCFGEdges_IfBreak_WithForwardToPremerge) {
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EXPECT_EQ(bi20->succ_edge[99], EdgeKind::kIfBreak);
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EXPECT_THAT(p->error(), Eq(""));
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// TODO(crbug.com/tint/775): The SPIR-V reader errors out on this case.
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// Remove this when it's fixed.
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p->DeliberatelyInvalidSpirv();
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}
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TEST_F(
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@ -10460,7 +10497,7 @@ Return{
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TEST_F(SpvParserCFGTest, EmitBody_ReturnValue_Loop) {
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auto p = parser(test::Assemble(CommonTypes() + R"(
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%200 = OpFunction %void None %voidfn
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%200 = OpFunction %uint None %uintfn
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%210 = OpLabel
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OpBranch %220
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@ -11002,8 +11039,9 @@ TEST_F(
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"(violates post-dominance rule)"));
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}
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TEST_F(SpvParserCFGTest,
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EmitBody_Branch_LoopBreak_MultiBlockLoop_FromContinueConstructEnd) {
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TEST_F(
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SpvParserCFGTest,
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EmitBody_Branch_LoopBreak_MultiBlockLoop_FromContinueConstructEnd_Unconditional) {
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auto p = parser(test::Assemble(CommonTypes() + R"(
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%100 = OpFunction %void None %voidfn
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@ -11017,6 +11055,52 @@ TEST_F(SpvParserCFGTest,
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%80 = OpLabel ; continue target
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OpStore %var %uint_1
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OpBranch %99 ; should be a backedge
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; This is invalid as there must be a backedge to the loop header.
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; The SPIR-V allows this and understands how to emit it, even if it's not
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; permitted by the SPIR-V validator.
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%99 = OpLabel
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OpReturn
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OpFunctionEnd
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)"));
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p->DeliberatelyInvalidSpirv();
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ASSERT_TRUE(p->BuildAndParseInternalModuleExceptFunctions()) << p->error();
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auto fe = p->function_emitter(100);
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EXPECT_TRUE(fe.EmitBody()) << p->error();
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auto got = ToString(p->builder(), fe.ast_body());
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auto* expect = R"(Loop{
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continuing {
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Assignment{
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Identifier[not set]{var_1}
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ScalarConstructor[not set]{1u}
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}
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Break{}
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}
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}
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Return{}
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)";
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ASSERT_EQ(expect, got);
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}
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TEST_F(
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SpvParserCFGTest,
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EmitBody_Branch_LoopBreak_MultiBlockLoop_FromContinueConstructEnd_Conditional) {
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auto p = parser(test::Assemble(CommonTypes() + R"(
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%100 = OpFunction %void None %voidfn
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%10 = OpLabel
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OpBranch %20
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%20 = OpLabel
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OpLoopMerge %99 %80 None
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OpBranch %80
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%80 = OpLabel ; continue target
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OpStore %var %uint_1
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OpBranchConditional %cond %20 %99 ; backedge, and exit
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%99 = OpLabel
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OpReturn
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@ -11033,7 +11117,18 @@ TEST_F(SpvParserCFGTest,
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Identifier[not set]{var_1}
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ScalarConstructor[not set]{1u}
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}
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Break{}
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If{
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(
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ScalarConstructor[not set]{false}
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)
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{
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}
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}
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Else{
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{
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Break{}
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}
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}
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}
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}
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Return{}
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@ -14198,10 +14293,10 @@ TEST_F(SpvParserCFGTest, SiblingLoopConstruct_ContinueIsWholeMultiBlockLoop) {
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%20 = OpLabel
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OpLoopMerge %99 %20 None ; continue target is also loop header
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OpBranchConditional %cond %30 %99
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OpBranch %30
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%30 = OpLabel
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OpBranch %20
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OpBranchConditional %cond %20 %99
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%99 = OpLabel
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OpReturn
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