Also, it's not clear if OpSRem has a direct mapping.
Bug: tint:3
Change-Id: Ie7834253cf14109fbebd2ece8e18d9899b29753b
Reviewed-on: https://dawn-review.googlesource.com/c/tint/+/19881
Reviewed-by: dan sinclair <dsinclair@google.com>
(I expect that) the WGSL signed division operator expects both operands
to be signed and the result will also be signed.
When the operands of a SPIR-V OpSDiv is unsigned, then wrap
the operand in an as-cast to the corresponding signed type.
When the result type of a SPIR-V OpSDiv instruction is unsigned,
we have to wrap the generated WGSL operator with an as-cast to
that unsigned type.
This first CL addresses OpSDiv. We'll address other operations in future CLs.
Bug: tint:3
Change-Id: If3849ceb44b21db87c1efd2c6a2cd63c6d648c88
Reviewed-on: https://dawn-review.googlesource.com/c/tint/+/19800
Reviewed-by: dan sinclair <dsinclair@google.com>
Also adds generic support for generating a combinatorial value
as a const definition.
Bug: tint:3
Change-Id: Idae758d146264491679710967e48ea270436be91
Reviewed-on: https://dawn-review.googlesource.com/c/tint/+/19107
Reviewed-by: dan sinclair <dsinclair@google.com>
