139 lines
4.3 KiB
C++
139 lines
4.3 KiB
C++
// Copyright 2022 The Abseil Authors.
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// https://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#ifndef ABSL_BASE_INTERNAL_PREFETCH_H_
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#define ABSL_BASE_INTERNAL_PREFETCH_H_
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#include "absl/base/config.h"
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#ifdef __SSE__
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#include <xmmintrin.h>
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#endif
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#if defined(_MSC_VER) && defined(ABSL_INTERNAL_HAVE_SSE)
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#include <intrin.h>
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#pragma intrinsic(_mm_prefetch)
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#endif
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// Compatibility wrappers around __builtin_prefetch, to prefetch data
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// for read if supported by the toolchain.
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// Move data into the cache before it is read, or "prefetch" it.
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//
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// The value of `addr` is the address of the memory to prefetch. If
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// the target and compiler support it, data prefetch instructions are
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// generated. If the prefetch is done some time before the memory is
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// read, it may be in the cache by the time the read occurs.
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//
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// The function names specify the temporal locality heuristic applied,
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// using the names of Intel prefetch instructions:
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//
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// T0 - high degree of temporal locality; data should be left in as
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// many levels of the cache possible
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// T1 - moderate degree of temporal locality
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// T2 - low degree of temporal locality
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// Nta - no temporal locality, data need not be left in the cache
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// after the read
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//
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// Incorrect or gratuitous use of these functions can degrade
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// performance, so use them only when representative benchmarks show
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// an improvement.
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//
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// Example usage:
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//
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// absl::base_internal::PrefetchT0(addr);
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//
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// Currently, the different prefetch calls behave on some Intel
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// architectures as follows:
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//
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// SNB..SKL SKX
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// PrefetchT0() L1/L2/L3 L1/L2
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// PrefetchT1() L2/L3 L2
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// PrefetchT2() L2/L3 L2
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// PrefetchNta() L1/--/L3 L1*
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//
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// * On SKX PrefetchNta() will bring the line into L1 but will evict
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// from L3 cache. This might result in surprising behavior.
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//
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// SNB = Sandy Bridge, SKL = Skylake, SKX = Skylake Xeon.
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//
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namespace absl {
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ABSL_NAMESPACE_BEGIN
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namespace base_internal {
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void PrefetchT0(const void* addr);
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void PrefetchT1(const void* addr);
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void PrefetchT2(const void* addr);
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void PrefetchNta(const void* addr);
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// Implementation details follow.
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#if ABSL_HAVE_BUILTIN(__builtin_prefetch) || defined(__GNUC__)
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#define ABSL_INTERNAL_HAVE_PREFETCH 1
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// See __builtin_prefetch:
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// https://gcc.gnu.org/onlinedocs/gcc/Other-Builtins.html.
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//
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// These functions speculatively load for read only. This is
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// safe for all currently supported platforms. However, prefetch for
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// store may have problems depending on the target platform.
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//
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inline void PrefetchT0(const void* addr) {
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// Note: this uses prefetcht0 on Intel.
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__builtin_prefetch(addr, 0, 3);
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}
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inline void PrefetchT1(const void* addr) {
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// Note: this uses prefetcht1 on Intel.
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__builtin_prefetch(addr, 0, 2);
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}
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inline void PrefetchT2(const void* addr) {
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// Note: this uses prefetcht2 on Intel.
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__builtin_prefetch(addr, 0, 1);
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}
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inline void PrefetchNta(const void* addr) {
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// Note: this uses prefetchtnta on Intel.
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__builtin_prefetch(addr, 0, 0);
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}
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#elif defined(ABSL_INTERNAL_HAVE_SSE)
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#define ABSL_INTERNAL_HAVE_PREFETCH 1
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inline void PrefetchT0(const void* addr) {
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_mm_prefetch(reinterpret_cast<const char*>(addr), _MM_HINT_T0);
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}
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inline void PrefetchT1(const void* addr) {
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_mm_prefetch(reinterpret_cast<const char*>(addr), _MM_HINT_T1);
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}
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inline void PrefetchT2(const void* addr) {
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_mm_prefetch(reinterpret_cast<const char*>(addr), _MM_HINT_T2);
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}
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inline void PrefetchNta(const void* addr) {
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_mm_prefetch(reinterpret_cast<const char*>(addr), _MM_HINT_NTA);
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}
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#else
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inline void PrefetchT0(const void*) {}
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inline void PrefetchT1(const void*) {}
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inline void PrefetchT2(const void*) {}
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inline void PrefetchNta(const void*) {}
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#endif
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} // namespace base_internal
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ABSL_NAMESPACE_END
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} // namespace absl
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#endif // ABSL_BASE_INTERNAL_PREFETCH_H_
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