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https://github.com/encounter/objdiff.git
synced 2025-12-19 09:55:28 +00:00
MIPS relocation pairing, '$' prefix option & fixes
Implements MIPS relocation pairing logic. New option for "Register '$' prefix", off by default. Fixes various regressions introduced by refactoring. Resolves #122 Resolves #156
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@@ -1,4 +1,4 @@
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use alloc::{string::ToString, vec::Vec};
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use alloc::{collections::BTreeMap, string::ToString, vec::Vec};
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use core::ops::Range;
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use anyhow::{bail, Result};
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@@ -25,6 +25,7 @@ pub struct ArchMips {
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pub abi: Abi,
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pub isa_extension: Option<IsaExtension>,
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pub ri_gp_value: i32,
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pub paired_relocations: Vec<BTreeMap<u64, i64>>,
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}
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const EF_MIPS_ABI: u32 = 0x0000F000;
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@@ -64,16 +65,60 @@ impl ArchMips {
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// Parse the ri_gp_value stored in .reginfo to be able to correctly
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// calculate R_MIPS_GPREL16 relocations later. The value is stored
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// 0x14 bytes into .reginfo (on 32 bit platforms)
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// 0x14 bytes into .reginfo (on 32-bit platforms)
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let endianness = object.endianness();
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let ri_gp_value = object
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.section_by_name(".reginfo")
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.and_then(|section| section.data().ok())
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.and_then(|data| data.get(0x14..0x18))
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.and_then(|s| s.try_into().ok())
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.map(|bytes| object.endianness().read_i32_bytes(bytes))
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.map(|bytes| endianness.read_i32_bytes(bytes))
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.unwrap_or(0);
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Ok(Self { endianness: object.endianness(), abi, isa_extension, ri_gp_value })
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// Parse all relocations to pair R_MIPS_HI16 and R_MIPS_LO16. Since the instructions only
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// have 16-bit immediate fields, the 32-bit addend is split across the two relocations.
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// R_MIPS_LO16 relocations without an immediately preceding R_MIPS_HI16 use the last seen
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// R_MIPS_HI16 addend.
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// See https://refspecs.linuxfoundation.org/elf/mipsabi.pdf pages 4-17 and 4-18
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let mut paired_relocations = Vec::with_capacity(object.sections().count() + 1);
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for obj_section in object.sections() {
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let data = obj_section.data()?;
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let mut last_hi = None;
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let mut last_hi_addend = 0;
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let mut addends = BTreeMap::new();
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for (addr, reloc) in obj_section.relocations() {
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if !reloc.has_implicit_addend() {
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continue;
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}
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match reloc.flags() {
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object::RelocationFlags::Elf { r_type: elf::R_MIPS_HI16 } => {
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let code = data[addr as usize..addr as usize + 4].try_into()?;
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let addend = ((endianness.read_u32_bytes(code) & 0x0000FFFF) << 16) as i32;
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last_hi = Some(addr);
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last_hi_addend = addend;
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}
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object::RelocationFlags::Elf { r_type: elf::R_MIPS_LO16 } => {
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let code = data[addr as usize..addr as usize + 4].try_into()?;
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let addend = (endianness.read_u32_bytes(code) & 0x0000FFFF) as i16 as i32;
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let full_addend = (last_hi_addend + addend) as i64;
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if let Some(hi_addr) = last_hi.take() {
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addends.insert(hi_addr, full_addend);
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}
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addends.insert(addr, full_addend);
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}
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_ => {
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last_hi = None;
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}
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}
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}
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let section_index = obj_section.index().0;
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if section_index >= paired_relocations.len() {
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paired_relocations.resize_with(section_index + 1, BTreeMap::new);
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}
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paired_relocations[section_index] = addends;
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}
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Ok(Self { endianness, abi, isa_extension, ri_gp_value, paired_relocations })
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}
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fn instruction_flags(&self, diff_config: &DiffObjConfig) -> rabbitizer::InstructionFlags {
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@@ -127,18 +172,16 @@ impl Arch for ArchMips {
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diff_config: &DiffObjConfig,
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) -> Result<Vec<ScannedInstruction>> {
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let instruction_flags = self.instruction_flags(diff_config);
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let start_address = address;
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let mut ops = Vec::<ScannedInstruction>::with_capacity(code.len() / 4);
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let mut cur_addr = start_address as u32;
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let mut cur_addr = address as u32;
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for chunk in code.chunks_exact(4) {
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let code = self.endianness.read_u32_bytes(chunk.try_into()?);
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let vram = Vram::new(cur_addr);
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let instruction = rabbitizer::Instruction::new(code, vram, instruction_flags);
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let instruction =
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rabbitizer::Instruction::new(code, Vram::new(cur_addr), instruction_flags);
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let opcode = instruction.opcode() as u16;
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let branch_dest =
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instruction.get_branch_offset_generic().map(|o| (vram + o).inner() as u64);
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let branch_dest = instruction.get_branch_vram_generic().map(|v| v.inner() as u64);
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ops.push(ScannedInstruction {
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ins_ref: InstructionRef { address, size: 4, opcode },
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ins_ref: InstructionRef { address: cur_addr as u64, size: 4, opcode },
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branch_dest,
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});
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cur_addr += 4;
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@@ -164,6 +207,7 @@ impl Arch for ArchMips {
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function_range,
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resolved.section_index,
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&display_flags,
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diff_config,
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cb,
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)?;
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Ok(())
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@@ -177,6 +221,17 @@ impl Arch for ArchMips {
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reloc: &object::Relocation,
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flags: RelocationFlags,
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) -> Result<i64> {
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// Check for paired R_MIPS_HI16 and R_MIPS_LO16 relocations.
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if let RelocationFlags::Elf(elf::R_MIPS_HI16 | elf::R_MIPS_LO16) = flags {
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if let Some(addend) = self
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.paired_relocations
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.get(section.index().0)
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.and_then(|m| m.get(&address).copied())
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{
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return Ok(addend);
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}
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}
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let data = section.data()?;
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let code = data[address as usize..address as usize + 4].try_into()?;
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let addend = self.endianness.read_u32_bytes(code);
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@@ -246,6 +301,7 @@ fn push_args(
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function_range: Range<u64>,
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section_index: usize,
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display_flags: &rabbitizer::InstructionDisplayFlags,
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diff_config: &DiffObjConfig,
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mut arg_cb: impl FnMut(InstructionPart) -> Result<()>,
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) -> Result<()> {
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let operands = instruction.valued_operands_iter();
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@@ -305,9 +361,14 @@ fn push_args(
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})))?;
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}
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arg_cb(InstructionPart::basic("("))?;
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arg_cb(InstructionPart::opaque(
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base.either_name(instruction.flags().abi(), display_flags.named_gpr()),
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))?;
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let mut value =
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base.either_name(instruction.flags().abi(), display_flags.named_gpr());
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if !diff_config.mips_register_prefix {
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if let Some(trimmed) = value.strip_prefix('$') {
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value = trimmed;
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}
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}
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arg_cb(InstructionPart::opaque(value))?;
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arg_cb(InstructionPart::basic(")"))?;
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}
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// ValuedOperand::r5900_immediate15(..) => match relocation {
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@@ -321,9 +382,14 @@ fn push_args(
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// }
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// },
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_ => {
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arg_cb(InstructionPart::opaque(
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op.display(instruction, display_flags, None::<&str>).to_string(),
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))?;
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let value = op.display(instruction, display_flags, None::<&str>).to_string();
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if !diff_config.mips_register_prefix {
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if let Some(value) = value.strip_prefix('$') {
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arg_cb(InstructionPart::opaque(value))?;
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continue;
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}
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}
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arg_cb(InstructionPart::opaque(value))?;
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}
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}
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}
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