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Use let chains (a.k.a. cargo clippy --fix)

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This commit is contained in:
Luke Street
2025-08-02 11:26:59 -06:00
parent 0dc123b064
commit c9c3b32376
17 changed files with 507 additions and 507 deletions
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548
objdiff-core/src/arch/arm64.rs
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@@ -509,25 +509,25 @@ where Cb: FnMut(InstructionPart<'static>) {
return "ubfx";
}
Opcode::SBFM => {
if let Operand::Immediate(63) = ins.operands[3] {
if let Operand::Register(SizeCode::X, _) = ins.operands[0] {
push_operand(args, &ins.operands[0], ctx);
push_separator(args);
push_operand(args, &ins.operands[1], ctx);
push_separator(args);
push_operand(args, &ins.operands[2], ctx);
return "asr";
}
if let Operand::Immediate(63) = ins.operands[3]
&& let Operand::Register(SizeCode::X, _) = ins.operands[0]
{
push_operand(args, &ins.operands[0], ctx);
push_separator(args);
push_operand(args, &ins.operands[1], ctx);
push_separator(args);
push_operand(args, &ins.operands[2], ctx);
return "asr";
}
if let Operand::Immediate(31) = ins.operands[3] {
if let Operand::Register(SizeCode::W, _) = ins.operands[0] {
push_operand(args, &ins.operands[0], ctx);
push_separator(args);
push_operand(args, &ins.operands[1], ctx);
push_separator(args);
push_operand(args, &ins.operands[2], ctx);
return "asr";
}
if let Operand::Immediate(31) = ins.operands[3]
&& let Operand::Register(SizeCode::W, _) = ins.operands[0]
{
push_operand(args, &ins.operands[0], ctx);
push_separator(args);
push_operand(args, &ins.operands[1], ctx);
push_separator(args);
push_operand(args, &ins.operands[2], ctx);
return "asr";
}
if let Operand::Immediate(0) = ins.operands[2] {
let newsrc = if let Operand::Register(_size, srcnum) = ins.operands[1] {
@@ -554,22 +554,21 @@ where Cb: FnMut(InstructionPart<'static>) {
}
if let (Operand::Immediate(imms), Operand::Immediate(immr)) =
(ins.operands[2], ins.operands[3])
&& immr < imms
{
if immr < imms {
let size = if let Operand::Register(size, _) = ins.operands[0] {
if size == SizeCode::W { 32 } else { 64 }
} else {
unreachable!("operand 0 is always a register");
};
push_operand(args, &ins.operands[0], ctx);
push_separator(args);
push_operand(args, &ins.operands[1], ctx);
push_separator(args);
push_unsigned(args, (size - imms) as u64);
push_separator(args);
push_unsigned(args, (immr + 1) as u64);
return "sbfiz";
}
let size = if let Operand::Register(size, _) = ins.operands[0] {
if size == SizeCode::W { 32 } else { 64 }
} else {
unreachable!("operand 0 is always a register");
};
push_operand(args, &ins.operands[0], ctx);
push_separator(args);
push_operand(args, &ins.operands[1], ctx);
push_separator(args);
push_unsigned(args, (size - imms) as u64);
push_separator(args);
push_unsigned(args, (immr + 1) as u64);
return "sbfiz";
}
// `sbfm` is never actually displayed: in the remaining case, it is always aliased to `sbfx`
let width = if let (Operand::Immediate(lsb), Operand::Immediate(width)) =
@@ -593,15 +592,14 @@ where Cb: FnMut(InstructionPart<'static>) {
Opcode::EXTR => {
if let (Operand::Register(_, rn), Operand::Register(_, rm)) =
(ins.operands[1], ins.operands[2])
&& rn == rm
{
if rn == rm {
push_operand(args, &ins.operands[0], ctx);
push_separator(args);
push_operand(args, &ins.operands[2], ctx);
push_separator(args);
push_operand(args, &ins.operands[3], ctx);
return "ror";
}
push_operand(args, &ins.operands[0], ctx);
push_separator(args);
push_operand(args, &ins.operands[2], ctx);
push_separator(args);
push_operand(args, &ins.operands[3], ctx);
return "ror";
}
"extr"
}
@@ -804,27 +802,24 @@ where Cb: FnMut(InstructionPart<'static>) {
"csneg"
}
Opcode::CSINC => {
if let (
Operand::Register(_, n),
Operand::Register(_, m),
Operand::ConditionCode(cond),
) = (ins.operands[1], ins.operands[2], ins.operands[3])
if let (Operand::Register(_, n), Operand::Register(_, m), Operand::ConditionCode(cond)) =
(ins.operands[1], ins.operands[2], ins.operands[3])
&& n == m
&& cond < 0b1110
{
if n == m && cond < 0b1110 {
return if n == 31 {
push_operand(args, &ins.operands[0], ctx);
push_separator(args);
push_condition_code(args, cond ^ 0x01);
"cset"
} else {
push_operand(args, &ins.operands[0], ctx);
push_separator(args);
push_operand(args, &ins.operands[1], ctx);
push_separator(args);
push_condition_code(args, cond ^ 0x01);
"cinc"
};
}
return if n == 31 {
push_operand(args, &ins.operands[0], ctx);
push_separator(args);
push_condition_code(args, cond ^ 0x01);
"cset"
} else {
push_operand(args, &ins.operands[0], ctx);
push_separator(args);
push_operand(args, &ins.operands[1], ctx);
push_separator(args);
push_condition_code(args, cond ^ 0x01);
"cinc"
};
}
"csinc"
}
@@ -1200,15 +1195,13 @@ where Cb: FnMut(InstructionPart<'static>) {
Operand::Register(reg_sz, _),
Operand::SIMDRegisterElementsLane(_, _, elem_sz, _),
) = (ins.operands[0], ins.operands[1])
&& ((reg_sz == SizeCode::W && elem_sz == SIMDSizeCode::S)
|| (reg_sz == SizeCode::X && elem_sz == SIMDSizeCode::D))
{
if (reg_sz == SizeCode::W && elem_sz == SIMDSizeCode::S)
|| (reg_sz == SizeCode::X && elem_sz == SIMDSizeCode::D)
{
push_operand(args, &ins.operands[0], ctx);
push_separator(args);
push_operand(args, &ins.operands[1], ctx);
return "mov";
}
push_operand(args, &ins.operands[0], ctx);
push_separator(args);
push_operand(args, &ins.operands[1], ctx);
return "mov";
}
"umov"
}
@@ -1308,14 +1301,15 @@ where Cb: FnMut(InstructionPart<'static>) {
}
}
Opcode::LDADDB(ar) => {
if let Operand::Register(_, rt) = ins.operands[1] {
if rt == 31 && ar & 0b10 == 0b00 {
let inst = if ar & 0b01 == 0b00 { "staddb" } else { "staddlb" };
push_operand(args, &ins.operands[0], ctx);
push_separator(args);
push_operand(args, &ins.operands[2], ctx);
return inst;
}
if let Operand::Register(_, rt) = ins.operands[1]
&& rt == 31
&& ar & 0b10 == 0b00
{
let inst = if ar & 0b01 == 0b00 { "staddb" } else { "staddlb" };
push_operand(args, &ins.operands[0], ctx);
push_separator(args);
push_operand(args, &ins.operands[2], ctx);
return inst;
}
if ar == 0 {
"ldaddb"
@@ -1328,14 +1322,15 @@ where Cb: FnMut(InstructionPart<'static>) {
}
}
Opcode::LDCLRB(ar) => {
if let Operand::Register(_, rt) = ins.operands[1] {
if rt == 31 && ar & 0b10 == 0b00 {
let inst = if ar & 0b01 == 0b00 { "stclrb" } else { "stclrlb" };
push_operand(args, &ins.operands[0], ctx);
push_separator(args);
push_operand(args, &ins.operands[2], ctx);
return inst;
}
if let Operand::Register(_, rt) = ins.operands[1]
&& rt == 31
&& ar & 0b10 == 0b00
{
let inst = if ar & 0b01 == 0b00 { "stclrb" } else { "stclrlb" };
push_operand(args, &ins.operands[0], ctx);
push_separator(args);
push_operand(args, &ins.operands[2], ctx);
return inst;
}
if ar == 0 {
"ldclrb"
@@ -1348,14 +1343,15 @@ where Cb: FnMut(InstructionPart<'static>) {
}
}
Opcode::LDEORB(ar) => {
if let Operand::Register(_, rt) = ins.operands[1] {
if rt == 31 && ar & 0b10 == 0b00 {
let inst = if ar & 0b01 == 0b00 { "steorb" } else { "steorlb" };
push_operand(args, &ins.operands[0], ctx);
push_separator(args);
push_operand(args, &ins.operands[2], ctx);
return inst;
}
if let Operand::Register(_, rt) = ins.operands[1]
&& rt == 31
&& ar & 0b10 == 0b00
{
let inst = if ar & 0b01 == 0b00 { "steorb" } else { "steorlb" };
push_operand(args, &ins.operands[0], ctx);
push_separator(args);
push_operand(args, &ins.operands[2], ctx);
return inst;
}
if ar == 0 {
"ldeorb"
@@ -1368,14 +1364,15 @@ where Cb: FnMut(InstructionPart<'static>) {
}
}
Opcode::LDSETB(ar) => {
if let Operand::Register(_, rt) = ins.operands[1] {
if rt == 31 && ar & 0b10 == 0b00 {
let inst = if ar & 0b01 == 0b00 { "stsetb" } else { "stsetlb" };
push_operand(args, &ins.operands[0], ctx);
push_separator(args);
push_operand(args, &ins.operands[2], ctx);
return inst;
}
if let Operand::Register(_, rt) = ins.operands[1]
&& rt == 31
&& ar & 0b10 == 0b00
{
let inst = if ar & 0b01 == 0b00 { "stsetb" } else { "stsetlb" };
push_operand(args, &ins.operands[0], ctx);
push_separator(args);
push_operand(args, &ins.operands[2], ctx);
return inst;
}
if ar == 0 {
"ldsetb"
@@ -1388,14 +1385,15 @@ where Cb: FnMut(InstructionPart<'static>) {
}
}
Opcode::LDSMAXB(ar) => {
if let Operand::Register(_, rt) = ins.operands[1] {
if rt == 31 && ar & 0b10 == 0b00 {
let inst = if ar & 0b01 == 0b00 { "stsmaxb" } else { "stsmaxlb" };
push_operand(args, &ins.operands[0], ctx);
push_separator(args);
push_operand(args, &ins.operands[2], ctx);
return inst;
}
if let Operand::Register(_, rt) = ins.operands[1]
&& rt == 31
&& ar & 0b10 == 0b00
{
let inst = if ar & 0b01 == 0b00 { "stsmaxb" } else { "stsmaxlb" };
push_operand(args, &ins.operands[0], ctx);
push_separator(args);
push_operand(args, &ins.operands[2], ctx);
return inst;
}
if ar == 0 {
"ldsmaxb"
@@ -1408,14 +1406,15 @@ where Cb: FnMut(InstructionPart<'static>) {
}
}
Opcode::LDSMINB(ar) => {
if let Operand::Register(_, rt) = ins.operands[1] {
if rt == 31 && ar & 0b10 == 0b00 {
let inst = if ar & 0b01 == 0b00 { "stsminb" } else { "stsminlb" };
push_operand(args, &ins.operands[0], ctx);
push_separator(args);
push_operand(args, &ins.operands[2], ctx);
return inst;
}
if let Operand::Register(_, rt) = ins.operands[1]
&& rt == 31
&& ar & 0b10 == 0b00
{
let inst = if ar & 0b01 == 0b00 { "stsminb" } else { "stsminlb" };
push_operand(args, &ins.operands[0], ctx);
push_separator(args);
push_operand(args, &ins.operands[2], ctx);
return inst;
}
if ar == 0 {
"ldsminb"
@@ -1428,14 +1427,15 @@ where Cb: FnMut(InstructionPart<'static>) {
}
}
Opcode::LDUMAXB(ar) => {
if let Operand::Register(_, rt) = ins.operands[1] {
if rt == 31 && ar & 0b10 == 0b00 {
let inst = if ar & 0b01 == 0b00 { "stumaxb" } else { "stumaxlb" };
push_operand(args, &ins.operands[0], ctx);
push_separator(args);
push_operand(args, &ins.operands[2], ctx);
return inst;
}
if let Operand::Register(_, rt) = ins.operands[1]
&& rt == 31
&& ar & 0b10 == 0b00
{
let inst = if ar & 0b01 == 0b00 { "stumaxb" } else { "stumaxlb" };
push_operand(args, &ins.operands[0], ctx);
push_separator(args);
push_operand(args, &ins.operands[2], ctx);
return inst;
}
if ar == 0 {
"ldumaxb"
@@ -1448,14 +1448,15 @@ where Cb: FnMut(InstructionPart<'static>) {
}
}
Opcode::LDUMINB(ar) => {
if let Operand::Register(_, rt) = ins.operands[1] {
if rt == 31 && ar & 0b10 == 0b00 {
let inst = if ar & 0b01 == 0b00 { "stuminb" } else { "stuminlb" };
push_operand(args, &ins.operands[0], ctx);
push_separator(args);
push_operand(args, &ins.operands[2], ctx);
return inst;
}
if let Operand::Register(_, rt) = ins.operands[1]
&& rt == 31
&& ar & 0b10 == 0b00
{
let inst = if ar & 0b01 == 0b00 { "stuminb" } else { "stuminlb" };
push_operand(args, &ins.operands[0], ctx);
push_separator(args);
push_operand(args, &ins.operands[2], ctx);
return inst;
}
// write!(fmt, "{}", self.opcode)?;
if ar == 0 {
@@ -1469,14 +1470,15 @@ where Cb: FnMut(InstructionPart<'static>) {
}
}
Opcode::LDADDH(ar) => {
if let Operand::Register(_, rt) = ins.operands[1] {
if rt == 31 && ar & 0b10 == 0b00 {
let inst = if ar & 0b01 == 0b00 { "staddh" } else { "staddlh" };
push_operand(args, &ins.operands[0], ctx);
push_separator(args);
push_operand(args, &ins.operands[2], ctx);
return inst;
}
if let Operand::Register(_, rt) = ins.operands[1]
&& rt == 31
&& ar & 0b10 == 0b00
{
let inst = if ar & 0b01 == 0b00 { "staddh" } else { "staddlh" };
push_operand(args, &ins.operands[0], ctx);
push_separator(args);
push_operand(args, &ins.operands[2], ctx);
return inst;
}
if ar == 0 {
"ldaddh"
@@ -1489,14 +1491,15 @@ where Cb: FnMut(InstructionPart<'static>) {
}
}
Opcode::LDCLRH(ar) => {
if let Operand::Register(_, rt) = ins.operands[1] {
if rt == 31 && ar & 0b10 == 0b00 {
let inst = if ar & 0b01 == 0b00 { "stclrh" } else { "stclrlh" };
push_operand(args, &ins.operands[0], ctx);
push_separator(args);
push_operand(args, &ins.operands[2], ctx);
return inst;
}
if let Operand::Register(_, rt) = ins.operands[1]
&& rt == 31
&& ar & 0b10 == 0b00
{
let inst = if ar & 0b01 == 0b00 { "stclrh" } else { "stclrlh" };
push_operand(args, &ins.operands[0], ctx);
push_separator(args);
push_operand(args, &ins.operands[2], ctx);
return inst;
}
if ar == 0 {
"ldclrh"
@@ -1509,14 +1512,15 @@ where Cb: FnMut(InstructionPart<'static>) {
}
}
Opcode::LDEORH(ar) => {
if let Operand::Register(_, rt) = ins.operands[1] {
if rt == 31 && ar & 0b10 == 0b00 {
let inst = if ar & 0b01 == 0b00 { "steorh" } else { "steorlh" };
push_operand(args, &ins.operands[0], ctx);
push_separator(args);
push_operand(args, &ins.operands[2], ctx);
return inst;
}
if let Operand::Register(_, rt) = ins.operands[1]
&& rt == 31
&& ar & 0b10 == 0b00
{
let inst = if ar & 0b01 == 0b00 { "steorh" } else { "steorlh" };
push_operand(args, &ins.operands[0], ctx);
push_separator(args);
push_operand(args, &ins.operands[2], ctx);
return inst;
}
if ar == 0 {
"ldeorh"
@@ -1529,14 +1533,15 @@ where Cb: FnMut(InstructionPart<'static>) {
}
}
Opcode::LDSETH(ar) => {
if let Operand::Register(_, rt) = ins.operands[1] {
if rt == 31 && ar & 0b10 == 0b00 {
let inst = if ar & 0b01 == 0b00 { "stseth" } else { "stsetlh" };
push_operand(args, &ins.operands[0], ctx);
push_separator(args);
push_operand(args, &ins.operands[2], ctx);
return inst;
}
if let Operand::Register(_, rt) = ins.operands[1]
&& rt == 31
&& ar & 0b10 == 0b00
{
let inst = if ar & 0b01 == 0b00 { "stseth" } else { "stsetlh" };
push_operand(args, &ins.operands[0], ctx);
push_separator(args);
push_operand(args, &ins.operands[2], ctx);
return inst;
}
if ar == 0 {
"ldseth"
@@ -1549,14 +1554,15 @@ where Cb: FnMut(InstructionPart<'static>) {
}
}
Opcode::LDSMAXH(ar) => {
if let Operand::Register(_, rt) = ins.operands[1] {
if rt == 31 && ar & 0b10 == 0b00 {
let inst = if ar & 0b01 == 0b00 { "stsmaxh" } else { "stsmaxlh" };
push_operand(args, &ins.operands[0], ctx);
push_separator(args);
push_operand(args, &ins.operands[2], ctx);
return inst;
}
if let Operand::Register(_, rt) = ins.operands[1]
&& rt == 31
&& ar & 0b10 == 0b00
{
let inst = if ar & 0b01 == 0b00 { "stsmaxh" } else { "stsmaxlh" };
push_operand(args, &ins.operands[0], ctx);
push_separator(args);
push_operand(args, &ins.operands[2], ctx);
return inst;
}
if ar == 0 {
"ldsmaxh"
@@ -1569,14 +1575,15 @@ where Cb: FnMut(InstructionPart<'static>) {
}
}
Opcode::LDSMINH(ar) => {
if let Operand::Register(_, rt) = ins.operands[1] {
if rt == 31 && ar & 0b10 == 0b00 {
let inst = if ar & 0b01 == 0b00 { "stsminh" } else { "stsminlh" };
push_operand(args, &ins.operands[0], ctx);
push_separator(args);
push_operand(args, &ins.operands[2], ctx);
return inst;
}
if let Operand::Register(_, rt) = ins.operands[1]
&& rt == 31
&& ar & 0b10 == 0b00
{
let inst = if ar & 0b01 == 0b00 { "stsminh" } else { "stsminlh" };
push_operand(args, &ins.operands[0], ctx);
push_separator(args);
push_operand(args, &ins.operands[2], ctx);
return inst;
}
if ar == 0 {
"ldsminh"
@@ -1589,14 +1596,15 @@ where Cb: FnMut(InstructionPart<'static>) {
}
}
Opcode::LDUMAXH(ar) => {
if let Operand::Register(_, rt) = ins.operands[1] {
if rt == 31 && ar & 0b10 == 0b00 {
let inst = if ar & 0b01 == 0b00 { "stumaxh" } else { "stumaxlh" };
push_operand(args, &ins.operands[0], ctx);
push_separator(args);
push_operand(args, &ins.operands[2], ctx);
return inst;
}
if let Operand::Register(_, rt) = ins.operands[1]
&& rt == 31
&& ar & 0b10 == 0b00
{
let inst = if ar & 0b01 == 0b00 { "stumaxh" } else { "stumaxlh" };
push_operand(args, &ins.operands[0], ctx);
push_separator(args);
push_operand(args, &ins.operands[2], ctx);
return inst;
}
if ar == 0 {
"ldumaxh"
@@ -1609,14 +1617,15 @@ where Cb: FnMut(InstructionPart<'static>) {
}
}
Opcode::LDUMINH(ar) => {
if let Operand::Register(_, rt) = ins.operands[1] {
if rt == 31 && ar & 0b10 == 0b00 {
let inst = if ar & 0b01 == 0b00 { "stuminh" } else { "stuminlh" };
push_operand(args, &ins.operands[0], ctx);
push_separator(args);
push_operand(args, &ins.operands[2], ctx);
return inst;
}
if let Operand::Register(_, rt) = ins.operands[1]
&& rt == 31
&& ar & 0b10 == 0b00
{
let inst = if ar & 0b01 == 0b00 { "stuminh" } else { "stuminlh" };
push_operand(args, &ins.operands[0], ctx);
push_separator(args);
push_operand(args, &ins.operands[2], ctx);
return inst;
}
if ar == 0 {
"lduminh"
@@ -1629,14 +1638,15 @@ where Cb: FnMut(InstructionPart<'static>) {
}
}
Opcode::LDADD(ar) => {
if let Operand::Register(_, rt) = ins.operands[1] {
if rt == 31 && ar & 0b10 == 0b00 {
let inst = if ar & 0b01 == 0b00 { "stadd" } else { "staddl" };
push_operand(args, &ins.operands[0], ctx);
push_separator(args);
push_operand(args, &ins.operands[2], ctx);
return inst;
}
if let Operand::Register(_, rt) = ins.operands[1]
&& rt == 31
&& ar & 0b10 == 0b00
{
let inst = if ar & 0b01 == 0b00 { "stadd" } else { "staddl" };
push_operand(args, &ins.operands[0], ctx);
push_separator(args);
push_operand(args, &ins.operands[2], ctx);
return inst;
}
if ar == 0 {
"ldadd"
@@ -1649,14 +1659,15 @@ where Cb: FnMut(InstructionPart<'static>) {
}
}
Opcode::LDCLR(ar) => {
if let Operand::Register(_, rt) = ins.operands[1] {
if rt == 31 && ar & 0b10 == 0b00 {
let inst = if ar & 0b01 == 0b00 { "stclr" } else { "stclrl" };
push_operand(args, &ins.operands[0], ctx);
push_separator(args);
push_operand(args, &ins.operands[2], ctx);
return inst;
}
if let Operand::Register(_, rt) = ins.operands[1]
&& rt == 31
&& ar & 0b10 == 0b00
{
let inst = if ar & 0b01 == 0b00 { "stclr" } else { "stclrl" };
push_operand(args, &ins.operands[0], ctx);
push_separator(args);
push_operand(args, &ins.operands[2], ctx);
return inst;
}
if ar == 0 {
"ldclr"
@@ -1669,14 +1680,15 @@ where Cb: FnMut(InstructionPart<'static>) {
}
}
Opcode::LDEOR(ar) => {
if let Operand::Register(_, rt) = ins.operands[1] {
if rt == 31 && ar & 0b10 == 0b00 {
let inst = if ar & 0b01 == 0b00 { "steor" } else { "steorl" };
push_operand(args, &ins.operands[0], ctx);
push_separator(args);
push_operand(args, &ins.operands[2], ctx);
return inst;
}
if let Operand::Register(_, rt) = ins.operands[1]
&& rt == 31
&& ar & 0b10 == 0b00
{
let inst = if ar & 0b01 == 0b00 { "steor" } else { "steorl" };
push_operand(args, &ins.operands[0], ctx);
push_separator(args);
push_operand(args, &ins.operands[2], ctx);
return inst;
}
if ar == 0 {
"ldeor"
@@ -1689,14 +1701,15 @@ where Cb: FnMut(InstructionPart<'static>) {
}
}
Opcode::LDSET(ar) => {
if let Operand::Register(_, rt) = ins.operands[1] {
if rt == 31 && ar & 0b10 == 0b00 {
let inst = if ar & 0b01 == 0b00 { "stset" } else { "stsetl" };
push_operand(args, &ins.operands[0], ctx);
push_separator(args);
push_operand(args, &ins.operands[2], ctx);
return inst;
}
if let Operand::Register(_, rt) = ins.operands[1]
&& rt == 31
&& ar & 0b10 == 0b00
{
let inst = if ar & 0b01 == 0b00 { "stset" } else { "stsetl" };
push_operand(args, &ins.operands[0], ctx);
push_separator(args);
push_operand(args, &ins.operands[2], ctx);
return inst;
}
if ar == 0 {
"ldset"
@@ -1709,14 +1722,15 @@ where Cb: FnMut(InstructionPart<'static>) {
}
}
Opcode::LDSMAX(ar) => {
if let Operand::Register(_, rt) = ins.operands[1] {
if rt == 31 && ar & 0b10 == 0b00 {
let inst = if ar & 0b01 == 0b00 { "stsmax" } else { "stsmaxl" };
push_operand(args, &ins.operands[0], ctx);
push_separator(args);
push_operand(args, &ins.operands[2], ctx);
return inst;
}
if let Operand::Register(_, rt) = ins.operands[1]
&& rt == 31
&& ar & 0b10 == 0b00
{
let inst = if ar & 0b01 == 0b00 { "stsmax" } else { "stsmaxl" };
push_operand(args, &ins.operands[0], ctx);
push_separator(args);
push_operand(args, &ins.operands[2], ctx);
return inst;
}
if ar == 0 {
"ldsmax"
@@ -1729,14 +1743,15 @@ where Cb: FnMut(InstructionPart<'static>) {
}
}
Opcode::LDSMIN(ar) => {
if let Operand::Register(_, rt) = ins.operands[1] {
if rt == 31 && ar & 0b10 == 0b00 {
let inst = if ar & 0b01 == 0b00 { "stsmin" } else { "stsminl" };
push_operand(args, &ins.operands[0], ctx);
push_separator(args);
push_operand(args, &ins.operands[2], ctx);
return inst;
}
if let Operand::Register(_, rt) = ins.operands[1]
&& rt == 31
&& ar & 0b10 == 0b00
{
let inst = if ar & 0b01 == 0b00 { "stsmin" } else { "stsminl" };
push_operand(args, &ins.operands[0], ctx);
push_separator(args);
push_operand(args, &ins.operands[2], ctx);
return inst;
}
if ar == 0 {
"ldsmin"
@@ -1749,14 +1764,15 @@ where Cb: FnMut(InstructionPart<'static>) {
}
}
Opcode::LDUMAX(ar) => {
if let Operand::Register(_, rt) = ins.operands[1] {
if rt == 31 && ar & 0b10 == 0b00 {
let inst = if ar & 0b01 == 0b00 { "stumax" } else { "stumaxl" };
push_operand(args, &ins.operands[0], ctx);
push_separator(args);
push_operand(args, &ins.operands[2], ctx);
return inst;
}
if let Operand::Register(_, rt) = ins.operands[1]
&& rt == 31
&& ar & 0b10 == 0b00
{
let inst = if ar & 0b01 == 0b00 { "stumax" } else { "stumaxl" };
push_operand(args, &ins.operands[0], ctx);
push_separator(args);
push_operand(args, &ins.operands[2], ctx);
return inst;
}
if ar == 0 {
"ldumax"
@@ -1769,14 +1785,15 @@ where Cb: FnMut(InstructionPart<'static>) {
}
}
Opcode::LDUMIN(ar) => {
if let Operand::Register(_, rt) = ins.operands[1] {
if rt == 31 && ar & 0b10 == 0b00 {
let inst = if ar & 0b01 == 0b00 { "stumin" } else { "stuminl" };
push_operand(args, &ins.operands[0], ctx);
push_separator(args);
push_operand(args, &ins.operands[2], ctx);
return inst;
}
if let Operand::Register(_, rt) = ins.operands[1]
&& rt == 31
&& ar & 0b10 == 0b00
{
let inst = if ar & 0b01 == 0b00 { "stumin" } else { "stuminl" };
push_operand(args, &ins.operands[0], ctx);
push_separator(args);
push_operand(args, &ins.operands[2], ctx);
return inst;
}
if ar == 0 {
"ldumin"
@@ -2067,16 +2084,15 @@ where Cb: FnMut(InstructionPart<'static>) {
/// Relocations that appear in Operand::PCOffset.
fn is_pc_offset_reloc(reloc: Option<ResolvedRelocation>) -> Option<ResolvedRelocation> {
if let Some(resolved) = reloc {
if let RelocationFlags::Elf(
if let Some(resolved) = reloc
&& let RelocationFlags::Elf(
elf::R_AARCH64_ADR_PREL_PG_HI21
| elf::R_AARCH64_JUMP26
| elf::R_AARCH64_CALL26
| elf::R_AARCH64_ADR_GOT_PAGE,
) = resolved.relocation.flags
{
return Some(resolved);
}
{
return Some(resolved);
}
None
}

15
objdiff-core/src/arch/mips.rs
View File

@@ -242,17 +242,16 @@ impl Arch for ArchMips {
object::RelocationFlags::Elf { r_type } => {
if relocation.has_implicit_addend() {
// Check for paired R_MIPS_HI16 and R_MIPS_LO16 relocations.
if let elf::R_MIPS_HI16 | elf::R_MIPS_LO16 = r_type {
if let Some(addend) = self
if let elf::R_MIPS_HI16 | elf::R_MIPS_LO16 = r_type
&& let Some(addend) = self
.paired_relocations
.get(section.index().0)
.and_then(|m| m.get(&address).copied())
{
return Ok(Some(RelocationOverride {
target: RelocationOverrideTarget::Keep,
addend,
}));
}
{
return Ok(Some(RelocationOverride {
target: RelocationOverrideTarget::Keep,
addend,
}));
}
let data = section.data()?;

8
objdiff-core/src/arch/mod.rs
View File

@@ -215,10 +215,10 @@ impl dyn Arch {
// Remove any branch destinations that are outside the function range
for ins in result.iter_mut() {
if let Some(branch_dest) = ins.branch_dest {
if branch_dest < function_start || branch_dest >= function_end {
ins.branch_dest = None;
}
if let Some(branch_dest) = ins.branch_dest
&& (branch_dest < function_start || branch_dest >= function_end)
{
ins.branch_dest = None;
}
}

38
objdiff-core/src/arch/ppc/flow_analysis.rs
View File

@@ -514,14 +514,14 @@ pub fn ppc_data_flow_analysis(
}
fn get_string_data(obj: &Object, symbol_index: usize, offset: Simm) -> Option<&str> {
if let Some(sym) = obj.symbols.get(symbol_index) {
if sym.name.starts_with("@stringBase") && offset.0 != 0 {
if let Some(data) = obj.symbol_data(symbol_index) {
let bytes = &data[offset.0 as usize..];
if let Ok(Ok(str)) = CStr::from_bytes_until_nul(bytes).map(|x| x.to_str()) {
return Some(str);
}
}
if let Some(sym) = obj.symbols.get(symbol_index)
&& sym.name.starts_with("@stringBase")
&& offset.0 != 0
&& let Some(data) = obj.symbol_data(symbol_index)
{
let bytes = &data[offset.0 as usize..];
if let Ok(Ok(str)) = CStr::from_bytes_until_nul(bytes).map(|x| x.to_str()) {
return Some(str);
}
}
None
@@ -577,19 +577,17 @@ fn generate_flow_analysis_result(
let registers = register_state_at.get(index as usize).unwrap_or(&default_register_state);
if let (powerpc::Opcode::Addi, Argument::GPR(rel), Argument::Simm(offset)) =
(ins.op, args[1], args[2])
&& let RegisterContent::Symbol(sym_index) = registers[rel]
&& let Some(str) = get_string_data(obj, sym_index, offset)
{
if let RegisterContent::Symbol(sym_index) = registers[rel] {
if let Some(str) = get_string_data(obj, sym_index, offset) {
// Show the string constant in the analysis result
let formatted = format!("\"{str}\"");
analysis_result.set_argument_value_at_address(
ins_address,
2,
FlowAnalysisValue::Text(clamp_text_length(formatted, 20)),
);
// Don't continue, we want to show the stringbase value as well
}
}
// Show the string constant in the analysis result
let formatted = format!("\"{str}\"");
analysis_result.set_argument_value_at_address(
ins_address,
2,
FlowAnalysisValue::Text(clamp_text_length(formatted, 20)),
);
// Don't continue, we want to show the stringbase value as well
}
let is_store = is_store_instruction(ins.op);

59
objdiff-core/src/arch/ppc/mod.rs
View File

@@ -866,44 +866,43 @@ fn generate_fake_pool_relocations_for_function(
break;
}
}
if let Some(branch_dest) = branch_dest {
if branch_dest >= func_address as u32
&& (branch_dest - func_address as u32) < code.len() as u32
{
let dest_offset_into_func = branch_dest - func_address as u32;
let dest_code_slice = &code[dest_offset_into_func as usize..];
match ins.op {
Opcode::Bc => {
// Conditional branch.
// Add the branch destination to the queue to do later.
if let Some(branch_dest) = branch_dest
&& branch_dest >= func_address as u32
&& (branch_dest - func_address as u32) < code.len() as u32
{
let dest_offset_into_func = branch_dest - func_address as u32;
let dest_code_slice = &code[dest_offset_into_func as usize..];
match ins.op {
Opcode::Bc => {
// Conditional branch.
// Add the branch destination to the queue to do later.
ins_iters_with_gpr_state.push((
InsIter::new(dest_code_slice, branch_dest, extensions),
gpr_pool_relocs.clone(),
));
// Then continue on with the current iterator.
}
Opcode::B => {
if simplified.mnemonic != "bl" {
// Unconditional branch.
// Add the branch destination to the queue.
ins_iters_with_gpr_state.push((
InsIter::new(dest_code_slice, branch_dest, extensions),
gpr_pool_relocs.clone(),
));
// Then continue on with the current iterator.
// Break out of the current iterator so we can do the newly added one.
break;
}
Opcode::B => {
if simplified.mnemonic != "bl" {
// Unconditional branch.
// Add the branch destination to the queue.
ins_iters_with_gpr_state.push((
InsIter::new(dest_code_slice, branch_dest, extensions),
gpr_pool_relocs.clone(),
));
// Break out of the current iterator so we can do the newly added one.
break;
}
}
_ => unreachable!(),
}
_ => unreachable!(),
}
}
if let Opcode::Bcctr = ins.op {
if simplified.mnemonic == "bctr" {
// Unconditional branch to count register.
// Likely a jump table.
gpr_state_at_bctr.insert(cur_addr, gpr_pool_relocs.clone());
}
if let Opcode::Bcctr = ins.op
&& simplified.mnemonic == "bctr"
{
// Unconditional branch to count register.
// Likely a jump table.
gpr_state_at_bctr.insert(cur_addr, gpr_pool_relocs.clone());
}
// Then handle keeping track of which GPR contains which pool relocation.

14
objdiff-core/src/diff/display.rs
View File

@@ -385,13 +385,13 @@ pub fn symbol_context(obj: &Object, symbol_index: usize) -> Vec<ContextItem> {
if let Some(name) = &symbol.demangled_name {
out.push(ContextItem::Copy { value: name.clone(), label: None });
}
if symbol.section.is_some() {
if let Some(address) = symbol.virtual_address {
out.push(ContextItem::Copy {
value: format!("{address:x}"),
label: Some("virtual address".to_string()),
});
}
if symbol.section.is_some()
&& let Some(address) = symbol.virtual_address
{
out.push(ContextItem::Copy {
value: format!("{address:x}"),
label: Some("virtual address".to_string()),
});
}
out.append(&mut obj.arch.symbol_context(obj, symbol_index));
out

25
objdiff-core/src/diff/mod.rs
View File

@@ -467,15 +467,15 @@ fn apply_symbol_mappings(
) -> Result<()> {
// If we're selecting a symbol to use as a comparison, mark it as used
// This ensures that we don't match it to another symbol at any point
if let Some(left_name) = &mapping_config.selecting_left {
if let Some(left_symbol) = left.symbol_by_name(left_name) {
left_used.insert(left_symbol);
}
if let Some(left_name) = &mapping_config.selecting_left
&& let Some(left_symbol) = left.symbol_by_name(left_name)
{
left_used.insert(left_symbol);
}
if let Some(right_name) = &mapping_config.selecting_right {
if let Some(right_symbol) = right.symbol_by_name(right_name) {
right_used.insert(right_symbol);
}
if let Some(right_name) = &mapping_config.selecting_right
&& let Some(right_symbol) = right.symbol_by_name(right_name)
{
right_used.insert(right_symbol);
}
// Apply manual symbol mappings
@@ -639,17 +639,16 @@ fn find_symbol(
// If they are at the same address in the same section
if in_symbol.name.starts_with('@')
&& matches!(section_kind, SectionKind::Data | SectionKind::Bss)
{
if let Some((symbol_idx, _)) = unmatched_symbols(obj, used).find(|(_, symbol)| {
&& let Some((symbol_idx, _)) = unmatched_symbols(obj, used).find(|(_, symbol)| {
let Some(section_index) = symbol.section else {
return false;
};
symbol.name.starts_with('@')
&& symbol.address == in_symbol.address
&& obj.sections[section_index].name == section_name
}) {
return Some(symbol_idx);
}
})
{
return Some(symbol_idx);
}
// Match Metrowerks symbol$1234 against symbol$2345
if let Some((prefix, suffix)) = in_symbol.name.split_once('$') {

9
objdiff-core/src/obj/read.rs
View File

@@ -550,12 +550,11 @@ fn perform_data_flow_analysis(obj: &mut Object, config: &DiffObjConfig) -> Resul
}
// Optional full data flow analysis
if config.analyze_data_flow {
if let Some(flow_result) =
if config.analyze_data_flow
&& let Some(flow_result) =
obj.arch.data_flow_analysis(obj, symbol, code, &section.relocations)
{
generated_flow_results.push((symbol.clone(), flow_result));
}
{
generated_flow_results.push((symbol.clone(), flow_result));
}
}
}

2
objdiff-core/src/util.rs
View File

@@ -48,7 +48,7 @@ pub fn align_data_to_4<W: std::io::Write + ?Sized>(
len: usize,
) -> std::io::Result<()> {
const ALIGN_BYTES: &[u8] = &[0; 4];
if len % 4 != 0 {
if !len.is_multiple_of(4) {
writer.write_all(&ALIGN_BYTES[..4 - len % 4])?;
}
Ok(())