encounter/objdiff
1
0
Fork 0
mirror of https://github.com/encounter/objdiff.git synced 2025-12-19 09:55:28 +00:00
Code Issues Packages Projects Releases Wiki Activity

Standardize the values for invalid and data opcodes (#261)

Browse Source 
* Standardize the value for an invalid opcode
>
> This makes it so that all arches share the same value for an invalid opcode, so platform-specific logic isn't needed for checking whether instructions are valid.
Also updated dependencies

* OPCODE_DATA too
This commit is contained in:
Ethan Roseman
2025-09-14 03:33:06 +09:00
committed by GitHub
parent e6035b00df
commit e2c70342c9
11 changed files with 440 additions and 339 deletions
Download Patch File Download Diff File Expand all files Collapse all files

16
objdiff-core/src/arch/x86.rs
View File

@@ -9,7 +9,7 @@ use iced_x86::{
use object::{Endian as _, Object as _, ObjectSection as _, elf, pe};
use crate::{
arch::{Arch, RelocationOverride, RelocationOverrideTarget},
arch::{Arch, OPCODE_DATA, RelocationOverride, RelocationOverrideTarget},
diff::{DiffObjConfig, X86Formatter, display::InstructionPart},
obj::{InstructionRef, Relocation, RelocationFlags, ResolvedInstructionRef, Section, Symbol},
};
@@ -89,8 +89,6 @@ impl ArchX86 {
}
}
const DATA_OPCODE: u16 = u16::MAX - 1;
impl Arch for ArchX86 {
fn scan_instructions_internal(
&self,
@@ -121,7 +119,7 @@ impl Arch for ArchX86 {
out.push(InstructionRef {
address,
size: size as u8,
opcode: DATA_OPCODE,
opcode: OPCODE_DATA,
branch_dest: None,
});
@@ -148,7 +146,7 @@ impl Arch for ArchX86 {
out.push(InstructionRef {
address: indirect_array_address + i as u64,
size: 1,
opcode: DATA_OPCODE,
opcode: OPCODE_DATA,
branch_dest: None,
});
}
@@ -187,14 +185,14 @@ impl Arch for ArchX86 {
diff_config: &DiffObjConfig,
cb: &mut dyn FnMut(InstructionPart) -> Result<()>,
) -> Result<()> {
if resolved.ins_ref.opcode == DATA_OPCODE {
if resolved.ins_ref.opcode == OPCODE_DATA {
let (mnemonic, imm) = match resolved.ins_ref.size {
1 => (".byte", resolved.code[0] as u64),
2 => (".word", self.endianness.read_u16_bytes(resolved.code.try_into()?) as u64),
4 => (".dword", self.endianness.read_u32_bytes(resolved.code.try_into()?) as u64),
_ => bail!("Unsupported x86 inline data size {}", resolved.ins_ref.size),
};
cb(InstructionPart::opcode(mnemonic, DATA_OPCODE))?;
cb(InstructionPart::opcode(mnemonic, OPCODE_DATA))?;
if resolved.relocation.is_some() {
cb(InstructionPart::reloc())?;
} else {
@@ -836,7 +834,7 @@ mod test {
ins_ref: InstructionRef {
address: 0x1234,
size: 1,
opcode: DATA_OPCODE,
opcode: OPCODE_DATA,
branch_dest: None,
},
code: &code,
@@ -850,7 +848,7 @@ mod test {
)
.unwrap();
assert_eq!(parts, &[
InstructionPart::opcode(".byte", DATA_OPCODE),
InstructionPart::opcode(".byte", OPCODE_DATA),
InstructionPart::unsigned(0xABu64),
]);
}