Update gnuv2_demangle to version 0.3 (#275)

* Migrate to unarm 2.0

* Update unarm to proper 2.0 release

* Deduplicate formatters for opaque instruction parts in ARM

* Add option to enable VFPv2 for ARM

* Update unarm to 2.0.1

* Fix read order for big-endian Thumb code

* Skip leading space in ARM instruction params

* Update ARM tests

* arm.rs: Use `alloc::borrow::Cow`

Cargo.lock

@@ -2031,9 +2031,9 @@ dependencies = [
 
 [[package]]
 name = "gnuv2_demangle"
-version = "0.1.0"
+version = "0.3.0"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "73012a2b235359cdf9e71e153da760f7268a4ad1e2c86fa3a70dca2113015695"
+checksum = "e7d12082d0c6e6f34b51ee608cc7d882bc993304f2dde3a67cfdc9196ed2741d"
 
 [[package]]
 name = "gpu-alloc"
@@ -5690,9 +5690,9 @@ dependencies = [
 
 [[package]]
 name = "unarm"
-version = "1.9.2"
+version = "2.0.1"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "9ea856cd3ee3abd1b585bbcdc6f8a4b356f43558fae98d76e502be868dc40e90"
+checksum = "e6b878ddad69fe9e0a17830aa6854f4645a31769308559317cbf1da5022eff54"
 
 [[package]]
 name = "unicase"

objdiff-core/Cargo.toml

@@ -161,7 +161,7 @@ rabbitizer = { version = "2.0.0-alpha.4", default-features = false, features = [
 iced-x86 = { version = "1.21", default-features = false, features = ["decoder", "intel", "gas", "masm", "nasm", "exhaustive_enums", "no_std"], optional = true }
 
 # arm
-unarm = { version = "1.9", optional = true }
+unarm = { version = "2.0", optional = true }
 arm-attr = { version = "0.2", optional = true }
 
 # arm64
@@ -179,7 +179,7 @@ encoding_rs = { version = "0.8.35", optional = true }
 # demangler
 cpp_demangle = { version = "0.4", optional = true, default-features = false, features = ["alloc"] }
 cwdemangle = { version = "1.0", optional = true }
-gnuv2_demangle = { version = "0.1.0", optional = true }
+gnuv2_demangle = { version = "0.3", optional = true }
 msvc-demangler = { version = "0.11", optional = true }
 
 [target.'cfg(windows)'.dependencies]

objdiff-core/config-schema.json

@@ -128,20 +128,43 @@
           "value": "auto",
           "name": "Auto"
         },
+        {
+          "value": "v4",
+          "name": "ARMv4"
+        },
         {
           "value": "v4t",
           "name": "ARMv4T (GBA)"
         },
+        {
+          "value": "v5t",
+          "name": "ARMv5T"
+        },
         {
           "value": "v5te",
           "name": "ARMv5TE (DS)"
         },
+        {
+          "value": "v5tej",
+          "name": "ARMv5TEJ"
+        },
+        {
+          "value": "v6",
+          "name": "ARMv6"
+        },
         {
           "value": "v6k",
           "name": "ARMv6K (3DS)"
         }
       ]
     },
+    {
+      "id": "arm.vfpV2",
+      "type": "boolean",
+      "default": true,
+      "name": "VFPv2 instructions",
+      "description": "Adds floating-point instructions from VFPv2."
+    },
     {
       "id": "arm.unifiedSyntax",
       "type": "boolean",
@@ -328,6 +351,7 @@
       "name": "ARM",
       "properties": [
         "arm.archVersion",
+        "arm.vfpV2",
         "arm.unifiedSyntax",
         "arm.avRegisters",
         "arm.r9Usage",

objdiff-core/src/arch/arm.rs

@@ -1,16 +1,17 @@
-use alloc::{collections::BTreeMap, format, string::ToString, vec::Vec};
+use alloc::{borrow::Cow, collections::BTreeMap, vec::Vec};
+use core::fmt::Write;
 
 use anyhow::{Result, bail};
 use arm_attr::{BuildAttrs, enums::CpuArch, tag::Tag};
 use object::{Endian as _, Object as _, ObjectSection as _, ObjectSymbol as _, elf};
-use unarm::{args, arm, thumb};
+use unarm::FormatValue as _;
 
 use crate::{
     arch::{Arch, OPCODE_DATA, OPCODE_INVALID, RelocationOverride, RelocationOverrideTarget},
     diff::{ArmArchVersion, ArmR9Usage, DiffObjConfig, display::InstructionPart},
     obj::{
-        InstructionRef, Relocation, RelocationFlags, ResolvedInstructionRef, ResolvedRelocation,
+        InstructionRef, Relocation, RelocationFlags, ResolvedInstructionRef, Section, SectionKind,
-        Section, SectionKind, Symbol, SymbolFlag, SymbolFlagSet, SymbolKind,
+        Symbol, SymbolFlag, SymbolFlagSet, SymbolKind,
     },
 };
 
@@ -18,7 +19,7 @@ use crate::{
 pub struct ArchArm {
     /// Maps section index, to list of disasm modes (arm, thumb or data) sorted by address
     disasm_modes: BTreeMap<usize, Vec<DisasmMode>>,
-    detected_version: Option<unarm::ArmVersion>,
+    detected_version: Option<unarm::Version>,
     endianness: object::Endianness,
 }
 
@@ -36,7 +37,7 @@ impl ArchArm {
         }
     }
 
-    fn elf_detect_arm_version(file: &object::File) -> Result<Option<unarm::ArmVersion>> {
+    fn elf_detect_arm_version(file: &object::File) -> Result<Option<unarm::Version>> {
         // Check ARM attributes
         if let Some(arm_attrs) = file.sections().find(|s| {
             s.kind() == object::SectionKind::Elf(elf::SHT_ARM_ATTRIBUTES)
@@ -57,9 +58,12 @@ impl ArchArm {
                     if let Tag::CpuArch(cpu_arch) = tag { Some(cpu_arch) } else { None }
                 });
                 match cpu_arch {
-                    Some(CpuArch::V4T) => return Ok(Some(unarm::ArmVersion::V4T)),
+                    Some(CpuArch::V4) => return Ok(Some(unarm::Version::V4)),
-                    Some(CpuArch::V5TE) => return Ok(Some(unarm::ArmVersion::V5Te)),
+                    Some(CpuArch::V4T) => return Ok(Some(unarm::Version::V4T)),
-                    Some(CpuArch::V6K) => return Ok(Some(unarm::ArmVersion::V6K)),
+                    Some(CpuArch::V5TE) => return Ok(Some(unarm::Version::V5Te)),
+                    Some(CpuArch::V5TEJ) => return Ok(Some(unarm::Version::V5Tej)),
+                    Some(CpuArch::V6) => return Ok(Some(unarm::Version::V6)),
+                    Some(CpuArch::V6K) => return Ok(Some(unarm::Version::V6K)),
                     Some(arch) => bail!("ARM arch {} not supported", arch),
                     None => {}
                 };
@@ -89,31 +93,33 @@ impl ArchArm {
             .collect()
     }
 
-    fn parse_flags(&self, diff_config: &DiffObjConfig) -> unarm::ParseFlags {
+    fn unarm_options(&self, diff_config: &DiffObjConfig) -> unarm::Options {
-        unarm::ParseFlags {
+        let mut extensions = unarm::Extensions::none();
-            ual: diff_config.arm_unified_syntax,
+        if diff_config.arm_vfp_v2 {
-            version: match diff_config.arm_arch_version {
+            extensions = extensions.with(unarm::Extension::VfpV2);
-                ArmArchVersion::Auto => self.detected_version.unwrap_or(unarm::ArmVersion::V5Te),
-                ArmArchVersion::V4t => unarm::ArmVersion::V4T,
-                ArmArchVersion::V5te => unarm::ArmVersion::V5Te,
-                ArmArchVersion::V6k => unarm::ArmVersion::V6K,
-            },
         }
-    }
+        unarm::Options {
-
+            version: match diff_config.arm_arch_version {
-    fn display_options(&self, diff_config: &DiffObjConfig) -> unarm::DisplayOptions {
+                ArmArchVersion::Auto => self.detected_version.unwrap_or(unarm::Version::V5Te),
-        unarm::DisplayOptions {
+                ArmArchVersion::V4 => unarm::Version::V4,
-            reg_names: unarm::RegNames {
+                ArmArchVersion::V4t => unarm::Version::V4T,
-                av_registers: diff_config.arm_av_registers,
+                ArmArchVersion::V5t => unarm::Version::V5T,
-                r9_use: match diff_config.arm_r9_usage {
+                ArmArchVersion::V5te => unarm::Version::V5Te,
-                    ArmR9Usage::GeneralPurpose => unarm::R9Use::GeneralPurpose,
+                ArmArchVersion::V5tej => unarm::Version::V5Tej,
-                    ArmR9Usage::Sb => unarm::R9Use::Pid,
+                ArmArchVersion::V6 => unarm::Version::V6,
-                    ArmR9Usage::Tr => unarm::R9Use::Tls,
+                ArmArchVersion::V6k => unarm::Version::V6K,
-                },
-                explicit_stack_limit: diff_config.arm_sl_usage,
-                frame_pointer: diff_config.arm_fp_usage,
-                ip: diff_config.arm_ip_usage,
             },
+            extensions,
+            av: diff_config.arm_av_registers,
+            r9_use: match diff_config.arm_r9_usage {
+                ArmR9Usage::GeneralPurpose => unarm::R9Use::R9,
+                ArmR9Usage::Sb => unarm::R9Use::Sb,
+                ArmR9Usage::Tr => unarm::R9Use::Tr,
+            },
+            sl: diff_config.arm_sl_usage,
+            fp: diff_config.arm_fp_usage,
+            ip: diff_config.arm_ip_usage,
+            ual: diff_config.arm_unified_syntax,
         }
     }
 
@@ -122,32 +128,7 @@ impl ArchArm {
         ins_ref: InstructionRef,
         code: &[u8],
         diff_config: &DiffObjConfig,
-    ) -> Result<(unarm::Ins, unarm::ParsedIns)> {
+    ) -> Result<unarm::Ins> {
-        if ins_ref.opcode == thumb::Opcode::BlH as u16 && ins_ref.size == 4 {
-            // Special case: combined thumb BL instruction
-            let parse_flags = self.parse_flags(diff_config);
-            let first_ins = thumb::Ins {
-                code: match self.endianness {
-                    object::Endianness::Little => u16::from_le_bytes([code[0], code[1]]),
-                    object::Endianness::Big => u16::from_be_bytes([code[0], code[1]]),
-                } as u32,
-                op: thumb::Opcode::BlH,
-            };
-            let second_ins = thumb::Ins::new(
-                match self.endianness {
-                    object::Endianness::Little => u16::from_le_bytes([code[2], code[3]]),
-                    object::Endianness::Big => u16::from_be_bytes([code[2], code[3]]),
-                } as u32,
-                &parse_flags,
-            );
-            let first_parsed = first_ins.parse(&parse_flags);
-            let second_parsed = second_ins.parse(&parse_flags);
-            return Ok((
-                unarm::Ins::Thumb(first_ins),
-                first_parsed.combine_thumb_bl(&second_parsed),
-            ));
-        }
-
         let code = match (self.endianness, ins_ref.size) {
             (object::Endianness::Little, 2) => u16::from_le_bytes([code[0], code[1]]) as u32,
             (object::Endianness::Little, 4) => {
@@ -159,21 +140,24 @@ impl ArchArm {
             }
             _ => bail!("Invalid instruction size {}", ins_ref.size),
         };
-        let (ins, parsed_ins) = if ins_ref.opcode == OPCODE_DATA {
+
-            let mut args = args::Arguments::default();
+        let thumb = ins_ref.opcode & (1 << 15) == 0;
-            args[0] = args::Argument::UImm(code);
+        let discriminant = ins_ref.opcode & !(1 << 15);
-            let mnemonic = if ins_ref.size == 4 { ".word" } else { ".hword" };
+        let pc = ins_ref.address as u32;
-            (unarm::Ins::Data, unarm::ParsedIns { mnemonic, args })
+        let options = self.unarm_options(diff_config);
-        } else if ins_ref.opcode & (1 << 15) != 0 {
+
-            let ins = arm::Ins { code, op: arm::Opcode::from(ins_ref.opcode as u8) };
+        let ins = if ins_ref.opcode == OPCODE_DATA {
-            let parsed = ins.parse(&self.parse_flags(diff_config));
+            match ins_ref.size {
-            (unarm::Ins::Arm(ins), parsed)
+                4 => unarm::Ins::Word(code),
+                2 => unarm::Ins::HalfWord(code as u16),
+                _ => bail!("Invalid data size {}", ins_ref.size),
+            }
+        } else if thumb {
+            unarm::parse_thumb_with_discriminant(code, discriminant, pc, &options)
         } else {
-            let ins = thumb::Ins { code, op: thumb::Opcode::from(ins_ref.opcode as u8) };
+            unarm::parse_arm_with_discriminant(code, discriminant, pc, &options)
-            let parsed = ins.parse(&self.parse_flags(diff_config));
-            (unarm::Ins::Thumb(ins), parsed)
         };
-        Ok((ins, parsed_ins))
+        Ok(ins)
     }
 }
 
@@ -213,10 +197,11 @@ impl Arch for ArchArm {
             .take_while(|x| x.address < end_addr);
         let mut next_mapping = mappings_iter.next();
 
-        let ins_count = code.len() / mode.instruction_size(start_addr);
+        let min_ins_size = if mode == unarm::ParseMode::Thumb { 2 } else { 4 };
+        let ins_count = code.len() / min_ins_size;
         let mut ops = Vec::<InstructionRef>::with_capacity(ins_count);
 
-        let parse_flags = self.parse_flags(diff_config);
+        let options = self.unarm_options(diff_config);
 
         let mut address = start_addr;
         while address < end_addr {
@@ -226,9 +211,8 @@ impl Arch for ArchArm {
                 next_mapping = mappings_iter.next();
             }
 
-            let mut ins_size = mode.instruction_size(address);
             let data = &code[(address - start_addr) as usize..];
-            if data.len() < ins_size {
+            if data.len() < min_ins_size {
                 // Push the remainder as data
                 ops.push(InstructionRef {
                     address: address as u64,
@@ -238,82 +222,75 @@ impl Arch for ArchArm {
                 });
                 break;
             }
-            let code = match (self.endianness, ins_size) {
+
-                (object::Endianness::Little, 2) => u16::from_le_bytes([data[0], data[1]]) as u32,
+            // Check how many bytes we can/should read
-                (object::Endianness::Little, 4) => {
+            let num_code_bytes = if data.len() >= 4 {
-                    u32::from_le_bytes([data[0], data[1], data[2], data[3]])
+                // Read 4 bytes even for Thumb, as the parser will determine if it's a 2 or 4 byte instruction
-                }
+                4
-                (object::Endianness::Big, 2) => u16::from_be_bytes([data[0], data[1]]) as u32,
+            } else if mode != unarm::ParseMode::Arm {
-                (object::Endianness::Big, 4) => {
+                2
-                    u32::from_be_bytes([data[0], data[1], data[2], data[3]])
+            } else {
-                }
+                // Invalid instruction size
-                _ => {
+                ops.push(InstructionRef {
-                    // Invalid instruction size
+                    address: address as u64,
-                    ops.push(InstructionRef {
+                    size: min_ins_size as u8,
-                        address: address as u64,
+                    opcode: OPCODE_INVALID,
-                        size: ins_size as u8,
+                    branch_dest: None,
-                        opcode: OPCODE_INVALID,
+                });
-                        branch_dest: None,
+                address += min_ins_size as u32;
-                    });
+                continue;
-                    address += ins_size as u32;
-                    continue;
-                }
             };
 
-            let (opcode, branch_dest) = match mode {
+            let code = match num_code_bytes {
-                unarm::ParseMode::Arm => {
+                4 => match self.endianness {
-                    let ins = arm::Ins::new(code, &parse_flags);
+                    object::Endianness::Little => {
-                    let opcode = ins.op as u16 | (1 << 15);
+                        u32::from_le_bytes([data[0], data[1], data[2], data[3]])
-                    let branch_dest = match ins.op {
+                    }
-                        arm::Opcode::B | arm::Opcode::Bl => {
+                    object::Endianness::Big => {
-                            address.checked_add_signed(ins.field_branch_offset())
+                        if mode != unarm::ParseMode::Thumb {
+                            u32::from_be_bytes([data[0], data[1], data[2], data[3]])
+                        } else {
+                            // For 4-byte Thumb instructions, read two 16-bit halfwords in big endian
+                            u32::from_be_bytes([data[2], data[3], data[0], data[1]])
                         }
-                        arm::Opcode::BlxI => address.checked_add_signed(ins.field_blx_offset()),
+                    }
-                        _ => None,
+                },
-                    };
+                2 => match self.endianness {
-                    (opcode, branch_dest)
+                    object::Endianness::Little => u16::from_le_bytes([data[0], data[1]]) as u32,
+                    object::Endianness::Big => u16::from_be_bytes([data[0], data[1]]) as u32,
+                },
+                _ => unreachable!(),
+            };
+
+            let (opcode, ins, ins_size) = match mode {
+                unarm::ParseMode::Arm => {
+                    let ins = unarm::parse_arm(code, address, &options);
+                    let opcode = ins.discriminant() | (1 << 15);
+                    (opcode, ins, 4)
                 }
                 unarm::ParseMode::Thumb => {
-                    let ins = thumb::Ins::new(code, &parse_flags);
+                    let (ins, size) = unarm::parse_thumb(code, address, &options);
-                    let opcode = ins.op as u16;
+                    let opcode = ins.discriminant();
-                    let branch_dest = match ins.op {
+                    (opcode, ins, size)
-                        thumb::Opcode::B | thumb::Opcode::Bl => {
-                            address.checked_add_signed(ins.field_branch_offset_8())
-                        }
-                        thumb::Opcode::BlH if data.len() >= 4 => {
-                            // Combine BL instructions
-                            let second_ins = thumb::Ins::new(
-                                match self.endianness {
-                                    object::Endianness::Little => {
-                                        u16::from_le_bytes([data[2], data[3]]) as u32
-                                    }
-                                    object::Endianness::Big => {
-                                        u16::from_be_bytes([data[2], data[3]]) as u32
-                                    }
-                                },
-                                &parse_flags,
-                            );
-                            if let Some(low) = match second_ins.op {
-                                thumb::Opcode::Bl => Some(second_ins.field_low_branch_offset_11()),
-                                thumb::Opcode::BlxI => Some(second_ins.field_low_blx_offset_11()),
-                                _ => None,
-                            } {
-                                ins_size = 4;
-                                address.checked_add_signed(
-                                    (ins.field_high_branch_offset_11() + (low as i32)) << 9 >> 9,
-                                )
-                            } else {
-                                None
-                            }
-                        }
-                        thumb::Opcode::BLong => {
-                            address.checked_add_signed(ins.field_branch_offset_11())
-                        }
-                        _ => None,
-                    };
-                    (opcode, branch_dest)
                 }
-                unarm::ParseMode::Data => (OPCODE_DATA, None),
+                unarm::ParseMode::Data => (
+                    OPCODE_DATA,
+                    if num_code_bytes == 4 {
+                        unarm::Ins::Word(code)
+                    } else {
+                        unarm::Ins::HalfWord(code as u16)
+                    },
+                    num_code_bytes,
+                ),
+            };
+
+            let branch_dest = match ins {
+                unarm::Ins::B { target, .. }
+                | unarm::Ins::Bl { target, .. }
+                | unarm::Ins::Blx { target: unarm::BlxTarget::Direct(target), .. } => {
+                    Some(target.addr)
+                }
+                _ => None,
             };
 
             ops.push(InstructionRef {
@@ -322,7 +299,7 @@ impl Arch for ArchArm {
                 opcode,
                 branch_dest: branch_dest.map(|x| x as u64),
             });
-            address += ins_size as u32;
+            address += ins_size;
         }
 
         Ok(ops)
@@ -334,20 +311,17 @@ impl Arch for ArchArm {
         diff_config: &DiffObjConfig,
         cb: &mut dyn FnMut(InstructionPart) -> Result<()>,
     ) -> Result<()> {
-        let (ins, parsed_ins) = self.parse_ins_ref(resolved.ins_ref, resolved.code, diff_config)?;
+        let ins = self.parse_ins_ref(resolved.ins_ref, resolved.code, diff_config)?;
-        cb(InstructionPart::opcode(parsed_ins.mnemonic, resolved.ins_ref.opcode))?;
+
-        if ins == unarm::Ins::Data && resolved.relocation.is_some() {
+        let options = self.unarm_options(diff_config);
-            cb(InstructionPart::reloc())?;
+        let mut string_fmt = unarm::StringFormatter::new(&options);
-        } else {
+        ins.write_opcode(&mut string_fmt)?;
-            push_args(
+        let opcode = string_fmt.into_string();
-                ins,
+        cb(InstructionPart::opcode(opcode, resolved.ins_ref.opcode))?;
-                &parsed_ins,
+
-                resolved.relocation,
+        let mut args_formatter =
-                resolved.ins_ref.address as u32,
+            ArgsFormatter { options: &options, cb, resolved: &resolved, skip_leading_space: true };
-                self.display_options(diff_config),
+        ins.write_params(&mut args_formatter)?;
-                cb,
-            )?;
-        }
         Ok(())
     }
 
@@ -495,203 +469,133 @@ impl DisasmMode {
     }
 }
 
-fn push_args(
+pub struct ArgsFormatter<'a> {
-    ins: unarm::Ins,
+    options: &'a unarm::Options,
-    parsed_ins: &unarm::ParsedIns,
+    cb: &'a mut dyn FnMut(InstructionPart) -> Result<()>,
-    relocation: Option<ResolvedRelocation>,
+    resolved: &'a ResolvedInstructionRef<'a>,
-    cur_addr: u32,
+    skip_leading_space: bool,
-    display_options: unarm::DisplayOptions,
+}
-    mut arg_cb: impl FnMut(InstructionPart) -> Result<()>,
+
-) -> Result<()> {
+impl ArgsFormatter<'_> {
-    let reloc_arg = find_reloc_arg(parsed_ins, relocation);
+    fn write(&mut self, part: InstructionPart) -> core::fmt::Result {
-    let mut writeback = false;
+        (self.cb)(part).map_err(|_| core::fmt::Error)
-    let mut deref = false;
+    }
-    for (i, &arg) in parsed_ins.args_iter().enumerate() {
+
-        // Emit punctuation before separator
+    fn write_opaque<F>(&mut self, value: F) -> core::fmt::Result
-        if deref {
+    where F: unarm::FormatValue {
-            match arg {
+        let mut string_fmt = unarm::StringFormatter::new(self.options);
-                args::Argument::OffsetImm(args::OffsetImm { post_indexed: true, value: _ })
+        value.write(&mut string_fmt)?;
-                | args::Argument::OffsetReg(args::OffsetReg {
+        self.write(InstructionPart::opaque(string_fmt.into_string()))?;
-                    add: _,
+        Ok(())
-                    post_indexed: true,
+    }
-                    reg: _,
+}
-                })
+
-                | args::Argument::CoOption(_) => {
+impl Write for ArgsFormatter<'_> {
-                    deref = false;
+    fn write_str(&mut self, s: &str) -> core::fmt::Result { self.write(InstructionPart::basic(s)) }
-                    arg_cb(InstructionPart::basic("]"))?;
+}
-                    if writeback {
+
-                        writeback = false;
+impl unarm::FormatIns for ArgsFormatter<'_> {
-                        arg_cb(InstructionPart::opaque("!"))?;
+    fn options(&self) -> &unarm::Options { self.options }
-                    }
+
+    fn write_ins(&mut self, ins: &unarm::Ins) -> core::fmt::Result {
+        let mut string_fmt = unarm::StringFormatter::new(self.options);
+        ins.write_opcode(&mut string_fmt)?;
+        let opcode = string_fmt.into_string();
+        self.write(InstructionPart::Opcode(Cow::Owned(opcode), self.resolved.ins_ref.opcode))?;
+        ins.write_params(self)
+    }
+
+    fn write_space(&mut self) -> core::fmt::Result {
+        if self.skip_leading_space {
+            self.skip_leading_space = false;
+            Ok(())
+        } else {
+            self.write_str(" ")
+        }
+    }
+
+    fn write_separator(&mut self) -> core::fmt::Result { self.write(InstructionPart::separator()) }
+
+    fn write_uimm(&mut self, uimm: u32) -> core::fmt::Result {
+        if let Some(resolved) = self.resolved.relocation
+            && let RelocationFlags::Elf(elf::R_ARM_ABS32) = resolved.relocation.flags
+        {
+            return self.write(InstructionPart::reloc());
+        }
+        self.write(InstructionPart::unsigned(uimm))
+    }
+
+    fn write_simm(&mut self, simm: i32) -> core::fmt::Result {
+        self.write(InstructionPart::signed(simm))
+    }
+
+    fn write_branch_target(&mut self, branch_target: unarm::BranchTarget) -> core::fmt::Result {
+        if let Some(resolved) = self.resolved.relocation {
+            match resolved.relocation.flags {
+                RelocationFlags::Elf(elf::R_ARM_THM_XPC22)
+                | RelocationFlags::Elf(elf::R_ARM_THM_PC22)
+                | RelocationFlags::Elf(elf::R_ARM_PC24)
+                | RelocationFlags::Elf(elf::R_ARM_XPC25)
+                | RelocationFlags::Elf(elf::R_ARM_CALL) => {
+                    return self.write(InstructionPart::reloc());
                 }
                 _ => {}
             }
         }
-
+        self.write(InstructionPart::branch_dest(branch_target.addr))
-        if i > 0 {
-            arg_cb(InstructionPart::separator())?;
-        }
-
-        if reloc_arg == Some(i) {
-            arg_cb(InstructionPart::reloc())?;
-        } else {
-            match arg {
-                args::Argument::None => {}
-                args::Argument::Reg(reg) => {
-                    if reg.deref {
-                        deref = true;
-                        arg_cb(InstructionPart::basic("["))?;
-                    }
-                    arg_cb(InstructionPart::opaque(
-                        reg.reg.display(display_options.reg_names).to_string(),
-                    ))?;
-                    if reg.writeback {
-                        if reg.deref {
-                            writeback = true;
-                        } else {
-                            arg_cb(InstructionPart::opaque("!"))?;
-                        }
-                    }
-                }
-                args::Argument::RegList(reg_list) => {
-                    arg_cb(InstructionPart::basic("{"))?;
-                    let mut first = true;
-                    for i in 0..16 {
-                        if (reg_list.regs & (1 << i)) != 0 {
-                            if !first {
-                                arg_cb(InstructionPart::separator())?;
-                            }
-                            arg_cb(InstructionPart::opaque(
-                                args::Register::parse(i)
-                                    .display(display_options.reg_names)
-                                    .to_string(),
-                            ))?;
-                            first = false;
-                        }
-                    }
-                    arg_cb(InstructionPart::basic("}"))?;
-                    if reg_list.user_mode {
-                        arg_cb(InstructionPart::opaque("^"))?;
-                    }
-                }
-                args::Argument::UImm(value)
-                | args::Argument::CoOpcode(value)
-                | args::Argument::SatImm(value) => {
-                    arg_cb(InstructionPart::basic("#"))?;
-                    arg_cb(InstructionPart::unsigned(value))?;
-                }
-                args::Argument::SImm(value)
-                | args::Argument::OffsetImm(args::OffsetImm { post_indexed: _, value }) => {
-                    arg_cb(InstructionPart::basic("#"))?;
-                    arg_cb(InstructionPart::signed(value))?;
-                }
-                args::Argument::BranchDest(value) => {
-                    arg_cb(InstructionPart::branch_dest(cur_addr.wrapping_add_signed(value)))?;
-                }
-                args::Argument::CoOption(value) => {
-                    arg_cb(InstructionPart::basic("{"))?;
-                    arg_cb(InstructionPart::unsigned(value))?;
-                    arg_cb(InstructionPart::basic("}"))?;
-                }
-                args::Argument::CoprocNum(value) => {
-                    arg_cb(InstructionPart::opaque(format!("p{value}")))?;
-                }
-                args::Argument::ShiftImm(shift) => {
-                    arg_cb(InstructionPart::opaque(shift.op.to_string()))?;
-                    arg_cb(InstructionPart::basic(" #"))?;
-                    arg_cb(InstructionPart::unsigned(shift.imm))?;
-                }
-                args::Argument::ShiftReg(shift) => {
-                    arg_cb(InstructionPart::opaque(shift.op.to_string()))?;
-                    arg_cb(InstructionPart::basic(" "))?;
-                    arg_cb(InstructionPart::opaque(
-                        shift.reg.display(display_options.reg_names).to_string(),
-                    ))?;
-                }
-                args::Argument::OffsetReg(offset) => {
-                    if !offset.add {
-                        arg_cb(InstructionPart::basic("-"))?;
-                    }
-                    arg_cb(InstructionPart::opaque(
-                        offset.reg.display(display_options.reg_names).to_string(),
-                    ))?;
-                }
-                args::Argument::CpsrMode(mode) => {
-                    arg_cb(InstructionPart::basic("#"))?;
-                    arg_cb(InstructionPart::unsigned(mode.mode))?;
-                    if mode.writeback {
-                        arg_cb(InstructionPart::opaque("!"))?;
-                    }
-                }
-                args::Argument::CoReg(_)
-                | args::Argument::StatusReg(_)
-                | args::Argument::StatusMask(_)
-                | args::Argument::Shift(_)
-                | args::Argument::CpsrFlags(_)
-                | args::Argument::Endian(_) => {
-                    arg_cb(InstructionPart::opaque(
-                        arg.display(display_options, None).to_string(),
-                    ))?;
-                }
-            }
-        }
-    }
-    if deref {
-        arg_cb(InstructionPart::basic("]"))?;
-        if writeback {
-            arg_cb(InstructionPart::opaque("!"))?;
-        }
     }
 
-    let branch_dest = get_pc_relative_load_address(ins, cur_addr);
+    fn write_reg(&mut self, reg: unarm::Reg) -> core::fmt::Result { self.write_opaque(reg) }
-    if let Some(branch_dest) = branch_dest {
+
-        arg_cb(InstructionPart::basic(" (->"))?;
+    fn write_status_reg(&mut self, status_reg: unarm::StatusReg) -> core::fmt::Result {
-        arg_cb(InstructionPart::branch_dest(branch_dest))?;
+        self.write_opaque(status_reg)
-        arg_cb(InstructionPart::basic(")"))?;
     }
 
-    Ok(())
+    fn write_status_fields(&mut self, status_fields: unarm::StatusFields) -> core::fmt::Result {
-}
+        self.write_opaque(status_fields)
-
-fn find_reloc_arg(
-    parsed_ins: &unarm::ParsedIns,
-    relocation: Option<ResolvedRelocation>,
-) -> Option<usize> {
-    if let Some(resolved) = relocation {
-        match resolved.relocation.flags {
-            // Calls
-            RelocationFlags::Elf(elf::R_ARM_THM_XPC22)
-            | RelocationFlags::Elf(elf::R_ARM_THM_PC22)
-            | RelocationFlags::Elf(elf::R_ARM_PC24)
-            | RelocationFlags::Elf(elf::R_ARM_XPC25)
-            | RelocationFlags::Elf(elf::R_ARM_CALL) => {
-                parsed_ins.args.iter().rposition(|a| matches!(a, args::Argument::BranchDest(_)))
-            }
-            // Data
-            RelocationFlags::Elf(elf::R_ARM_ABS32) => {
-                parsed_ins.args.iter().rposition(|a| matches!(a, args::Argument::UImm(_)))
-            }
-            _ => None,
-        }
-    } else {
-        None
     }
-}
 
-fn get_pc_relative_load_address(ins: unarm::Ins, address: u32) -> Option<u32> {
+    fn write_shift_op(&mut self, shift_op: unarm::ShiftOp) -> core::fmt::Result {
-    match ins {
+        self.write_opaque(shift_op)
-        unarm::Ins::Arm(ins)
+    }
-            if ins.op == arm::Opcode::Ldr
+
-                && ins.modifier_addr_ldr_str() == arm::AddrLdrStr::Imm
+    fn write_coproc(&mut self, coproc: unarm::Coproc) -> core::fmt::Result {
-                && ins.field_rn_deref().reg == args::Register::Pc =>
+        self.write_opaque(coproc)
+    }
+
+    fn write_co_reg(&mut self, co_reg: unarm::CoReg) -> core::fmt::Result {
+        self.write_opaque(co_reg)
+    }
+
+    fn write_aif_flags(&mut self, aif_flags: unarm::AifFlags) -> core::fmt::Result {
+        self.write_opaque(aif_flags)
+    }
+
+    fn write_endianness(&mut self, endianness: unarm::Endianness) -> core::fmt::Result {
+        self.write_opaque(endianness)
+    }
+
+    fn write_sreg(&mut self, sreg: unarm::Sreg) -> core::fmt::Result { self.write_opaque(sreg) }
+
+    fn write_dreg(&mut self, dreg: unarm::Dreg) -> core::fmt::Result { self.write_opaque(dreg) }
+
+    fn write_fpscr(&mut self, fpscr: unarm::Fpscr) -> core::fmt::Result { self.write_opaque(fpscr) }
+
+    fn write_addr_ldr_str(&mut self, addr_ldr_str: unarm::AddrLdrStr) -> core::fmt::Result {
+        addr_ldr_str.write(self)?;
+        if let unarm::AddrLdrStr::Pre {
+            rn: unarm::Reg::Pc,
+            offset: unarm::LdrStrOffset::Imm(offset),
+            ..
+        } = addr_ldr_str
         {
-            let offset = ins.field_offset_12().value;
+            let thumb = self.resolved.ins_ref.opcode & (1 << 15) == 0;
-            Some(address.wrapping_add_signed(offset + 8))
+            let pc_offset = if thumb { 4 } else { 8 };
+            let pc = (self.resolved.ins_ref.address as u32 & !3) + pc_offset;
+            self.write(InstructionPart::basic(" (->"))?;
+            self.write(InstructionPart::branch_dest(pc.wrapping_add(offset as u32)))?;
+            self.write(InstructionPart::basic(")"))?;
         }
-        unarm::Ins::Thumb(ins) if ins.op == thumb::Opcode::LdrPc => {
+        Ok(())
-            let offset = ins.field_rel_immed_8().value;
-            Some((address & !3).wrapping_add_signed(offset + 4))
-        }
-        _ => None,
     }
 }

objdiff-core/src/diff/demangler.rs

@@ -41,7 +41,7 @@ impl Demangler {
 
     fn demangle_gnu_legacy(name: &str) -> Option<String> {
         let name = name.trim_start_matches('.');
-        gnuv2_demangle::demangle(name, &gnuv2_demangle::DemangleConfig::new_no_cfilt_mimics()).ok()
+        gnuv2_demangle::demangle(name, &gnuv2_demangle::DemangleConfig::new()).ok()
     }
 }
 

objdiff-core/tests/snapshots/arch_arm__combine_text_sections-2.snap

@@ -2,6 +2,6 @@
 source: objdiff-core/tests/arch_arm.rs
 expression: output
 ---
-[(Line(90), Dim, 5), (Address(0), Dim, 5), (Spacing(4), Normal, 0), (Opcode("ldr", 32799), Normal, 10), (Argument(Opaque("r12")), Normal, 0), (Basic(", "), Normal, 0), (Basic("["), Normal, 0), (Argument(Opaque("pc")), Normal, 0), (Basic(", "), Normal, 0), (Basic("#"), Normal, 0), (Argument(Signed(0)), Normal, 0), (Basic("]"), Normal, 0), (Basic(" (->"), Normal, 0), (BranchDest(8), Normal, 0), (Basic(")"), Normal, 0), (Eol, Normal, 0)]
+[(Line(90), Dim, 5), (Address(0), Dim, 5), (Spacing(4), Normal, 0), (Opcode("ldr", 32792), Normal, 10), (Argument(Opaque("r12")), Normal, 0), (Basic(", "), Normal, 0), (Basic("["), Normal, 0), (Argument(Opaque("pc")), Normal, 0), (Basic(", "), Normal, 0), (Basic("#"), Normal, 0), (Argument(Signed(0)), Normal, 0), (Basic("]"), Normal, 0), (Basic(" (->"), Normal, 0), (BranchDest(8), Normal, 0), (Basic(")"), Normal, 0), (Eol, Normal, 0)]
-[(Line(90), Dim, 5), (Address(4), Dim, 5), (Spacing(4), Normal, 0), (Opcode("bx", 32779), Normal, 10), (Argument(Opaque("r12")), Normal, 0), (Eol, Normal, 0)]
+[(Line(90), Dim, 5), (Address(4), Dim, 5), (Spacing(4), Normal, 0), (Opcode("bx", 32777), Normal, 10), (Argument(Opaque("r12")), Normal, 0), (Eol, Normal, 0)]
 [(Line(90), Dim, 5), (Address(8), Dim, 5), (Spacing(4), Normal, 0), (Opcode(".word", 65534), Normal, 10), (Symbol(Symbol { name: "esEnemyDraw", demangled_name: None, address: 0, size: 0, kind: Unknown, section: None, flags: FlagSet(Global), align: None, virtual_address: None }), Bright, 0), (Eol, Normal, 0)]

objdiff-core/tests/snapshots/arch_arm__combine_text_sections.snap

@@ -8,7 +8,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 76,
                 size: 4,
-                opcode: 32799,
+                opcode: 32792,
                 branch_dest: None,
             },
         ),
@@ -22,7 +22,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 80,
                 size: 4,
-                opcode: 32779,
+                opcode: 32777,
                 branch_dest: None,
             },
         ),

objdiff-core/tests/snapshots/arch_arm__read_arm-2.snap

@@ -8,7 +8,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 40,
                 size: 4,
-                opcode: 32895,
+                opcode: 32883,
                 branch_dest: None,
             },
         ),
@@ -22,7 +22,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 44,
                 size: 4,
-                opcode: 32818,
+                opcode: 32811,
                 branch_dest: None,
             },
         ),
@@ -36,7 +36,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 48,
                 size: 4,
-                opcode: 32818,
+                opcode: 32811,
                 branch_dest: None,
             },
         ),
@@ -50,7 +50,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 52,
                 size: 4,
-                opcode: 32774,
+                opcode: 32775,
                 branch_dest: None,
             },
         ),
@@ -64,7 +64,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 56,
                 size: 4,
-                opcode: 32799,
+                opcode: 32792,
                 branch_dest: None,
             },
         ),
@@ -78,7 +78,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 60,
                 size: 4,
-                opcode: 32786,
+                opcode: 32784,
                 branch_dest: None,
             },
         ),
@@ -92,7 +92,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 64,
                 size: 4,
-                opcode: 32770,
+                opcode: 32769,
                 branch_dest: None,
             },
         ),
@@ -106,7 +106,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 68,
                 size: 4,
-                opcode: 32773,
+                opcode: 32772,
                 branch_dest: Some(
                     240,
                 ),
@@ -127,7 +127,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 72,
                 size: 4,
-                opcode: 32773,
+                opcode: 32772,
                 branch_dest: Some(
                     240,
                 ),
@@ -148,7 +148,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 76,
                 size: 4,
-                opcode: 32773,
+                opcode: 32772,
                 branch_dest: Some(
                     240,
                 ),
@@ -169,7 +169,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 80,
                 size: 4,
-                opcode: 32773,
+                opcode: 32772,
                 branch_dest: Some(
                     240,
                 ),
@@ -190,7 +190,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 84,
                 size: 4,
-                opcode: 32773,
+                opcode: 32772,
                 branch_dest: Some(
                     232,
                 ),
@@ -211,7 +211,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 88,
                 size: 4,
-                opcode: 32773,
+                opcode: 32772,
                 branch_dest: Some(
                     164,
                 ),
@@ -232,7 +232,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 92,
                 size: 4,
-                opcode: 32773,
+                opcode: 32772,
                 branch_dest: Some(
                     240,
                 ),
@@ -253,7 +253,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 96,
                 size: 4,
-                opcode: 32773,
+                opcode: 32772,
                 branch_dest: Some(
                     180,
                 ),
@@ -274,7 +274,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 100,
                 size: 4,
-                opcode: 32773,
+                opcode: 32772,
                 branch_dest: Some(
                     116,
                 ),
@@ -295,7 +295,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 104,
                 size: 4,
-                opcode: 32773,
+                opcode: 32772,
                 branch_dest: Some(
                     192,
                 ),
@@ -316,7 +316,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 108,
                 size: 4,
-                opcode: 32773,
+                opcode: 32772,
                 branch_dest: Some(
                     204,
                 ),
@@ -337,7 +337,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 112,
                 size: 4,
-                opcode: 32773,
+                opcode: 32772,
                 branch_dest: Some(
                     204,
                 ),
@@ -358,7 +358,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 116,
                 size: 4,
-                opcode: 32799,
+                opcode: 32792,
                 branch_dest: None,
             },
         ),
@@ -379,7 +379,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 120,
                 size: 4,
-                opcode: 32799,
+                opcode: 32792,
                 branch_dest: None,
             },
         ),
@@ -393,7 +393,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 124,
                 size: 4,
-                opcode: 32774,
+                opcode: 32775,
                 branch_dest: None,
             },
         ),
@@ -407,7 +407,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 128,
                 size: 4,
-                opcode: 32800,
+                opcode: 32793,
                 branch_dest: None,
             },
         ),
@@ -421,7 +421,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 132,
                 size: 4,
-                opcode: 32786,
+                opcode: 32784,
                 branch_dest: None,
             },
         ),
@@ -435,7 +435,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 136,
                 size: 4,
-                opcode: 32773,
+                opcode: 32772,
                 branch_dest: Some(
                     148,
                 ),
@@ -456,7 +456,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 140,
                 size: 4,
-                opcode: 32774,
+                opcode: 32775,
                 branch_dest: Some(
                     464,
                 ),
@@ -477,7 +477,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 144,
                 size: 4,
-                opcode: 32774,
+                opcode: 32775,
                 branch_dest: None,
             },
         ),
@@ -491,7 +491,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 148,
                 size: 4,
-                opcode: 32799,
+                opcode: 32792,
                 branch_dest: None,
             },
         ),
@@ -512,7 +512,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 152,
                 size: 4,
-                opcode: 32799,
+                opcode: 32792,
                 branch_dest: None,
             },
         ),
@@ -526,7 +526,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 156,
                 size: 4,
-                opcode: 32777,
+                opcode: 32776,
                 branch_dest: None,
             },
         ),
@@ -540,7 +540,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 160,
                 size: 4,
-                opcode: 32773,
+                opcode: 32772,
                 branch_dest: Some(
                     240,
                 ),
@@ -561,7 +561,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 164,
                 size: 4,
-                opcode: 32818,
+                opcode: 32811,
                 branch_dest: None,
             },
         ),
@@ -582,7 +582,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 168,
                 size: 4,
-                opcode: 32818,
+                opcode: 32811,
                 branch_dest: None,
             },
         ),
@@ -596,7 +596,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 172,
                 size: 4,
-                opcode: 32774,
+                opcode: 32775,
                 branch_dest: None,
             },
         ),
@@ -610,7 +610,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 176,
                 size: 4,
-                opcode: 32773,
+                opcode: 32772,
                 branch_dest: Some(
                     240,
                 ),
@@ -631,7 +631,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 180,
                 size: 4,
-                opcode: 32818,
+                opcode: 32811,
                 branch_dest: None,
             },
         ),
@@ -652,7 +652,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 184,
                 size: 4,
-                opcode: 32774,
+                opcode: 32775,
                 branch_dest: None,
             },
         ),
@@ -666,7 +666,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 188,
                 size: 4,
-                opcode: 32773,
+                opcode: 32772,
                 branch_dest: Some(
                     240,
                 ),
@@ -687,7 +687,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 192,
                 size: 4,
-                opcode: 32818,
+                opcode: 32811,
                 branch_dest: None,
             },
         ),
@@ -708,7 +708,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 196,
                 size: 4,
-                opcode: 32774,
+                opcode: 32775,
                 branch_dest: None,
             },
         ),
@@ -722,7 +722,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 200,
                 size: 4,
-                opcode: 32773,
+                opcode: 32772,
                 branch_dest: Some(
                     240,
                 ),
@@ -743,7 +743,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 204,
                 size: 4,
-                opcode: 32799,
+                opcode: 32792,
                 branch_dest: None,
             },
         ),
@@ -765,7 +765,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 208,
                 size: 4,
-                opcode: 32818,
+                opcode: 32811,
                 branch_dest: None,
             },
         ),
@@ -779,7 +779,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 212,
                 size: 4,
-                opcode: 32799,
+                opcode: 32792,
                 branch_dest: None,
             },
         ),
@@ -793,7 +793,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 216,
                 size: 4,
-                opcode: 32818,
+                opcode: 32811,
                 branch_dest: None,
             },
         ),
@@ -807,7 +807,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 220,
                 size: 4,
-                opcode: 32899,
+                opcode: 32885,
                 branch_dest: None,
             },
         ),
@@ -821,7 +821,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 224,
                 size: 4,
-                opcode: 32774,
+                opcode: 32775,
                 branch_dest: None,
             },
         ),
@@ -835,7 +835,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 228,
                 size: 4,
-                opcode: 32773,
+                opcode: 32772,
                 branch_dest: Some(
                     240,
                 ),
@@ -856,7 +856,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 232,
                 size: 4,
-                opcode: 32818,
+                opcode: 32811,
                 branch_dest: None,
             },
         ),
@@ -877,7 +877,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 236,
                 size: 4,
-                opcode: 32774,
+                opcode: 32775,
                 branch_dest: None,
             },
         ),
@@ -891,7 +891,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 240,
                 size: 4,
-                opcode: 32799,
+                opcode: 32792,
                 branch_dest: None,
             },
         ),
@@ -921,7 +921,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 244,
                 size: 4,
-                opcode: 32829,
+                opcode: 32819,
                 branch_dest: None,
             },
         ),
@@ -935,7 +935,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 248,
                 size: 4,
-                opcode: 32786,
+                opcode: 32784,
                 branch_dest: None,
             },
         ),
@@ -949,7 +949,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 252,
                 size: 4,
-                opcode: 32773,
+                opcode: 32772,
                 branch_dest: Some(
                     276,
                 ),
@@ -970,7 +970,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 256,
                 size: 4,
-                opcode: 32818,
+                opcode: 32811,
                 branch_dest: None,
             },
         ),
@@ -984,7 +984,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 260,
                 size: 4,
-                opcode: 32774,
+                opcode: 32775,
                 branch_dest: None,
             },
         ),
@@ -998,7 +998,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 264,
                 size: 4,
-                opcode: 32799,
+                opcode: 32792,
                 branch_dest: None,
             },
         ),
@@ -1012,7 +1012,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 268,
                 size: 4,
-                opcode: 32799,
+                opcode: 32792,
                 branch_dest: None,
             },
         ),
@@ -1026,7 +1026,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 272,
                 size: 4,
-                opcode: 32778,
+                opcode: 32776,
                 branch_dest: None,
             },
         ),
@@ -1040,7 +1040,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 276,
                 size: 4,
-                opcode: 32799,
+                opcode: 32792,
                 branch_dest: None,
             },
         ),
@@ -1061,7 +1061,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 280,
                 size: 4,
-                opcode: 32786,
+                opcode: 32784,
                 branch_dest: None,
             },
         ),
@@ -1075,7 +1075,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 284,
                 size: 4,
-                opcode: 32773,
+                opcode: 32772,
                 branch_dest: Some(
                     328,
                 ),
@@ -1096,7 +1096,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 288,
                 size: 4,
-                opcode: 32773,
+                opcode: 32772,
                 branch_dest: Some(
                     336,
                 ),
@@ -1117,7 +1117,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 292,
                 size: 4,
-                opcode: 32786,
+                opcode: 32784,
                 branch_dest: None,
             },
         ),
@@ -1131,7 +1131,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 296,
                 size: 4,
-                opcode: 32773,
+                opcode: 32772,
                 branch_dest: Some(
                     348,
                 ),
@@ -1152,7 +1152,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 300,
                 size: 4,
-                opcode: 32829,
+                opcode: 32819,
                 branch_dest: None,
             },
         ),
@@ -1166,7 +1166,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 304,
                 size: 4,
-                opcode: 32786,
+                opcode: 32784,
                 branch_dest: None,
             },
         ),
@@ -1180,7 +1180,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 308,
                 size: 4,
-                opcode: 32773,
+                opcode: 32772,
                 branch_dest: Some(
                     348,
                 ),
@@ -1201,7 +1201,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 312,
                 size: 4,
-                opcode: 32786,
+                opcode: 32784,
                 branch_dest: None,
             },
         ),
@@ -1215,7 +1215,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 316,
                 size: 4,
-                opcode: 32786,
+                opcode: 32784,
                 branch_dest: None,
             },
         ),
@@ -1229,7 +1229,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 320,
                 size: 4,
-                opcode: 32773,
+                opcode: 32772,
                 branch_dest: Some(
                     380,
                 ),
@@ -1250,7 +1250,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 324,
                 size: 4,
-                opcode: 32773,
+                opcode: 32772,
                 branch_dest: Some(
                     348,
                 ),
@@ -1271,7 +1271,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 328,
                 size: 4,
-                opcode: 32786,
+                opcode: 32784,
                 branch_dest: None,
             },
         ),
@@ -1292,7 +1292,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 332,
                 size: 4,
-                opcode: 32773,
+                opcode: 32772,
                 branch_dest: Some(
                     348,
                 ),
@@ -1313,7 +1313,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 336,
                 size: 4,
-                opcode: 32818,
+                opcode: 32811,
                 branch_dest: None,
             },
         ),
@@ -1334,7 +1334,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 340,
                 size: 4,
-                opcode: 32774,
+                opcode: 32775,
                 branch_dest: None,
             },
         ),
@@ -1348,7 +1348,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 344,
                 size: 4,
-                opcode: 32773,
+                opcode: 32772,
                 branch_dest: Some(
                     380,
                 ),
@@ -1369,7 +1369,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 348,
                 size: 4,
-                opcode: 32818,
+                opcode: 32811,
                 branch_dest: None,
             },
         ),
@@ -1393,7 +1393,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 352,
                 size: 4,
-                opcode: 32774,
+                opcode: 32775,
                 branch_dest: None,
             },
         ),
@@ -1407,7 +1407,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 356,
                 size: 4,
-                opcode: 32786,
+                opcode: 32784,
                 branch_dest: None,
             },
         ),
@@ -1421,7 +1421,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 360,
                 size: 4,
-                opcode: 32786,
+                opcode: 32784,
                 branch_dest: None,
             },
         ),
@@ -1435,7 +1435,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 364,
                 size: 4,
-                opcode: 32773,
+                opcode: 32772,
                 branch_dest: Some(
                     380,
                 ),
@@ -1456,7 +1456,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 368,
                 size: 4,
-                opcode: 32774,
+                opcode: 32775,
                 branch_dest: None,
             },
         ),
@@ -1470,7 +1470,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 372,
                 size: 4,
-                opcode: 32818,
+                opcode: 32811,
                 branch_dest: None,
             },
         ),
@@ -1484,7 +1484,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 376,
                 size: 4,
-                opcode: 32899,
+                opcode: 32885,
                 branch_dest: None,
             },
         ),
@@ -1498,7 +1498,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 380,
                 size: 4,
-                opcode: 32829,
+                opcode: 32819,
                 branch_dest: None,
             },
         ),
@@ -1521,7 +1521,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 384,
                 size: 4,
-                opcode: 32770,
+                opcode: 32769,
                 branch_dest: None,
             },
         ),
@@ -1535,7 +1535,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 388,
                 size: 4,
-                opcode: 32770,
+                opcode: 32769,
                 branch_dest: None,
             },
         ),
@@ -1549,7 +1549,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 392,
                 size: 4,
-                opcode: 32898,
+                opcode: 32884,
                 branch_dest: None,
             },
         ),
@@ -1563,7 +1563,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 396,
                 size: 4,
-                opcode: 32786,
+                opcode: 32784,
                 branch_dest: None,
             },
         ),
@@ -1577,7 +1577,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 400,
                 size: 4,
-                opcode: 32773,
+                opcode: 32772,
                 branch_dest: Some(
                     424,
                 ),
@@ -1598,7 +1598,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 404,
                 size: 4,
-                opcode: 32818,
+                opcode: 32811,
                 branch_dest: None,
             },
         ),
@@ -1619,7 +1619,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 408,
                 size: 4,
-                opcode: 32774,
+                opcode: 32775,
                 branch_dest: None,
             },
         ),
@@ -1633,7 +1633,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 412,
                 size: 4,
-                opcode: 32770,
+                opcode: 32769,
                 branch_dest: None,
             },
         ),
@@ -1647,7 +1647,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 416,
                 size: 4,
-                opcode: 32786,
+                opcode: 32784,
                 branch_dest: None,
             },
         ),
@@ -1661,7 +1661,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 420,
                 size: 4,
-                opcode: 32773,
+                opcode: 32772,
                 branch_dest: Some(
                     404,
                 ),
@@ -1682,7 +1682,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 424,
                 size: 4,
-                opcode: 32799,
+                opcode: 32792,
                 branch_dest: None,
             },
         ),
@@ -1703,7 +1703,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 428,
                 size: 4,
-                opcode: 32799,
+                opcode: 32792,
                 branch_dest: None,
             },
         ),
@@ -1717,7 +1717,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 432,
                 size: 4,
-                opcode: 32800,
+                opcode: 32793,
                 branch_dest: None,
             },
         ),
@@ -1731,7 +1731,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 436,
                 size: 4,
-                opcode: 32786,
+                opcode: 32784,
                 branch_dest: None,
             },
         ),
@@ -1745,7 +1745,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 440,
                 size: 4,
-                opcode: 32773,
+                opcode: 32772,
                 branch_dest: Some(
                     448,
                 ),
@@ -1766,7 +1766,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 444,
                 size: 4,
-                opcode: 32774,
+                opcode: 32775,
                 branch_dest: None,
             },
         ),
@@ -1780,7 +1780,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 448,
                 size: 4,
-                opcode: 32818,
+                opcode: 32811,
                 branch_dest: None,
             },
         ),
@@ -1801,7 +1801,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 452,
                 size: 4,
-                opcode: 32899,
+                opcode: 32885,
                 branch_dest: None,
             },
         ),
@@ -1815,7 +1815,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 456,
                 size: 4,
-                opcode: 32793,
+                opcode: 32791,
                 branch_dest: None,
             },
         ),

objdiff-core/tests/snapshots/arch_arm__read_arm-3.snap

@@ -2,111 +2,111 @@
 source: objdiff-core/tests/arch_arm.rs
 expression: output
 ---
-[(Address(0), Dim, 5), (Spacing(4), Normal, 0), (Opcode("stmdb", 32895), Normal, 10), (Argument(Opaque("sp")), Normal, 0), (Argument(Opaque("!")), Normal, 0), (Basic(", "), Normal, 0), (Basic("{"), Normal, 0), (Argument(Opaque("r4")), Normal, 0), (Basic(", "), Normal, 0), (Argument(Opaque("r5")), Normal, 0), (Basic(", "), Normal, 0), (Argument(Opaque("r6")), Normal, 0), (Basic(", "), Normal, 0), (Argument(Opaque("lr")), Normal, 0), (Basic("}"), Normal, 0), (Eol, Normal, 0)]
+[(Address(0), Dim, 5), (Spacing(4), Normal, 0), (Opcode("stmdb", 32883), Normal, 10), (Argument(Opaque("sp")), Normal, 0), (Basic("!"), Normal, 0), (Basic(", "), Normal, 0), (Basic("{"), Normal, 0), (Argument(Opaque("r4")), Normal, 0), (Basic(", "), Normal, 0), (Argument(Opaque("r5")), Normal, 0), (Basic(", "), Normal, 0), (Argument(Opaque("r6")), Normal, 0), (Basic(", "), Normal, 0), (Argument(Opaque("lr")), Normal, 0), (Basic("}"), Normal, 0), (Eol, Normal, 0)]
-[(Address(4), Dim, 5), (Spacing(4), Normal, 0), (Opcode("mov", 32818), Normal, 10), (Argument(Opaque("r5")), Normal, 0), (Basic(", "), Normal, 0), (Argument(Opaque("r0")), Normal, 0), (Eol, Normal, 0)]
+[(Address(4), Dim, 5), (Spacing(4), Normal, 0), (Opcode("mov", 32811), Normal, 10), (Argument(Opaque("r5")), Normal, 0), (Basic(", "), Normal, 0), (Argument(Opaque("r0")), Normal, 0), (Eol, Normal, 0)]
-[(Address(8), Dim, 5), (Spacing(4), Normal, 0), (Opcode("mov", 32818), Normal, 10), (Argument(Opaque("r4")), Normal, 0), (Basic(", "), Normal, 0), (Argument(Opaque("r1")), Normal, 0), (Eol, Normal, 0)]
+[(Address(8), Dim, 5), (Spacing(4), Normal, 0), (Opcode("mov", 32811), Normal, 10), (Argument(Opaque("r4")), Normal, 0), (Basic(", "), Normal, 0), (Argument(Opaque("r1")), Normal, 0), (Eol, Normal, 0)]
-[(Address(12), Dim, 5), (Spacing(4), Normal, 0), (Opcode("bl", 32774), Normal, 10), (Symbol(Symbol { name: "_ZN13LinkStateBase12OnStateLeaveEi", demangled_name: Some("LinkStateBase::OnStateLeave(int)"), address: 0, size: 0, kind: Unknown, section: None, flags: FlagSet(Global | Weak), align: None, virtual_address: None }), Bright, 0), (Addend(-8), Bright, 0), (Eol, Normal, 0)]
+[(Address(12), Dim, 5), (Spacing(4), Normal, 0), (Opcode("bl", 32775), Normal, 10), (Symbol(Symbol { name: "_ZN13LinkStateBase12OnStateLeaveEi", demangled_name: Some("LinkStateBase::OnStateLeave(int)"), address: 0, size: 0, kind: Unknown, section: None, flags: FlagSet(Global | Weak), align: None, virtual_address: None }), Bright, 0), (Addend(-8), Bright, 0), (Eol, Normal, 0)]
-[(Address(16), Dim, 5), (Spacing(4), Normal, 0), (Opcode("ldr", 32799), Normal, 10), (Argument(Opaque("r0")), Normal, 0), (Basic(", "), Normal, 0), (Basic("["), Normal, 0), (Argument(Opaque("r5")), Normal, 0), (Basic(", "), Normal, 0), (Basic("#"), Normal, 0), (Argument(Signed(20)), Normal, 0), (Basic("]"), Normal, 0), (Eol, Normal, 0)]
+[(Address(16), Dim, 5), (Spacing(4), Normal, 0), (Opcode("ldr", 32792), Normal, 10), (Argument(Opaque("r0")), Normal, 0), (Basic(", "), Normal, 0), (Basic("["), Normal, 0), (Argument(Opaque("r5")), Normal, 0), (Basic(", "), Normal, 0), (Basic("#"), Normal, 0), (Argument(Signed(20)), Normal, 0), (Basic("]"), Normal, 0), (Eol, Normal, 0)]
-[(Address(20), Dim, 5), (Spacing(4), Normal, 0), (Opcode("cmp", 32786), Normal, 10), (Argument(Opaque("r0")), Normal, 0), (Basic(", "), Normal, 0), (Basic("#"), Normal, 0), (Argument(Unsigned(10)), Normal, 0), (Eol, Normal, 0)]
+[(Address(20), Dim, 5), (Spacing(4), Normal, 0), (Opcode("cmp", 32784), Normal, 10), (Argument(Opaque("r0")), Normal, 0), (Basic(", "), Normal, 0), (Basic("#"), Normal, 0), (Argument(Unsigned(10)), Normal, 0), (Eol, Normal, 0)]
-[(Address(24), Dim, 5), (Spacing(4), Normal, 0), (Opcode("addls", 32770), Normal, 10), (Argument(Opaque("pc")), Normal, 0), (Basic(", "), Normal, 0), (Argument(Opaque("pc")), Normal, 0), (Basic(", "), Normal, 0), (Argument(Opaque("r0")), Normal, 0), (Basic(", "), Normal, 0), (Argument(Opaque("lsl")), Normal, 0), (Basic(" #"), Normal, 0), (Argument(Unsigned(2)), Normal, 0), (Eol, Normal, 0)]
+[(Address(24), Dim, 5), (Spacing(4), Normal, 0), (Opcode("addls", 32769), Normal, 10), (Argument(Opaque("pc")), Normal, 0), (Basic(", "), Normal, 0), (Argument(Opaque("pc")), Normal, 0), (Basic(", "), Normal, 0), (Argument(Opaque("r0")), Normal, 0), (Basic(", "), Normal, 0), (Argument(Opaque("lsl")), Normal, 0), (Spacing(1), Normal, 0), (Basic("#"), Normal, 0), (Argument(Unsigned(2)), Normal, 0), (Eol, Normal, 0)]
-[(Address(28), Dim, 5), (Spacing(4), Normal, 0), (Opcode("b", 32773), Normal, 10), (BranchDest(200), Normal, 0), (Basic(" ~>"), Rotating(0), 0), (Eol, Normal, 0)]
+[(Address(28), Dim, 5), (Spacing(4), Normal, 0), (Opcode("b", 32772), Normal, 10), (BranchDest(200), Normal, 0), (Basic(" ~>"), Rotating(0), 0), (Eol, Normal, 0)]
-[(Address(32), Dim, 5), (Spacing(4), Normal, 0), (Opcode("b", 32773), Normal, 10), (BranchDest(200), Normal, 0), (Basic(" ~>"), Rotating(0), 0), (Eol, Normal, 0)]
+[(Address(32), Dim, 5), (Spacing(4), Normal, 0), (Opcode("b", 32772), Normal, 10), (BranchDest(200), Normal, 0), (Basic(" ~>"), Rotating(0), 0), (Eol, Normal, 0)]
-[(Address(36), Dim, 5), (Spacing(4), Normal, 0), (Opcode("b", 32773), Normal, 10), (BranchDest(200), Normal, 0), (Basic(" ~>"), Rotating(0), 0), (Eol, Normal, 0)]
+[(Address(36), Dim, 5), (Spacing(4), Normal, 0), (Opcode("b", 32772), Normal, 10), (BranchDest(200), Normal, 0), (Basic(" ~>"), Rotating(0), 0), (Eol, Normal, 0)]
-[(Address(40), Dim, 5), (Spacing(4), Normal, 0), (Opcode("b", 32773), Normal, 10), (BranchDest(200), Normal, 0), (Basic(" ~>"), Rotating(0), 0), (Eol, Normal, 0)]
+[(Address(40), Dim, 5), (Spacing(4), Normal, 0), (Opcode("b", 32772), Normal, 10), (BranchDest(200), Normal, 0), (Basic(" ~>"), Rotating(0), 0), (Eol, Normal, 0)]
-[(Address(44), Dim, 5), (Spacing(4), Normal, 0), (Opcode("b", 32773), Normal, 10), (BranchDest(192), Normal, 0), (Basic(" ~>"), Rotating(1), 0), (Eol, Normal, 0)]
+[(Address(44), Dim, 5), (Spacing(4), Normal, 0), (Opcode("b", 32772), Normal, 10), (BranchDest(192), Normal, 0), (Basic(" ~>"), Rotating(1), 0), (Eol, Normal, 0)]
-[(Address(48), Dim, 5), (Spacing(4), Normal, 0), (Opcode("b", 32773), Normal, 10), (BranchDest(124), Normal, 0), (Basic(" ~>"), Rotating(2), 0), (Eol, Normal, 0)]
+[(Address(48), Dim, 5), (Spacing(4), Normal, 0), (Opcode("b", 32772), Normal, 10), (BranchDest(124), Normal, 0), (Basic(" ~>"), Rotating(2), 0), (Eol, Normal, 0)]
-[(Address(52), Dim, 5), (Spacing(4), Normal, 0), (Opcode("b", 32773), Normal, 10), (BranchDest(200), Normal, 0), (Basic(" ~>"), Rotating(0), 0), (Eol, Normal, 0)]
+[(Address(52), Dim, 5), (Spacing(4), Normal, 0), (Opcode("b", 32772), Normal, 10), (BranchDest(200), Normal, 0), (Basic(" ~>"), Rotating(0), 0), (Eol, Normal, 0)]
-[(Address(56), Dim, 5), (Spacing(4), Normal, 0), (Opcode("b", 32773), Normal, 10), (BranchDest(140), Normal, 0), (Basic(" ~>"), Rotating(3), 0), (Eol, Normal, 0)]
+[(Address(56), Dim, 5), (Spacing(4), Normal, 0), (Opcode("b", 32772), Normal, 10), (BranchDest(140), Normal, 0), (Basic(" ~>"), Rotating(3), 0), (Eol, Normal, 0)]
-[(Address(60), Dim, 5), (Spacing(4), Normal, 0), (Opcode("b", 32773), Normal, 10), (BranchDest(76), Normal, 0), (Basic(" ~>"), Rotating(4), 0), (Eol, Normal, 0)]
+[(Address(60), Dim, 5), (Spacing(4), Normal, 0), (Opcode("b", 32772), Normal, 10), (BranchDest(76), Normal, 0), (Basic(" ~>"), Rotating(4), 0), (Eol, Normal, 0)]
-[(Address(64), Dim, 5), (Spacing(4), Normal, 0), (Opcode("b", 32773), Normal, 10), (BranchDest(152), Normal, 0), (Basic(" ~>"), Rotating(5), 0), (Eol, Normal, 0)]
+[(Address(64), Dim, 5), (Spacing(4), Normal, 0), (Opcode("b", 32772), Normal, 10), (BranchDest(152), Normal, 0), (Basic(" ~>"), Rotating(5), 0), (Eol, Normal, 0)]
-[(Address(68), Dim, 5), (Spacing(4), Normal, 0), (Opcode("b", 32773), Normal, 10), (BranchDest(164), Normal, 0), (Basic(" ~>"), Rotating(6), 0), (Eol, Normal, 0)]
+[(Address(68), Dim, 5), (Spacing(4), Normal, 0), (Opcode("b", 32772), Normal, 10), (BranchDest(164), Normal, 0), (Basic(" ~>"), Rotating(6), 0), (Eol, Normal, 0)]
-[(Address(72), Dim, 5), (Spacing(4), Normal, 0), (Opcode("b", 32773), Normal, 10), (BranchDest(164), Normal, 0), (Basic(" ~>"), Rotating(6), 0), (Eol, Normal, 0)]
+[(Address(72), Dim, 5), (Spacing(4), Normal, 0), (Opcode("b", 32772), Normal, 10), (BranchDest(164), Normal, 0), (Basic(" ~>"), Rotating(6), 0), (Eol, Normal, 0)]
-[(Address(76), Dim, 5), (Basic(" ~> "), Rotating(4), 0), (Opcode("ldr", 32799), Normal, 10), (Argument(Opaque("r0")), Normal, 0), (Basic(", "), Normal, 0), (Basic("["), Normal, 0), (Argument(Opaque("pc")), Normal, 0), (Basic(", "), Normal, 0), (Basic("#"), Normal, 0), (Argument(Signed(336)), Normal, 0), (Basic("]"), Normal, 0), (Basic(" (->"), Normal, 0), (BranchDest(420), Normal, 0), (Basic(")"), Normal, 0), (Eol, Normal, 0)]
+[(Address(76), Dim, 5), (Basic(" ~> "), Rotating(4), 0), (Opcode("ldr", 32792), Normal, 10), (Argument(Opaque("r0")), Normal, 0), (Basic(", "), Normal, 0), (Basic("["), Normal, 0), (Argument(Opaque("pc")), Normal, 0), (Basic(", "), Normal, 0), (Basic("#"), Normal, 0), (Argument(Signed(336)), Normal, 0), (Basic("]"), Normal, 0), (Basic(" (->"), Normal, 0), (BranchDest(420), Normal, 0), (Basic(")"), Normal, 0), (Eol, Normal, 0)]
-[(Address(80), Dim, 5), (Spacing(4), Normal, 0), (Opcode("ldr", 32799), Normal, 10), (Argument(Opaque("r0")), Normal, 0), (Basic(", "), Normal, 0), (Basic("["), Normal, 0), (Argument(Opaque("r0")), Normal, 0), (Basic(", "), Normal, 0), (Basic("#"), Normal, 0), (Argument(Signed(0)), Normal, 0), (Basic("]"), Normal, 0), (Eol, Normal, 0)]
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-[(Address(388), Dim, 5), (Spacing(4), Normal, 0), (Opcode("ldr", 32799), Normal, 10), (Argument(Opaque("r0")), Normal, 0), (Basic(", "), Normal, 0), (Basic("["), Normal, 0), (Argument(Opaque("r0")), Normal, 0), (Basic(", "), Normal, 0), (Basic("#"), Normal, 0), (Argument(Signed(0)), Normal, 0), (Basic("]"), Normal, 0), (Eol, Normal, 0)]
+[(Address(388), Dim, 5), (Spacing(4), Normal, 0), (Opcode("ldr", 32792), Normal, 10), (Argument(Opaque("r0")), Normal, 0), (Basic(", "), Normal, 0), (Basic("["), Normal, 0), (Argument(Opaque("r0")), Normal, 0), (Basic(", "), Normal, 0), (Basic("#"), Normal, 0), (Argument(Signed(0)), Normal, 0), (Basic("]"), Normal, 0), (Eol, Normal, 0)]
-[(Address(392), Dim, 5), (Spacing(4), Normal, 0), (Opcode("ldrb", 32800), Normal, 10), (Argument(Opaque("r1")), Normal, 0), (Basic(", "), Normal, 0), (Basic("["), Normal, 0), (Argument(Opaque("r0")), Normal, 0), (Basic(", "), Normal, 0), (Basic("#"), Normal, 0), (Argument(Signed(128)), Normal, 0), (Basic("]"), Normal, 0), (Eol, Normal, 0)]
+[(Address(392), Dim, 5), (Spacing(4), Normal, 0), (Opcode("ldrb", 32793), Normal, 10), (Argument(Opaque("r1")), Normal, 0), (Basic(", "), Normal, 0), (Basic("["), Normal, 0), (Argument(Opaque("r0")), Normal, 0), (Basic(", "), Normal, 0), (Basic("#"), Normal, 0), (Argument(Signed(128)), Normal, 0), (Basic("]"), Normal, 0), (Eol, Normal, 0)]
-[(Address(396), Dim, 5), (Spacing(4), Normal, 0), (Opcode("cmp", 32786), Normal, 10), (Argument(Opaque("r1")), Normal, 0), (Basic(", "), Normal, 0), (Basic("#"), Normal, 0), (Argument(Unsigned(0)), Normal, 0), (Eol, Normal, 0)]
+[(Address(396), Dim, 5), (Spacing(4), Normal, 0), (Opcode("cmp", 32784), Normal, 10), (Argument(Opaque("r1")), Normal, 0), (Basic(", "), Normal, 0), (Basic("#"), Normal, 0), (Argument(Unsigned(0)), Normal, 0), (Eol, Normal, 0)]
-[(Address(400), Dim, 5), (Spacing(4), Normal, 0), (Opcode("beq", 32773), Normal, 10), (BranchDest(408), Normal, 0), (Basic(" ~>"), Rotating(16), 0), (Eol, Normal, 0)]
+[(Address(400), Dim, 5), (Spacing(4), Normal, 0), (Opcode("beq", 32772), Normal, 10), (BranchDest(408), Normal, 0), (Basic(" ~>"), Rotating(16), 0), (Eol, Normal, 0)]
-[(Address(404), Dim, 5), (Spacing(4), Normal, 0), (Opcode("bl", 32774), Normal, 10), (Symbol(Symbol { name: "_ZN13PlayerControl13StopFollowingEv", demangled_name: Some("PlayerControl::StopFollowing()"), address: 0, size: 0, kind: Unknown, section: None, flags: FlagSet(Global | Weak), align: None, virtual_address: None }), Bright, 0), (Addend(-8), Bright, 0), (Eol, Normal, 0)]
+[(Address(404), Dim, 5), (Spacing(4), Normal, 0), (Opcode("bl", 32775), Normal, 10), (Symbol(Symbol { name: "_ZN13PlayerControl13StopFollowingEv", demangled_name: Some("PlayerControl::StopFollowing()"), address: 0, size: 0, kind: Unknown, section: None, flags: FlagSet(Global | Weak), align: None, virtual_address: None }), Bright, 0), (Addend(-8), Bright, 0), (Eol, Normal, 0)]
-[(Address(408), Dim, 5), (Basic(" ~> "), Rotating(16), 0), (Opcode("mov", 32818), Normal, 10), (Argument(Opaque("r0")), Normal, 0), (Basic(", "), Normal, 0), (Basic("#"), Normal, 0), (Argument(Unsigned(0)), Normal, 0), (Eol, Normal, 0)]
+[(Address(408), Dim, 5), (Basic(" ~> "), Rotating(16), 0), (Opcode("mov", 32811), Normal, 10), (Argument(Opaque("r0")), Normal, 0), (Basic(", "), Normal, 0), (Basic("#"), Normal, 0), (Argument(Unsigned(0)), Normal, 0), (Eol, Normal, 0)]
-[(Address(412), Dim, 5), (Spacing(4), Normal, 0), (Opcode("strb", 32899), Normal, 10), (Argument(Opaque("r0")), Normal, 0), (Basic(", "), Normal, 0), (Basic("["), Normal, 0), (Argument(Opaque("r5")), Normal, 0), (Basic(", "), Normal, 0), (Basic("#"), Normal, 0), (Argument(Signed(38)), Normal, 0), (Basic("]"), Normal, 0), (Eol, Normal, 0)]
+[(Address(412), Dim, 5), (Spacing(4), Normal, 0), (Opcode("strb", 32885), Normal, 10), (Argument(Opaque("r0")), Normal, 0), (Basic(", "), Normal, 0), (Basic("["), Normal, 0), (Argument(Opaque("r5")), Normal, 0), (Basic(", "), Normal, 0), (Basic("#"), Normal, 0), (Argument(Signed(38)), Normal, 0), (Basic("]"), Normal, 0), (Eol, Normal, 0)]
-[(Address(416), Dim, 5), (Spacing(4), Normal, 0), (Opcode("ldmia", 32793), Normal, 10), (Argument(Opaque("sp")), Normal, 0), (Argument(Opaque("!")), Normal, 0), (Basic(", "), Normal, 0), (Basic("{"), Normal, 0), (Argument(Opaque("r4")), Normal, 0), (Basic(", "), Normal, 0), (Argument(Opaque("r5")), Normal, 0), (Basic(", "), Normal, 0), (Argument(Opaque("r6")), Normal, 0), (Basic(", "), Normal, 0), (Argument(Opaque("pc")), Normal, 0), (Basic("}"), Normal, 0), (Eol, Normal, 0)]
+[(Address(416), Dim, 5), (Spacing(4), Normal, 0), (Opcode("ldmia", 32791), Normal, 10), (Argument(Opaque("sp")), Normal, 0), (Basic("!"), Normal, 0), (Basic(", "), Normal, 0), (Basic("{"), Normal, 0), (Argument(Opaque("r4")), Normal, 0), (Basic(", "), Normal, 0), (Argument(Opaque("r5")), Normal, 0), (Basic(", "), Normal, 0), (Argument(Opaque("r6")), Normal, 0), (Basic(", "), Normal, 0), (Argument(Opaque("pc")), Normal, 0), (Basic("}"), Normal, 0), (Eol, Normal, 0)]
 [(Address(420), Dim, 5), (Spacing(4), Normal, 0), (Opcode(".word", 65534), Normal, 10), (Symbol(Symbol { name: "data_027e103c", demangled_name: None, address: 0, size: 0, kind: Unknown, section: None, flags: FlagSet(Global | Weak), align: None, virtual_address: None }), Bright, 0), (Eol, Normal, 0)]
 [(Address(424), Dim, 5), (Basic(" ~> "), Rotating(8), 0), (Opcode(".word", 65534), Normal, 10), (Symbol(Symbol { name: "data_027e1098", demangled_name: None, address: 0, size: 0, kind: Unknown, section: None, flags: FlagSet(Global | Weak), align: None, virtual_address: None }), Bright, 0), (Eol, Normal, 0)]
 [(Address(428), Dim, 5), (Spacing(4), Normal, 0), (Opcode(".word", 65534), Normal, 10), (Symbol(Symbol { name: "gPlayerControl", demangled_name: None, address: 0, size: 0, kind: Unknown, section: None, flags: FlagSet(Global | Weak), align: None, virtual_address: None }), Bright, 0), (Eol, Normal, 0)]

objdiff-core/tests/snapshots/arch_arm__read_thumb-2.snap

@@ -8,7 +8,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 0,
                 size: 2,
-                opcode: 56,
+                opcode: 59,
                 branch_dest: None,
             },
         ),
@@ -22,7 +22,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 2,
                 size: 2,
-                opcode: 74,
+                opcode: 126,
                 branch_dest: None,
             },
         ),
@@ -36,7 +36,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 4,
                 size: 2,
-                opcode: 47,
+                opcode: 43,
                 branch_dest: None,
             },
         ),
@@ -50,7 +50,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 6,
                 size: 2,
-                opcode: 47,
+                opcode: 43,
                 branch_dest: None,
             },
         ),
@@ -64,7 +64,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 8,
                 size: 2,
-                opcode: 47,
+                opcode: 43,
                 branch_dest: None,
             },
         ),
@@ -78,7 +78,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 10,
                 size: 2,
-                opcode: 47,
+                opcode: 43,
                 branch_dest: None,
             },
         ),
@@ -92,7 +92,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 12,
                 size: 2,
-                opcode: 66,
+                opcode: 116,
                 branch_dest: None,
             },
         ),
@@ -106,7 +106,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 14,
                 size: 4,
-                opcode: 19,
+                opcode: 7,
                 branch_dest: None,
             },
         ),
@@ -120,7 +120,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 18,
                 size: 2,
-                opcode: 25,
+                opcode: 16,
                 branch_dest: None,
             },
         ),
@@ -134,7 +134,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 20,
                 size: 2,
-                opcode: 15,
+                opcode: 4,
                 branch_dest: Some(
                     212,
                 ),
@@ -155,7 +155,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 22,
                 size: 2,
-                opcode: 38,
+                opcode: 32,
                 branch_dest: None,
             },
         ),
@@ -169,7 +169,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 24,
                 size: 2,
-                opcode: 25,
+                opcode: 16,
                 branch_dest: None,
             },
         ),
@@ -183,7 +183,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 26,
                 size: 2,
-                opcode: 15,
+                opcode: 4,
                 branch_dest: Some(
                     48,
                 ),
@@ -204,7 +204,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 28,
                 size: 2,
-                opcode: 34,
+                opcode: 24,
                 branch_dest: None,
             },
         ),
@@ -218,7 +218,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 30,
                 size: 2,
-                opcode: 26,
+                opcode: 16,
                 branch_dest: None,
             },
         ),
@@ -232,7 +232,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 32,
                 size: 2,
-                opcode: 15,
+                opcode: 4,
                 branch_dest: Some(
                     94,
                 ),
@@ -253,7 +253,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 34,
                 size: 2,
-                opcode: 35,
+                opcode: 24,
                 branch_dest: None,
             },
         ),
@@ -267,7 +267,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 36,
                 size: 2,
-                opcode: 47,
+                opcode: 43,
                 branch_dest: None,
             },
         ),
@@ -281,7 +281,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 38,
                 size: 2,
-                opcode: 47,
+                opcode: 43,
                 branch_dest: None,
             },
         ),
@@ -295,7 +295,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 40,
                 size: 4,
-                opcode: 19,
+                opcode: 7,
                 branch_dest: None,
             },
         ),
@@ -309,7 +309,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 44,
                 size: 2,
-                opcode: 7,
+                opcode: 1,
                 branch_dest: None,
             },
         ),
@@ -323,7 +323,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 46,
                 size: 2,
-                opcode: 55,
+                opcode: 58,
                 branch_dest: None,
             },
         ),
@@ -337,7 +337,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 48,
                 size: 2,
-                opcode: 47,
+                opcode: 43,
                 branch_dest: None,
             },
         ),
@@ -358,7 +358,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 50,
                 size: 2,
-                opcode: 47,
+                opcode: 43,
                 branch_dest: None,
             },
         ),
@@ -372,7 +372,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 52,
                 size: 4,
-                opcode: 19,
+                opcode: 7,
                 branch_dest: None,
             },
         ),
@@ -386,7 +386,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 56,
                 size: 2,
-                opcode: 25,
+                opcode: 16,
                 branch_dest: None,
             },
         ),
@@ -400,7 +400,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 58,
                 size: 2,
-                opcode: 15,
+                opcode: 4,
                 branch_dest: Some(
                     212,
                 ),
@@ -421,7 +421,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 60,
                 size: 2,
-                opcode: 34,
+                opcode: 24,
                 branch_dest: None,
             },
         ),
@@ -435,7 +435,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 62,
                 size: 2,
-                opcode: 33,
+                opcode: 24,
                 branch_dest: None,
             },
         ),
@@ -449,7 +449,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 64,
                 size: 2,
-                opcode: 36,
+                opcode: 25,
                 branch_dest: None,
             },
         ),
@@ -463,7 +463,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 66,
                 size: 2,
-                opcode: 42,
+                opcode: 36,
                 branch_dest: None,
             },
         ),
@@ -477,7 +477,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 68,
                 size: 2,
-                opcode: 44,
+                opcode: 37,
                 branch_dest: None,
             },
         ),
@@ -491,7 +491,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 70,
                 size: 2,
-                opcode: 15,
+                opcode: 4,
                 branch_dest: Some(
                     212,
                 ),
@@ -512,7 +512,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 72,
                 size: 2,
-                opcode: 46,
+                opcode: 43,
                 branch_dest: None,
             },
         ),
@@ -526,7 +526,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 74,
                 size: 2,
-                opcode: 17,
+                opcode: 5,
                 branch_dest: None,
             },
         ),
@@ -540,7 +540,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 76,
                 size: 2,
-                opcode: 46,
+                opcode: 43,
                 branch_dest: None,
             },
         ),
@@ -568,7 +568,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 80,
                 size: 2,
-                opcode: 67,
+                opcode: 117,
                 branch_dest: None,
             },
         ),
@@ -582,7 +582,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 82,
                 size: 2,
-                opcode: 36,
+                opcode: 25,
                 branch_dest: None,
             },
         ),
@@ -596,7 +596,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 84,
                 size: 2,
-                opcode: 46,
+                opcode: 43,
                 branch_dest: None,
             },
         ),
@@ -610,7 +610,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 86,
                 size: 2,
-                opcode: 7,
+                opcode: 1,
                 branch_dest: None,
             },
         ),
@@ -638,7 +638,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 90,
                 size: 2,
-                opcode: 67,
+                opcode: 117,
                 branch_dest: None,
             },
         ),
@@ -652,7 +652,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 92,
                 size: 2,
-                opcode: 55,
+                opcode: 58,
                 branch_dest: None,
             },
         ),
@@ -666,7 +666,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 94,
                 size: 2,
-                opcode: 34,
+                opcode: 24,
                 branch_dest: None,
             },
         ),
@@ -687,7 +687,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 96,
                 size: 2,
-                opcode: 34,
+                opcode: 24,
                 branch_dest: None,
             },
         ),
@@ -701,7 +701,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 98,
                 size: 2,
-                opcode: 4,
+                opcode: 1,
                 branch_dest: None,
             },
         ),
@@ -715,7 +715,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 100,
                 size: 4,
-                opcode: 19,
+                opcode: 7,
                 branch_dest: None,
             },
         ),
@@ -729,7 +729,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 104,
                 size: 2,
-                opcode: 66,
+                opcode: 116,
                 branch_dest: None,
             },
         ),
@@ -743,7 +743,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 106,
                 size: 2,
-                opcode: 47,
+                opcode: 43,
                 branch_dest: None,
             },
         ),
@@ -757,7 +757,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 108,
                 size: 4,
-                opcode: 19,
+                opcode: 7,
                 branch_dest: None,
             },
         ),
@@ -771,7 +771,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 112,
                 size: 2,
-                opcode: 47,
+                opcode: 43,
                 branch_dest: None,
             },
         ),
@@ -785,7 +785,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 114,
                 size: 2,
-                opcode: 6,
+                opcode: 1,
                 branch_dest: None,
             },
         ),
@@ -799,7 +799,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 116,
                 size: 2,
-                opcode: 66,
+                opcode: 116,
                 branch_dest: None,
             },
         ),
@@ -813,7 +813,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 118,
                 size: 2,
-                opcode: 35,
+                opcode: 24,
                 branch_dest: None,
             },
         ),
@@ -827,7 +827,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 120,
                 size: 2,
-                opcode: 47,
+                opcode: 43,
                 branch_dest: None,
             },
         ),
@@ -841,7 +841,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 122,
                 size: 2,
-                opcode: 47,
+                opcode: 43,
                 branch_dest: None,
             },
         ),
@@ -855,7 +855,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 124,
                 size: 2,
-                opcode: 47,
+                opcode: 43,
                 branch_dest: None,
             },
         ),
@@ -869,7 +869,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 126,
                 size: 4,
-                opcode: 19,
+                opcode: 7,
                 branch_dest: None,
             },
         ),
@@ -883,7 +883,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 130,
                 size: 2,
-                opcode: 25,
+                opcode: 16,
                 branch_dest: None,
             },
         ),
@@ -897,7 +897,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 132,
                 size: 2,
-                opcode: 15,
+                opcode: 4,
                 branch_dest: Some(
                     168,
                 ),
@@ -918,7 +918,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 134,
                 size: 2,
-                opcode: 47,
+                opcode: 43,
                 branch_dest: None,
             },
         ),
@@ -932,7 +932,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 136,
                 size: 4,
-                opcode: 19,
+                opcode: 7,
                 branch_dest: None,
             },
         ),
@@ -946,7 +946,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 140,
                 size: 2,
-                opcode: 47,
+                opcode: 43,
                 branch_dest: None,
             },
         ),
@@ -960,7 +960,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 142,
                 size: 2,
-                opcode: 25,
+                opcode: 16,
                 branch_dest: None,
             },
         ),
@@ -974,7 +974,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 144,
                 size: 2,
-                opcode: 15,
+                opcode: 4,
                 branch_dest: Some(
                     168,
                 ),
@@ -995,7 +995,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 146,
                 size: 2,
-                opcode: 34,
+                opcode: 24,
                 branch_dest: None,
             },
         ),
@@ -1009,7 +1009,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 148,
                 size: 2,
-                opcode: 33,
+                opcode: 24,
                 branch_dest: None,
             },
         ),
@@ -1023,7 +1023,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 150,
                 size: 2,
-                opcode: 36,
+                opcode: 25,
                 branch_dest: None,
             },
         ),
@@ -1037,7 +1037,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 152,
                 size: 2,
-                opcode: 42,
+                opcode: 36,
                 branch_dest: None,
             },
         ),
@@ -1051,7 +1051,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 154,
                 size: 2,
-                opcode: 44,
+                opcode: 37,
                 branch_dest: None,
             },
         ),
@@ -1065,7 +1065,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 156,
                 size: 2,
-                opcode: 15,
+                opcode: 4,
                 branch_dest: Some(
                     168,
                 ),
@@ -1086,7 +1086,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 158,
                 size: 2,
-                opcode: 46,
+                opcode: 43,
                 branch_dest: None,
             },
         ),
@@ -1100,7 +1100,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 160,
                 size: 2,
-                opcode: 17,
+                opcode: 5,
                 branch_dest: None,
             },
         ),
@@ -1114,7 +1114,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 162,
                 size: 2,
-                opcode: 46,
+                opcode: 43,
                 branch_dest: None,
             },
         ),
@@ -1142,7 +1142,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 166,
                 size: 2,
-                opcode: 67,
+                opcode: 117,
                 branch_dest: None,
             },
         ),
@@ -1156,7 +1156,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 168,
                 size: 2,
-                opcode: 25,
+                opcode: 16,
                 branch_dest: None,
             },
         ),
@@ -1179,7 +1179,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 170,
                 size: 2,
-                opcode: 15,
+                opcode: 4,
                 branch_dest: Some(
                     200,
                 ),
@@ -1200,7 +1200,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 172,
                 size: 2,
-                opcode: 35,
+                opcode: 24,
                 branch_dest: None,
             },
         ),
@@ -1214,7 +1214,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 174,
                 size: 2,
-                opcode: 25,
+                opcode: 16,
                 branch_dest: None,
             },
         ),
@@ -1228,7 +1228,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 176,
                 size: 2,
-                opcode: 15,
+                opcode: 4,
                 branch_dest: Some(
                     200,
                 ),
@@ -1249,7 +1249,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 178,
                 size: 2,
-                opcode: 34,
+                opcode: 24,
                 branch_dest: None,
             },
         ),
@@ -1263,7 +1263,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 180,
                 size: 2,
-                opcode: 37,
+                opcode: 25,
                 branch_dest: None,
             },
         ),
@@ -1277,7 +1277,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 182,
                 size: 2,
-                opcode: 42,
+                opcode: 36,
                 branch_dest: None,
             },
         ),
@@ -1291,7 +1291,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 184,
                 size: 2,
-                opcode: 44,
+                opcode: 37,
                 branch_dest: None,
             },
         ),
@@ -1305,7 +1305,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 186,
                 size: 2,
-                opcode: 15,
+                opcode: 4,
                 branch_dest: Some(
                     200,
                 ),
@@ -1326,7 +1326,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 188,
                 size: 2,
-                opcode: 32,
+                opcode: 24,
                 branch_dest: None,
             },
         ),
@@ -1340,7 +1340,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 190,
                 size: 2,
-                opcode: 34,
+                opcode: 24,
                 branch_dest: None,
             },
         ),
@@ -1354,7 +1354,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 192,
                 size: 2,
-                opcode: 46,
+                opcode: 43,
                 branch_dest: None,
             },
         ),
@@ -1368,7 +1368,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 194,
                 size: 2,
-                opcode: 46,
+                opcode: 43,
                 branch_dest: None,
             },
         ),
@@ -1382,7 +1382,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 196,
                 size: 4,
-                opcode: 19,
+                opcode: 7,
                 branch_dest: None,
             },
         ),
@@ -1396,7 +1396,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 200,
                 size: 2,
-                opcode: 34,
+                opcode: 24,
                 branch_dest: None,
             },
         ),
@@ -1419,7 +1419,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 202,
                 size: 2,
-                opcode: 35,
+                opcode: 24,
                 branch_dest: None,
             },
         ),
@@ -1433,7 +1433,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 204,
                 size: 2,
-                opcode: 34,
+                opcode: 24,
                 branch_dest: None,
             },
         ),
@@ -1447,7 +1447,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 206,
                 size: 2,
-                opcode: 4,
+                opcode: 1,
                 branch_dest: None,
             },
         ),
@@ -1461,7 +1461,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 208,
                 size: 4,
-                opcode: 19,
+                opcode: 7,
                 branch_dest: None,
             },
         ),
@@ -1475,7 +1475,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 212,
                 size: 2,
-                opcode: 7,
+                opcode: 1,
                 branch_dest: None,
             },
         ),
@@ -1498,7 +1498,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 214,
                 size: 2,
-                opcode: 55,
+                opcode: 58,
                 branch_dest: None,
             },
         ),

objdiff-core/tests/snapshots/arch_arm__read_thumb-3.snap

@@ -2,109 +2,109 @@
 source: objdiff-core/tests/arch_arm.rs
 expression: output
 ---
-[(Line(37), Dim, 5), (Address(0), Dim, 5), (Spacing(4), Normal, 0), (Opcode("push", 56), Normal, 10), (Basic("{"), Normal, 0), (Argument(Opaque("r3")), Normal, 0), (Basic(", "), Normal, 0), (Argument(Opaque("r4")), Normal, 0), (Basic(", "), Normal, 0), (Argument(Opaque("r5")), Normal, 0), (Basic(", "), Normal, 0), (Argument(Opaque("r6")), Normal, 0), (Basic(", "), Normal, 0), (Argument(Opaque("r7")), Normal, 0), (Basic(", "), Normal, 0), (Argument(Opaque("lr")), Normal, 0), (Basic("}"), Normal, 0), (Eol, Normal, 0)]
+[(Line(37), Dim, 5), (Address(0), Dim, 5), (Spacing(4), Normal, 0), (Opcode("push", 59), Normal, 10), (Basic("{"), Normal, 0), (Argument(Opaque("r3")), Normal, 0), (Basic(", "), Normal, 0), (Argument(Opaque("r4")), Normal, 0), (Basic(", "), Normal, 0), (Argument(Opaque("r5")), Normal, 0), (Basic(", "), Normal, 0), (Argument(Opaque("r6")), Normal, 0), (Basic(", "), Normal, 0), (Argument(Opaque("r7")), Normal, 0), (Basic(", "), Normal, 0), (Argument(Opaque("lr")), Normal, 0), (Basic("}"), Normal, 0), (Eol, Normal, 0)]
-[(Line(37), Dim, 5), (Address(2), Dim, 5), (Spacing(4), Normal, 0), (Opcode("sub", 74), Normal, 10), (Argument(Opaque("sp")), Normal, 0), (Basic(", "), Normal, 0), (Argument(Opaque("sp")), Normal, 0), (Basic(", "), Normal, 0), (Basic("#"), Normal, 0), (Argument(Signed(16)), Normal, 0), (Eol, Normal, 0)]
+[(Line(37), Dim, 5), (Address(2), Dim, 5), (Spacing(4), Normal, 0), (Opcode("sub", 126), Normal, 10), (Argument(Opaque("sp")), Normal, 0), (Basic(", "), Normal, 0), (Basic("#"), Normal, 0), (Argument(Unsigned(16)), Normal, 0), (Eol, Normal, 0)]
-[(Line(37), Dim, 5), (Address(4), Dim, 5), (Spacing(4), Normal, 0), (Opcode("mov", 47), Normal, 10), (Argument(Opaque("r5")), Normal, 0), (Basic(", "), Normal, 0), (Argument(Opaque("r0")), Normal, 0), (Eol, Normal, 0)]
+[(Line(37), Dim, 5), (Address(4), Dim, 5), (Spacing(4), Normal, 0), (Opcode("mov", 43), Normal, 10), (Argument(Opaque("r5")), Normal, 0), (Basic(", "), Normal, 0), (Argument(Opaque("r0")), Normal, 0), (Eol, Normal, 0)]
-[(Line(39), Dim, 5), (Address(6), Dim, 5), (Spacing(4), Normal, 0), (Opcode("mov", 47), Normal, 10), (Argument(Opaque("r0")), Normal, 0), (Basic(", "), Normal, 0), (Argument(Opaque("r3")), Normal, 0), (Eol, Normal, 0)]
+[(Line(39), Dim, 5), (Address(6), Dim, 5), (Spacing(4), Normal, 0), (Opcode("mov", 43), Normal, 10), (Argument(Opaque("r0")), Normal, 0), (Basic(", "), Normal, 0), (Argument(Opaque("r3")), Normal, 0), (Eol, Normal, 0)]
-[(Line(39), Dim, 5), (Address(8), Dim, 5), (Spacing(4), Normal, 0), (Opcode("mov", 47), Normal, 10), (Argument(Opaque("r4")), Normal, 0), (Basic(", "), Normal, 0), (Argument(Opaque("r1")), Normal, 0), (Eol, Normal, 0)]
+[(Line(39), Dim, 5), (Address(8), Dim, 5), (Spacing(4), Normal, 0), (Opcode("mov", 43), Normal, 10), (Argument(Opaque("r4")), Normal, 0), (Basic(", "), Normal, 0), (Argument(Opaque("r1")), Normal, 0), (Eol, Normal, 0)]
-[(Line(39), Dim, 5), (Address(10), Dim, 5), (Spacing(4), Normal, 0), (Opcode("mov", 47), Normal, 10), (Argument(Opaque("r6")), Normal, 0), (Basic(", "), Normal, 0), (Argument(Opaque("r2")), Normal, 0), (Eol, Normal, 0)]
+[(Line(39), Dim, 5), (Address(10), Dim, 5), (Spacing(4), Normal, 0), (Opcode("mov", 43), Normal, 10), (Argument(Opaque("r6")), Normal, 0), (Basic(", "), Normal, 0), (Argument(Opaque("r2")), Normal, 0), (Eol, Normal, 0)]
-[(Line(39), Dim, 5), (Address(12), Dim, 5), (Spacing(4), Normal, 0), (Opcode("str", 66), Normal, 10), (Argument(Opaque("r3")), Normal, 0), (Basic(", "), Normal, 0), (Basic("["), Normal, 0), (Argument(Opaque("sp")), Normal, 0), (Basic(", "), Normal, 0), (Basic("#"), Normal, 0), (Argument(Signed(4)), Normal, 0), (Basic("]"), Normal, 0), (Eol, Normal, 0)]
+[(Line(39), Dim, 5), (Address(12), Dim, 5), (Spacing(4), Normal, 0), (Opcode("str", 116), Normal, 10), (Argument(Opaque("r3")), Normal, 0), (Basic(", "), Normal, 0), (Basic("["), Normal, 0), (Argument(Opaque("sp")), Normal, 0), (Basic(", "), Normal, 0), (Basic("#"), Normal, 0), (Argument(Signed(4)), Normal, 0), (Basic("]"), Normal, 0), (Eol, Normal, 0)]
-[(Line(39), Dim, 5), (Address(14), Dim, 5), (Spacing(4), Normal, 0), (Opcode("bl", 19), Normal, 10), (Symbol(Symbol { name: "PokeSet_IsRemovedAll", demangled_name: None, address: 0, size: 0, kind: Unknown, section: None, flags: FlagSet(Global), align: None, virtual_address: None }), Bright, 0), (Addend(-4), Bright, 0), (Eol, Normal, 0)]
+[(Line(39), Dim, 5), (Address(14), Dim, 5), (Spacing(4), Normal, 0), (Opcode("bl", 7), Normal, 10), (Symbol(Symbol { name: "PokeSet_IsRemovedAll", demangled_name: None, address: 0, size: 0, kind: Unknown, section: None, flags: FlagSet(Global), align: None, virtual_address: None }), Bright, 0), (Addend(-4), Bright, 0), (Eol, Normal, 0)]
-[(Line(39), Dim, 5), (Address(18), Dim, 5), (Spacing(4), Normal, 0), (Opcode("cmp", 25), Normal, 10), (Argument(Opaque("r0")), Normal, 0), (Basic(", "), Normal, 0), (Basic("#"), Normal, 0), (Argument(Unsigned(0)), Normal, 0), (Eol, Normal, 0)]
+[(Line(39), Dim, 5), (Address(18), Dim, 5), (Spacing(4), Normal, 0), (Opcode("cmp", 16), Normal, 10), (Argument(Opaque("r0")), Normal, 0), (Basic(", "), Normal, 0), (Basic("#"), Normal, 0), (Argument(Unsigned(0)), Normal, 0), (Eol, Normal, 0)]
-[(Line(39), Dim, 5), (Address(20), Dim, 5), (Spacing(4), Normal, 0), (Opcode("bne", 15), Normal, 10), (BranchDest(212), Normal, 0), (Basic(" ~>"), Rotating(0), 0), (Eol, Normal, 0)]
+[(Line(39), Dim, 5), (Address(20), Dim, 5), (Spacing(4), Normal, 0), (Opcode("bne", 4), Normal, 10), (BranchDest(212), Normal, 0), (Basic(" ~>"), Rotating(0), 0), (Eol, Normal, 0)]
-[(Line(44), Dim, 5), (Address(22), Dim, 5), (Spacing(4), Normal, 0), (Opcode("ldrh", 38), Normal, 10), (Argument(Opaque("r1")), Normal, 0), (Basic(", "), Normal, 0), (Basic("["), Normal, 0), (Argument(Opaque("r4")), Normal, 0), (Basic(", "), Normal, 0), (Basic("#"), Normal, 0), (Argument(Signed(0)), Normal, 0), (Basic("]"), Normal, 0), (Eol, Normal, 0)]
+[(Line(44), Dim, 5), (Address(22), Dim, 5), (Spacing(4), Normal, 0), (Opcode("ldrh", 32), Normal, 10), (Argument(Opaque("r1")), Normal, 0), (Basic(", "), Normal, 0), (Basic("["), Normal, 0), (Argument(Opaque("r4")), Normal, 0), (Basic(", "), Normal, 0), (Basic("#"), Normal, 0), (Argument(Signed(0)), Normal, 0), (Basic("]"), Normal, 0), (Eol, Normal, 0)]
-[(Line(44), Dim, 5), (Address(24), Dim, 5), (Spacing(4), Normal, 0), (Opcode("cmp", 25), Normal, 10), (Argument(Opaque("r1")), Normal, 0), (Basic(", "), Normal, 0), (Basic("#"), Normal, 0), (Argument(Unsigned(164)), Normal, 0), (Eol, Normal, 0)]
+[(Line(44), Dim, 5), (Address(24), Dim, 5), (Spacing(4), Normal, 0), (Opcode("cmp", 16), Normal, 10), (Argument(Opaque("r1")), Normal, 0), (Basic(", "), Normal, 0), (Basic("#"), Normal, 0), (Argument(Unsigned(164)), Normal, 0), (Eol, Normal, 0)]
-[(Line(44), Dim, 5), (Address(26), Dim, 5), (Spacing(4), Normal, 0), (Opcode("beq", 15), Normal, 10), (BranchDest(48), Normal, 0), (Basic(" ~>"), Rotating(1), 0), (Eol, Normal, 0)]
+[(Line(44), Dim, 5), (Address(26), Dim, 5), (Spacing(4), Normal, 0), (Opcode("beq", 4), Normal, 10), (BranchDest(48), Normal, 0), (Basic(" ~>"), Rotating(1), 0), (Eol, Normal, 0)]
-[(Line(44), Dim, 5), (Address(28), Dim, 5), (Spacing(4), Normal, 0), (Opcode("ldr", 34), Normal, 10), (Argument(Opaque("r0")), Normal, 0), (Basic(", "), Normal, 0), (Basic("["), Normal, 0), (Argument(Opaque("pc")), Normal, 0), (Basic(", "), Normal, 0), (Basic("#"), Normal, 0), (Argument(Signed(184)), Normal, 0), (Basic("]"), Normal, 0), (Basic(" (->"), Normal, 0), (BranchDest(216), Normal, 0), (Basic(")"), Normal, 0), (Eol, Normal, 0)]
+[(Line(44), Dim, 5), (Address(28), Dim, 5), (Spacing(4), Normal, 0), (Opcode("ldr", 24), Normal, 10), (Argument(Opaque("r0")), Normal, 0), (Basic(", "), Normal, 0), (Basic("["), Normal, 0), (Argument(Opaque("pc")), Normal, 0), (Basic(", "), Normal, 0), (Basic("#"), Normal, 0), (Argument(Signed(184)), Normal, 0), (Basic("]"), Normal, 0), (Basic(" (->"), Normal, 0), (BranchDest(216), Normal, 0), (Basic(")"), Normal, 0), (Eol, Normal, 0)]
-[(Line(44), Dim, 5), (Address(30), Dim, 5), (Spacing(4), Normal, 0), (Opcode("cmp", 26), Normal, 10), (Argument(Opaque("r1")), Normal, 0), (Basic(", "), Normal, 0), (Argument(Opaque("r0")), Normal, 0), (Eol, Normal, 0)]
+[(Line(44), Dim, 5), (Address(30), Dim, 5), (Spacing(4), Normal, 0), (Opcode("cmp", 16), Normal, 10), (Argument(Opaque("r1")), Normal, 0), (Basic(", "), Normal, 0), (Argument(Opaque("r0")), Normal, 0), (Eol, Normal, 0)]
-[(Line(44), Dim, 5), (Address(32), Dim, 5), (Spacing(4), Normal, 0), (Opcode("bne", 15), Normal, 10), (BranchDest(94), Normal, 0), (Basic(" ~>"), Rotating(2), 0), (Eol, Normal, 0)]
+[(Line(44), Dim, 5), (Address(32), Dim, 5), (Spacing(4), Normal, 0), (Opcode("bne", 4), Normal, 10), (BranchDest(94), Normal, 0), (Basic(" ~>"), Rotating(2), 0), (Eol, Normal, 0)]
-[(Line(47), Dim, 5), (Address(34), Dim, 5), (Spacing(4), Normal, 0), (Opcode("ldr", 35), Normal, 10), (Argument(Opaque("r2")), Normal, 0), (Basic(", "), Normal, 0), (Basic("["), Normal, 0), (Argument(Opaque("sp")), Normal, 0), (Basic(", "), Normal, 0), (Basic("#"), Normal, 0), (Argument(Signed(4)), Normal, 0), (Basic("]"), Normal, 0), (Eol, Normal, 0)]
+[(Line(47), Dim, 5), (Address(34), Dim, 5), (Spacing(4), Normal, 0), (Opcode("ldr", 24), Normal, 10), (Argument(Opaque("r2")), Normal, 0), (Basic(", "), Normal, 0), (Basic("["), Normal, 0), (Argument(Opaque("sp")), Normal, 0), (Basic(", "), Normal, 0), (Basic("#"), Normal, 0), (Argument(Signed(4)), Normal, 0), (Basic("]"), Normal, 0), (Eol, Normal, 0)]
-[(Line(47), Dim, 5), (Address(36), Dim, 5), (Spacing(4), Normal, 0), (Opcode("mov", 47), Normal, 10), (Argument(Opaque("r0")), Normal, 0), (Basic(", "), Normal, 0), (Argument(Opaque("r5")), Normal, 0), (Eol, Normal, 0)]
+[(Line(47), Dim, 5), (Address(36), Dim, 5), (Spacing(4), Normal, 0), (Opcode("mov", 43), Normal, 10), (Argument(Opaque("r0")), Normal, 0), (Basic(", "), Normal, 0), (Argument(Opaque("r5")), Normal, 0), (Eol, Normal, 0)]
-[(Line(47), Dim, 5), (Address(38), Dim, 5), (Spacing(4), Normal, 0), (Opcode("mov", 47), Normal, 10), (Argument(Opaque("r1")), Normal, 0), (Basic(", "), Normal, 0), (Argument(Opaque("r6")), Normal, 0), (Eol, Normal, 0)]
+[(Line(47), Dim, 5), (Address(38), Dim, 5), (Spacing(4), Normal, 0), (Opcode("mov", 43), Normal, 10), (Argument(Opaque("r1")), Normal, 0), (Basic(", "), Normal, 0), (Argument(Opaque("r6")), Normal, 0), (Eol, Normal, 0)]
-[(Line(47), Dim, 5), (Address(40), Dim, 5), (Spacing(4), Normal, 0), (Opcode("bl", 19), Normal, 10), (Symbol(Symbol { name: "ServerDisplay_SkillSwap", demangled_name: None, address: 0, size: 0, kind: Unknown, section: None, flags: FlagSet(Global), align: None, virtual_address: None }), Bright, 0), (Addend(-4), Bright, 0), (Eol, Normal, 0)]
+[(Line(47), Dim, 5), (Address(40), Dim, 5), (Spacing(4), Normal, 0), (Opcode("bl", 7), Normal, 10), (Symbol(Symbol { name: "ServerDisplay_SkillSwap", demangled_name: None, address: 0, size: 0, kind: Unknown, section: None, flags: FlagSet(Global), align: None, virtual_address: None }), Bright, 0), (Addend(-4), Bright, 0), (Eol, Normal, 0)]
-[(Line(86), Dim, 5), (Address(44), Dim, 5), (Spacing(4), Normal, 0), (Opcode("add", 7), Normal, 10), (Argument(Opaque("sp")), Normal, 0), (Basic(", "), Normal, 0), (Basic("#"), Normal, 0), (Argument(Signed(16)), Normal, 0), (Eol, Normal, 0)]
+[(Line(86), Dim, 5), (Address(44), Dim, 5), (Spacing(4), Normal, 0), (Opcode("add", 1), Normal, 10), (Argument(Opaque("sp")), Normal, 0), (Basic(", "), Normal, 0), (Basic("#"), Normal, 0), (Argument(Unsigned(16)), Normal, 0), (Eol, Normal, 0)]
-[(Line(86), Dim, 5), (Address(46), Dim, 5), (Spacing(4), Normal, 0), (Opcode("pop", 55), Normal, 10), (Basic("{"), Normal, 0), (Argument(Opaque("r3")), Normal, 0), (Basic(", "), Normal, 0), (Argument(Opaque("r4")), Normal, 0), (Basic(", "), Normal, 0), (Argument(Opaque("r5")), Normal, 0), (Basic(", "), Normal, 0), (Argument(Opaque("r6")), Normal, 0), (Basic(", "), Normal, 0), (Argument(Opaque("r7")), Normal, 0), (Basic(", "), Normal, 0), (Argument(Opaque("pc")), Normal, 0), (Basic("}"), Normal, 0), (Eol, Normal, 0)]
+[(Line(86), Dim, 5), (Address(46), Dim, 5), (Spacing(4), Normal, 0), (Opcode("pop", 58), Normal, 10), (Basic("{"), Normal, 0), (Argument(Opaque("r3")), Normal, 0), (Basic(", "), Normal, 0), (Argument(Opaque("r4")), Normal, 0), (Basic(", "), Normal, 0), (Argument(Opaque("r5")), Normal, 0), (Basic(", "), Normal, 0), (Argument(Opaque("r6")), Normal, 0), (Basic(", "), Normal, 0), (Argument(Opaque("r7")), Normal, 0), (Basic(", "), Normal, 0), (Argument(Opaque("pc")), Normal, 0), (Basic("}"), Normal, 0), (Eol, Normal, 0)]
-[(Line(50), Dim, 5), (Address(48), Dim, 5), (Basic(" ~> "), Rotating(1), 0), (Opcode("mov", 47), Normal, 10), (Argument(Opaque("r0")), Normal, 0), (Basic(", "), Normal, 0), (Argument(Opaque("r5")), Normal, 0), (Eol, Normal, 0)]
+[(Line(50), Dim, 5), (Address(48), Dim, 5), (Basic(" ~> "), Rotating(1), 0), (Opcode("mov", 43), Normal, 10), (Argument(Opaque("r0")), Normal, 0), (Basic(", "), Normal, 0), (Argument(Opaque("r5")), Normal, 0), (Eol, Normal, 0)]
-[(Line(50), Dim, 5), (Address(50), Dim, 5), (Spacing(4), Normal, 0), (Opcode("mov", 47), Normal, 10), (Argument(Opaque("r1")), Normal, 0), (Basic(", "), Normal, 0), (Argument(Opaque("r6")), Normal, 0), (Eol, Normal, 0)]
+[(Line(50), Dim, 5), (Address(50), Dim, 5), (Spacing(4), Normal, 0), (Opcode("mov", 43), Normal, 10), (Argument(Opaque("r1")), Normal, 0), (Basic(", "), Normal, 0), (Argument(Opaque("r6")), Normal, 0), (Eol, Normal, 0)]
-[(Line(50), Dim, 5), (Address(52), Dim, 5), (Spacing(4), Normal, 0), (Opcode("bl", 19), Normal, 10), (Symbol(Symbol { name: "ServerEvent_CreateSubstitute", demangled_name: None, address: 0, size: 0, kind: Unknown, section: None, flags: FlagSet(Global), align: None, virtual_address: None }), Bright, 0), (Addend(-4), Bright, 0), (Eol, Normal, 0)]
+[(Line(50), Dim, 5), (Address(52), Dim, 5), (Spacing(4), Normal, 0), (Opcode("bl", 7), Normal, 10), (Symbol(Symbol { name: "ServerEvent_CreateSubstitute", demangled_name: None, address: 0, size: 0, kind: Unknown, section: None, flags: FlagSet(Global), align: None, virtual_address: None }), Bright, 0), (Addend(-4), Bright, 0), (Eol, Normal, 0)]
-[(Line(50), Dim, 5), (Address(56), Dim, 5), (Spacing(4), Normal, 0), (Opcode("cmp", 25), Normal, 10), (Argument(Opaque("r0")), Normal, 0), (Basic(", "), Normal, 0), (Basic("#"), Normal, 0), (Argument(Unsigned(0)), Normal, 0), (Eol, Normal, 0)]
+[(Line(50), Dim, 5), (Address(56), Dim, 5), (Spacing(4), Normal, 0), (Opcode("cmp", 16), Normal, 10), (Argument(Opaque("r0")), Normal, 0), (Basic(", "), Normal, 0), (Basic("#"), Normal, 0), (Argument(Unsigned(0)), Normal, 0), (Eol, Normal, 0)]
-[(Line(50), Dim, 5), (Address(58), Dim, 5), (Spacing(4), Normal, 0), (Opcode("beq", 15), Normal, 10), (BranchDest(212), Normal, 0), (Basic(" ~>"), Rotating(0), 0), (Eol, Normal, 0)]
+[(Line(50), Dim, 5), (Address(58), Dim, 5), (Spacing(4), Normal, 0), (Opcode("beq", 4), Normal, 10), (BranchDest(212), Normal, 0), (Basic(" ~>"), Rotating(0), 0), (Eol, Normal, 0)]
-[(Line(52), Dim, 5), (Address(60), Dim, 5), (Spacing(4), Normal, 0), (Opcode("ldr", 34), Normal, 10), (Argument(Opaque("r0")), Normal, 0), (Basic(", "), Normal, 0), (Basic("["), Normal, 0), (Argument(Opaque("pc")), Normal, 0), (Basic(", "), Normal, 0), (Basic("#"), Normal, 0), (Argument(Signed(156)), Normal, 0), (Basic("]"), Normal, 0), (Basic(" (->"), Normal, 0), (BranchDest(220), Normal, 0), (Basic(")"), Normal, 0), (Eol, Normal, 0)]
+[(Line(52), Dim, 5), (Address(60), Dim, 5), (Spacing(4), Normal, 0), (Opcode("ldr", 24), Normal, 10), (Argument(Opaque("r0")), Normal, 0), (Basic(", "), Normal, 0), (Basic("["), Normal, 0), (Argument(Opaque("pc")), Normal, 0), (Basic(", "), Normal, 0), (Basic("#"), Normal, 0), (Argument(Signed(156)), Normal, 0), (Basic("]"), Normal, 0), (Basic(" (->"), Normal, 0), (BranchDest(220), Normal, 0), (Basic(")"), Normal, 0), (Eol, Normal, 0)]
-[(Line(52), Dim, 5), (Address(62), Dim, 5), (Spacing(4), Normal, 0), (Opcode("ldr", 33), Normal, 10), (Argument(Opaque("r0")), Normal, 0), (Basic(", "), Normal, 0), (Basic("["), Normal, 0), (Argument(Opaque("r5")), Normal, 0), (Basic(", "), Normal, 0), (Argument(Opaque("r0")), Normal, 0), (Basic("]"), Normal, 0), (Eol, Normal, 0)]
+[(Line(52), Dim, 5), (Address(62), Dim, 5), (Spacing(4), Normal, 0), (Opcode("ldr", 24), Normal, 10), (Argument(Opaque("r0")), Normal, 0), (Basic(", "), Normal, 0), (Basic("["), Normal, 0), (Argument(Opaque("r5")), Normal, 0), (Basic(", "), Normal, 0), (Argument(Opaque("r0")), Normal, 0), (Basic("]"), Normal, 0), (Eol, Normal, 0)]
-[(Line(52), Dim, 5), (Address(64), Dim, 5), (Spacing(4), Normal, 0), (Opcode("ldrb", 36), Normal, 10), (Argument(Opaque("r2")), Normal, 0), (Basic(", "), Normal, 0), (Basic("["), Normal, 0), (Argument(Opaque("r0")), Normal, 0), (Basic(", "), Normal, 0), (Basic("#"), Normal, 0), (Argument(Signed(5)), Normal, 0), (Basic("]"), Normal, 0), (Eol, Normal, 0)]
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+[(Line(86), Dim, 5), (Address(212), Dim, 5), (Basic(" ~> "), Rotating(0), 0), (Opcode("add", 1), Normal, 10), (Argument(Opaque("sp")), Normal, 0), (Basic(", "), Normal, 0), (Basic("#"), Normal, 0), (Argument(Unsigned(16)), Normal, 0), (Eol, Normal, 0)]
-[(Line(86), Dim, 5), (Address(214), Dim, 5), (Spacing(4), Normal, 0), (Opcode("pop", 55), Normal, 10), (Basic("{"), Normal, 0), (Argument(Opaque("r3")), Normal, 0), (Basic(", "), Normal, 0), (Argument(Opaque("r4")), Normal, 0), (Basic(", "), Normal, 0), (Argument(Opaque("r5")), Normal, 0), (Basic(", "), Normal, 0), (Argument(Opaque("r6")), Normal, 0), (Basic(", "), Normal, 0), (Argument(Opaque("r7")), Normal, 0), (Basic(", "), Normal, 0), (Argument(Opaque("pc")), Normal, 0), (Basic("}"), Normal, 0), (Eol, Normal, 0)]
+[(Line(86), Dim, 5), (Address(214), Dim, 5), (Spacing(4), Normal, 0), (Opcode("pop", 58), Normal, 10), (Basic("{"), Normal, 0), (Argument(Opaque("r3")), Normal, 0), (Basic(", "), Normal, 0), (Argument(Opaque("r4")), Normal, 0), (Basic(", "), Normal, 0), (Argument(Opaque("r5")), Normal, 0), (Basic(", "), Normal, 0), (Argument(Opaque("r6")), Normal, 0), (Basic(", "), Normal, 0), (Argument(Opaque("r7")), Normal, 0), (Basic(", "), Normal, 0), (Argument(Opaque("pc")), Normal, 0), (Basic("}"), Normal, 0), (Eol, Normal, 0)]
-[(Line(86), Dim, 5), (Address(216), Dim, 5), (Spacing(4), Normal, 0), (Opcode(".word", 65534), Normal, 10), (Basic("#"), Normal, 0), (Argument(Unsigned(285)), Normal, 0), (Eol, Normal, 0)]
+[(Line(86), Dim, 5), (Address(216), Dim, 5), (Spacing(4), Normal, 0), (Opcode(".word", 65534), Normal, 10), (Argument(Unsigned(285)), Normal, 0), (Eol, Normal, 0)]
-[(Line(86), Dim, 5), (Address(220), Dim, 5), (Spacing(4), Normal, 0), (Opcode(".word", 65534), Normal, 10), (Basic("#"), Normal, 0), (Argument(Unsigned(1192)), Normal, 0), (Eol, Normal, 0)]
+[(Line(86), Dim, 5), (Address(220), Dim, 5), (Spacing(4), Normal, 0), (Opcode(".word", 65534), Normal, 10), (Argument(Unsigned(1192)), Normal, 0), (Eol, Normal, 0)]
-[(Line(86), Dim, 5), (Address(224), Dim, 5), (Spacing(4), Normal, 0), (Opcode(".word", 65534), Normal, 10), (Basic("#"), Normal, 0), (Argument(Unsigned(7544)), Normal, 0), (Eol, Normal, 0)]
+[(Line(86), Dim, 5), (Address(224), Dim, 5), (Spacing(4), Normal, 0), (Opcode(".word", 65534), Normal, 10), (Argument(Unsigned(7544)), Normal, 0), (Eol, Normal, 0)]
-[(Line(86), Dim, 5), (Address(228), Dim, 5), (Spacing(4), Normal, 0), (Opcode(".word", 65534), Normal, 10), (Basic("#"), Normal, 0), (Argument(Unsigned(9103)), Normal, 0), (Eol, Normal, 0)]
+[(Line(86), Dim, 5), (Address(228), Dim, 5), (Spacing(4), Normal, 0), (Opcode(".word", 65534), Normal, 10), (Argument(Unsigned(9103)), Normal, 0), (Eol, Normal, 0)]
-[(Line(86), Dim, 5), (Address(232), Dim, 5), (Spacing(4), Normal, 0), (Opcode(".word", 65534), Normal, 10), (Basic("#"), Normal, 0), (Argument(Unsigned(1930)), Normal, 0), (Eol, Normal, 0)]
+[(Line(86), Dim, 5), (Address(232), Dim, 5), (Spacing(4), Normal, 0), (Opcode(".word", 65534), Normal, 10), (Argument(Unsigned(1930)), Normal, 0), (Eol, Normal, 0)]
-[(Line(86), Dim, 5), (Address(236), Dim, 5), (Spacing(4), Normal, 0), (Opcode(".word", 65534), Normal, 10), (Basic("#"), Normal, 0), (Argument(Unsigned(4294901760)), Normal, 0), (Eol, Normal, 0)]
+[(Line(86), Dim, 5), (Address(236), Dim, 5), (Spacing(4), Normal, 0), (Opcode(".word", 65534), Normal, 10), (Argument(Unsigned(4294901760)), Normal, 0), (Eol, Normal, 0)]
-[(Line(86), Dim, 5), (Address(240), Dim, 5), (Spacing(4), Normal, 0), (Opcode(".word", 65534), Normal, 10), (Basic("#"), Normal, 0), (Argument(Unsigned(9129)), Normal, 0), (Eol, Normal, 0)]
+[(Line(86), Dim, 5), (Address(240), Dim, 5), (Spacing(4), Normal, 0), (Opcode(".word", 65534), Normal, 10), (Argument(Unsigned(9129)), Normal, 0), (Eol, Normal, 0)]

objdiff-core/tests/snapshots/arch_arm__trim_trailing_hword-2.snap

@@ -2,6 +2,6 @@
 source: objdiff-core/tests/arch_arm.rs
 expression: output
 ---
-[(Address(0), Dim, 5), (Spacing(4), Normal, 0), (Opcode("str", 64), Normal, 10), (Argument(Opaque("r1")), Normal, 0), (Basic(", "), Normal, 0), (Basic("["), Normal, 0), (Argument(Opaque("r0")), Normal, 0), (Basic(", "), Normal, 0), (Basic("#"), Normal, 0), (Argument(Signed(36)), Normal, 0), (Basic("]"), Normal, 0), (Eol, Normal, 0)]
+[(Address(0), Dim, 5), (Spacing(4), Normal, 0), (Opcode("str", 116), Normal, 10), (Argument(Opaque("r1")), Normal, 0), (Basic(", "), Normal, 0), (Basic("["), Normal, 0), (Argument(Opaque("r0")), Normal, 0), (Basic(", "), Normal, 0), (Basic("#"), Normal, 0), (Argument(Signed(36)), Normal, 0), (Basic("]"), Normal, 0), (Eol, Normal, 0)]
-[(Address(2), Dim, 5), (Spacing(4), Normal, 0), (Opcode("str", 64), Normal, 10), (Argument(Opaque("r2")), Normal, 0), (Basic(", "), Normal, 0), (Basic("["), Normal, 0), (Argument(Opaque("r0")), Normal, 0), (Basic(", "), Normal, 0), (Basic("#"), Normal, 0), (Argument(Signed(40)), Normal, 0), (Basic("]"), Normal, 0), (Eol, Normal, 0)]
+[(Address(2), Dim, 5), (Spacing(4), Normal, 0), (Opcode("str", 116), Normal, 10), (Argument(Opaque("r2")), Normal, 0), (Basic(", "), Normal, 0), (Basic("["), Normal, 0), (Argument(Opaque("r0")), Normal, 0), (Basic(", "), Normal, 0), (Basic("#"), Normal, 0), (Argument(Signed(40)), Normal, 0), (Basic("]"), Normal, 0), (Eol, Normal, 0)]
-[(Address(4), Dim, 5), (Spacing(4), Normal, 0), (Opcode("bx", 23), Normal, 10), (Argument(Opaque("lr")), Normal, 0), (Eol, Normal, 0)]
+[(Address(4), Dim, 5), (Spacing(4), Normal, 0), (Opcode("bx", 9), Normal, 10), (Argument(Opaque("lr")), Normal, 0), (Eol, Normal, 0)]

objdiff-core/tests/snapshots/arch_arm__trim_trailing_hword.snap

@@ -8,7 +8,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 0,
                 size: 2,
-                opcode: 64,
+                opcode: 116,
                 branch_dest: None,
             },
         ),
@@ -22,7 +22,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 2,
                 size: 2,
-                opcode: 64,
+                opcode: 116,
                 branch_dest: None,
             },
         ),
@@ -36,7 +36,7 @@ expression: diff.instruction_rows
             InstructionRef {
                 address: 4,
                 size: 2,
-                opcode: 23,
+                opcode: 9,
                 branch_dest: None,
             },
         ),