mirror of
https://github.com/encounter/objdiff.git
synced 2025-06-07 15:13:47 +00:00
Luke Street
8e8ab6bef8
COFF objects in particular don't contain the size of symbols. We infer the size of these symbols by extending them to the next symbol. If a tool emits symbols for branch targets, this causes the inferred size to be too small. This checks if a symbol starts with a certain prefix (right now, just .L or LAB_), and skips over it during symbol size inference. Resolves #174
679 lines
27 KiB
Rust
679 lines
27 KiB
Rust
use alloc::{
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collections::BTreeMap,
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format,
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string::{String, ToString},
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vec::Vec,
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};
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use anyhow::{Result, bail};
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use arm_attr::{BuildAttrs, enums::CpuArch, tag::Tag};
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use object::{Endian as _, Object as _, ObjectSection as _, ObjectSymbol as _, elf};
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use unarm::{args, arm, thumb};
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use crate::{
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arch::Arch,
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diff::{ArmArchVersion, ArmR9Usage, DiffObjConfig, display::InstructionPart},
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obj::{
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InstructionRef, Relocation, RelocationFlags, ResolvedInstructionRef, ResolvedRelocation,
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Section, SectionKind, Symbol, SymbolFlag, SymbolFlagSet, SymbolKind,
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},
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};
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#[derive(Debug)]
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pub struct ArchArm {
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/// Maps section index, to list of disasm modes (arm, thumb or data) sorted by address
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disasm_modes: BTreeMap<usize, Vec<DisasmMode>>,
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detected_version: Option<unarm::ArmVersion>,
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endianness: object::Endianness,
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}
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impl ArchArm {
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pub fn new(file: &object::File) -> Result<Self> {
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let endianness = file.endianness();
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match file {
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object::File::Elf32(_) => {
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// The disasm_modes mapping is populated later in the post_init step so that we have access to merged sections.
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let disasm_modes = BTreeMap::new();
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let detected_version = Self::elf_detect_arm_version(file)?;
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Ok(Self { disasm_modes, detected_version, endianness })
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}
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_ => bail!("Unsupported file format {:?}", file.format()),
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}
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}
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fn elf_detect_arm_version(file: &object::File) -> Result<Option<unarm::ArmVersion>> {
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// Check ARM attributes
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if let Some(arm_attrs) = file.sections().find(|s| {
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s.kind() == object::SectionKind::Elf(elf::SHT_ARM_ATTRIBUTES)
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&& s.name() == Ok(".ARM.attributes")
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}) {
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let attr_data = arm_attrs.uncompressed_data()?;
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let build_attrs = BuildAttrs::new(&attr_data, match file.endianness() {
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object::Endianness::Little => arm_attr::Endian::Little,
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object::Endianness::Big => arm_attr::Endian::Big,
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})?;
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for subsection in build_attrs.subsections() {
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let subsection = subsection?;
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if !subsection.is_aeabi() {
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continue;
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}
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// Only checking first CpuArch tag. Others may exist, but that's very unlikely.
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let cpu_arch = subsection.into_public_tag_iter()?.find_map(|(_, tag)| {
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if let Tag::CpuArch(cpu_arch) = tag { Some(cpu_arch) } else { None }
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});
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match cpu_arch {
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Some(CpuArch::V4T) => return Ok(Some(unarm::ArmVersion::V4T)),
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Some(CpuArch::V5TE) => return Ok(Some(unarm::ArmVersion::V5Te)),
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Some(CpuArch::V6K) => return Ok(Some(unarm::ArmVersion::V6K)),
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Some(arch) => bail!("ARM arch {} not supported", arch),
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None => {}
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};
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}
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}
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Ok(None)
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}
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fn get_mapping_symbols(
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sections: &[Section],
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symbols: &[Symbol],
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) -> BTreeMap<usize, Vec<DisasmMode>> {
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sections
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.iter()
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.enumerate()
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.filter(|(_, section)| section.kind == SectionKind::Code)
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.map(|(index, _)| {
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let mut mapping_symbols: Vec<_> = symbols
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.iter()
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.filter(|s| s.section.map(|i| i == index).unwrap_or(false))
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.filter_map(DisasmMode::from_symbol)
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.collect();
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mapping_symbols.sort_unstable_by_key(|x| x.address);
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(index, mapping_symbols)
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})
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.collect()
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}
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fn parse_flags(&self, diff_config: &DiffObjConfig) -> unarm::ParseFlags {
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unarm::ParseFlags {
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ual: diff_config.arm_unified_syntax,
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version: match diff_config.arm_arch_version {
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ArmArchVersion::Auto => self.detected_version.unwrap_or(unarm::ArmVersion::V5Te),
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ArmArchVersion::V4t => unarm::ArmVersion::V4T,
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ArmArchVersion::V5te => unarm::ArmVersion::V5Te,
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ArmArchVersion::V6k => unarm::ArmVersion::V6K,
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},
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}
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}
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fn display_options(&self, diff_config: &DiffObjConfig) -> unarm::DisplayOptions {
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unarm::DisplayOptions {
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reg_names: unarm::RegNames {
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av_registers: diff_config.arm_av_registers,
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r9_use: match diff_config.arm_r9_usage {
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ArmR9Usage::GeneralPurpose => unarm::R9Use::GeneralPurpose,
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ArmR9Usage::Sb => unarm::R9Use::Pid,
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ArmR9Usage::Tr => unarm::R9Use::Tls,
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},
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explicit_stack_limit: diff_config.arm_sl_usage,
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frame_pointer: diff_config.arm_fp_usage,
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ip: diff_config.arm_ip_usage,
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},
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}
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}
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fn parse_ins_ref(
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&self,
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ins_ref: InstructionRef,
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code: &[u8],
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diff_config: &DiffObjConfig,
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) -> Result<(unarm::Ins, unarm::ParsedIns)> {
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if ins_ref.opcode == thumb::Opcode::BlH as u16 && ins_ref.size == 4 {
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// Special case: combined thumb BL instruction
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let parse_flags = self.parse_flags(diff_config);
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let first_ins = thumb::Ins {
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code: match self.endianness {
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object::Endianness::Little => u16::from_le_bytes([code[0], code[1]]),
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object::Endianness::Big => u16::from_be_bytes([code[0], code[1]]),
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} as u32,
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op: thumb::Opcode::BlH,
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};
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let second_ins = thumb::Ins::new(
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match self.endianness {
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object::Endianness::Little => u16::from_le_bytes([code[2], code[3]]),
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object::Endianness::Big => u16::from_be_bytes([code[2], code[3]]),
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} as u32,
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&parse_flags,
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);
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let first_parsed = first_ins.parse(&parse_flags);
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let second_parsed = second_ins.parse(&parse_flags);
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return Ok((
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unarm::Ins::Thumb(first_ins),
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first_parsed.combine_thumb_bl(&second_parsed),
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));
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}
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let code = match (self.endianness, ins_ref.size) {
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(object::Endianness::Little, 2) => u16::from_le_bytes([code[0], code[1]]) as u32,
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(object::Endianness::Little, 4) => {
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u32::from_le_bytes([code[0], code[1], code[2], code[3]])
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}
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(object::Endianness::Big, 2) => u16::from_be_bytes([code[0], code[1]]) as u32,
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(object::Endianness::Big, 4) => {
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u32::from_be_bytes([code[0], code[1], code[2], code[3]])
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}
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_ => bail!("Invalid instruction size {}", ins_ref.size),
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};
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let (ins, parsed_ins) = if ins_ref.opcode == u16::MAX {
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let mut args = args::Arguments::default();
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args[0] = args::Argument::UImm(code);
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let mnemonic = if ins_ref.size == 4 { ".word" } else { ".hword" };
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(unarm::Ins::Data, unarm::ParsedIns { mnemonic, args })
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} else if ins_ref.opcode & (1 << 15) != 0 {
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let ins = arm::Ins { code, op: arm::Opcode::from(ins_ref.opcode as u8) };
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let parsed = ins.parse(&self.parse_flags(diff_config));
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(unarm::Ins::Arm(ins), parsed)
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} else {
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let ins = thumb::Ins { code, op: thumb::Opcode::from(ins_ref.opcode as u8) };
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let parsed = ins.parse(&self.parse_flags(diff_config));
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(unarm::Ins::Thumb(ins), parsed)
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};
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Ok((ins, parsed_ins))
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}
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}
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impl Arch for ArchArm {
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fn post_init(&mut self, sections: &[Section], symbols: &[Symbol]) {
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self.disasm_modes = Self::get_mapping_symbols(sections, symbols);
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}
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fn scan_instructions_internal(
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&self,
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address: u64,
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code: &[u8],
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section_index: usize,
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_relocations: &[Relocation],
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diff_config: &DiffObjConfig,
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) -> Result<Vec<InstructionRef>> {
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let start_addr = address as u32;
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let end_addr = start_addr + code.len() as u32;
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// Mapping symbols decide what kind of data comes after it. $a for ARM code, $t for Thumb code and $d for data.
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let fallback_mappings =
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[DisasmMode { address: start_addr, mapping: unarm::ParseMode::Arm }];
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let mapping_symbols = self
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.disasm_modes
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.get(§ion_index)
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.map(|x| x.as_slice())
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.unwrap_or(&fallback_mappings);
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let first_mapping_idx = mapping_symbols
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.binary_search_by_key(&start_addr, |x| x.address)
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.unwrap_or_else(|idx| idx.saturating_sub(1));
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let mut mode = mapping_symbols[first_mapping_idx].mapping;
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let mut mappings_iter = mapping_symbols
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.iter()
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.copied()
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.skip(first_mapping_idx + 1)
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.take_while(|x| x.address < end_addr);
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let mut next_mapping = mappings_iter.next();
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let ins_count = code.len() / mode.instruction_size(start_addr);
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let mut ops = Vec::<InstructionRef>::with_capacity(ins_count);
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let parse_flags = self.parse_flags(diff_config);
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let mut address = start_addr;
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while address < end_addr {
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while let Some(next) = next_mapping.filter(|x| address >= x.address) {
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// Change mapping
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mode = next.mapping;
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next_mapping = mappings_iter.next();
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}
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let mut ins_size = mode.instruction_size(address);
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let data = &code[(address - start_addr) as usize..];
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if data.len() < ins_size {
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// Push the remainder as data
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ops.push(InstructionRef {
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address: address as u64,
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size: data.len() as u8,
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opcode: u16::MAX,
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branch_dest: None,
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});
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break;
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}
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let code = match (self.endianness, ins_size) {
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(object::Endianness::Little, 2) => u16::from_le_bytes([data[0], data[1]]) as u32,
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(object::Endianness::Little, 4) => {
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u32::from_le_bytes([data[0], data[1], data[2], data[3]])
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}
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(object::Endianness::Big, 2) => u16::from_be_bytes([data[0], data[1]]) as u32,
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(object::Endianness::Big, 4) => {
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u32::from_be_bytes([data[0], data[1], data[2], data[3]])
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}
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_ => {
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// Invalid instruction size
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ops.push(InstructionRef {
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address: address as u64,
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size: ins_size as u8,
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opcode: u16::MAX,
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branch_dest: None,
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});
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address += ins_size as u32;
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continue;
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}
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};
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let (opcode, branch_dest) = match mode {
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unarm::ParseMode::Arm => {
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let ins = arm::Ins::new(code, &parse_flags);
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let opcode = ins.op as u16 | (1 << 15);
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let branch_dest = match ins.op {
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arm::Opcode::B | arm::Opcode::Bl => {
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address.checked_add_signed(ins.field_branch_offset())
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}
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arm::Opcode::BlxI => address.checked_add_signed(ins.field_blx_offset()),
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_ => None,
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};
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(opcode, branch_dest)
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}
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unarm::ParseMode::Thumb => {
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let ins = thumb::Ins::new(code, &parse_flags);
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let opcode = ins.op as u16;
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let branch_dest = match ins.op {
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thumb::Opcode::B | thumb::Opcode::Bl => {
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address.checked_add_signed(ins.field_branch_offset_8())
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}
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thumb::Opcode::BlH if data.len() >= 4 => {
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// Combine BL instructions
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let second_ins = thumb::Ins::new(
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match self.endianness {
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object::Endianness::Little => {
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u16::from_le_bytes([data[2], data[3]]) as u32
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}
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object::Endianness::Big => {
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u16::from_be_bytes([data[2], data[3]]) as u32
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}
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},
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&parse_flags,
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);
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if let Some(low) = match second_ins.op {
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thumb::Opcode::Bl => Some(second_ins.field_low_branch_offset_11()),
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thumb::Opcode::BlxI => Some(second_ins.field_low_blx_offset_11()),
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_ => None,
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} {
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ins_size = 4;
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address.checked_add_signed(
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(ins.field_high_branch_offset_11() + (low as i32)) << 9 >> 9,
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)
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} else {
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None
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}
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}
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thumb::Opcode::BLong => {
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address.checked_add_signed(ins.field_branch_offset_11())
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}
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_ => None,
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};
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(opcode, branch_dest)
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}
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unarm::ParseMode::Data => (u16::MAX, None),
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};
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ops.push(InstructionRef {
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address: address as u64,
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size: ins_size as u8,
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opcode,
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branch_dest: branch_dest.map(|x| x as u64),
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});
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address += ins_size as u32;
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}
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Ok(ops)
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}
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fn display_instruction(
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&self,
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resolved: ResolvedInstructionRef,
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diff_config: &DiffObjConfig,
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cb: &mut dyn FnMut(InstructionPart) -> Result<()>,
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) -> Result<()> {
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let (ins, parsed_ins) = self.parse_ins_ref(resolved.ins_ref, resolved.code, diff_config)?;
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cb(InstructionPart::opcode(parsed_ins.mnemonic, resolved.ins_ref.opcode))?;
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if ins == unarm::Ins::Data && resolved.relocation.is_some() {
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cb(InstructionPart::reloc())?;
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} else {
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push_args(
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ins,
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&parsed_ins,
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resolved.relocation,
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resolved.ins_ref.address as u32,
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self.display_options(diff_config),
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cb,
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)?;
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}
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Ok(())
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}
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fn implcit_addend(
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&self,
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_file: &object::File<'_>,
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section: &object::Section,
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address: u64,
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_relocation: &object::Relocation,
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flags: RelocationFlags,
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) -> Result<i64> {
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let section_data = section.data()?;
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let address = address as usize;
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Ok(match flags {
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// ARM calls
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RelocationFlags::Elf(elf::R_ARM_PC24)
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| RelocationFlags::Elf(elf::R_ARM_XPC25)
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| RelocationFlags::Elf(elf::R_ARM_CALL) => {
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let data = section_data[address..address + 4].try_into()?;
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let addend = self.endianness.read_i32_bytes(data);
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let imm24 = addend & 0xffffff;
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(imm24 << 2) << 8 >> 8
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}
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// Thumb calls
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RelocationFlags::Elf(elf::R_ARM_THM_PC22)
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| RelocationFlags::Elf(elf::R_ARM_THM_XPC22) => {
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let data = section_data[address..address + 2].try_into()?;
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let high = self.endianness.read_i16_bytes(data) as i32;
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let data = section_data[address + 2..address + 4].try_into()?;
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let low = self.endianness.read_i16_bytes(data) as i32;
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let imm22 = ((high & 0x7ff) << 11) | (low & 0x7ff);
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(imm22 << 1) << 9 >> 9
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}
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// Data
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RelocationFlags::Elf(elf::R_ARM_ABS32) => {
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let data = section_data[address..address + 4].try_into()?;
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self.endianness.read_i32_bytes(data)
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}
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flags => bail!("Unsupported ARM implicit relocation {flags:?}"),
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} as i64)
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}
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fn demangle(&self, name: &str) -> Option<String> {
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cpp_demangle::Symbol::new(name)
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.ok()
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.and_then(|s| s.demangle(&cpp_demangle::DemangleOptions::default()).ok())
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}
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fn reloc_name(&self, flags: RelocationFlags) -> Option<&'static str> {
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match flags {
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RelocationFlags::Elf(r_type) => match r_type {
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elf::R_ARM_NONE => Some("R_ARM_NONE"),
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elf::R_ARM_ABS32 => Some("R_ARM_ABS32"),
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elf::R_ARM_REL32 => Some("R_ARM_REL32"),
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elf::R_ARM_ABS16 => Some("R_ARM_ABS16"),
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elf::R_ARM_ABS8 => Some("R_ARM_ABS8"),
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elf::R_ARM_THM_PC22 => Some("R_ARM_THM_PC22"),
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elf::R_ARM_THM_XPC22 => Some("R_ARM_THM_XPC22"),
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elf::R_ARM_PC24 => Some("R_ARM_PC24"),
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elf::R_ARM_XPC25 => Some("R_ARM_XPC25"),
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elf::R_ARM_CALL => Some("R_ARM_CALL"),
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_ => None,
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},
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_ => None,
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}
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}
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fn data_reloc_size(&self, flags: RelocationFlags) -> usize {
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match flags {
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RelocationFlags::Elf(r_type) => match r_type {
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elf::R_ARM_NONE => 0,
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elf::R_ARM_ABS32 => 4,
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elf::R_ARM_REL32 => 4,
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elf::R_ARM_ABS16 => 2,
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elf::R_ARM_ABS8 => 1,
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elf::R_ARM_THM_PC22 => 4,
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elf::R_ARM_THM_XPC22 => 4,
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elf::R_ARM_PC24 => 4,
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elf::R_ARM_XPC25 => 4,
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elf::R_ARM_CALL => 4,
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_ => 1,
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},
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_ => 1,
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}
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}
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fn symbol_address(&self, address: u64, kind: SymbolKind) -> u64 {
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if kind == SymbolKind::Function { address & !1 } else { address }
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}
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fn extra_symbol_flags(&self, symbol: &object::Symbol) -> SymbolFlagSet {
|
|
let mut flags = SymbolFlagSet::default();
|
|
if DisasmMode::from_object_symbol(symbol).is_some() {
|
|
flags |= SymbolFlag::Hidden;
|
|
}
|
|
flags
|
|
}
|
|
}
|
|
|
|
#[derive(Clone, Copy, Debug)]
|
|
struct DisasmMode {
|
|
address: u32,
|
|
mapping: unarm::ParseMode,
|
|
}
|
|
|
|
impl DisasmMode {
|
|
fn from_object_symbol<'a>(sym: &object::Symbol<'a, '_, &'a [u8]>) -> Option<Self> {
|
|
sym.name()
|
|
.ok()
|
|
.and_then(unarm::ParseMode::from_mapping_symbol)
|
|
.map(|mapping| DisasmMode { address: sym.address() as u32, mapping })
|
|
}
|
|
|
|
fn from_symbol(sym: &Symbol) -> Option<Self> {
|
|
unarm::ParseMode::from_mapping_symbol(&sym.name)
|
|
.map(|mapping| DisasmMode { address: sym.address as u32, mapping })
|
|
}
|
|
}
|
|
|
|
fn push_args(
|
|
ins: unarm::Ins,
|
|
parsed_ins: &unarm::ParsedIns,
|
|
relocation: Option<ResolvedRelocation>,
|
|
cur_addr: u32,
|
|
display_options: unarm::DisplayOptions,
|
|
mut arg_cb: impl FnMut(InstructionPart) -> Result<()>,
|
|
) -> Result<()> {
|
|
let reloc_arg = find_reloc_arg(parsed_ins, relocation);
|
|
let mut writeback = false;
|
|
let mut deref = false;
|
|
for (i, &arg) in parsed_ins.args_iter().enumerate() {
|
|
// Emit punctuation before separator
|
|
if deref {
|
|
match arg {
|
|
args::Argument::OffsetImm(args::OffsetImm { post_indexed: true, value: _ })
|
|
| args::Argument::OffsetReg(args::OffsetReg {
|
|
add: _,
|
|
post_indexed: true,
|
|
reg: _,
|
|
})
|
|
| args::Argument::CoOption(_) => {
|
|
deref = false;
|
|
arg_cb(InstructionPart::basic("]"))?;
|
|
if writeback {
|
|
writeback = false;
|
|
arg_cb(InstructionPart::opaque("!"))?;
|
|
}
|
|
}
|
|
_ => {}
|
|
}
|
|
}
|
|
|
|
if i > 0 {
|
|
arg_cb(InstructionPart::separator())?;
|
|
}
|
|
|
|
if reloc_arg == Some(i) {
|
|
arg_cb(InstructionPart::reloc())?;
|
|
} else {
|
|
match arg {
|
|
args::Argument::None => {}
|
|
args::Argument::Reg(reg) => {
|
|
if reg.deref {
|
|
deref = true;
|
|
arg_cb(InstructionPart::basic("["))?;
|
|
}
|
|
arg_cb(InstructionPart::opaque(
|
|
reg.reg.display(display_options.reg_names).to_string(),
|
|
))?;
|
|
if reg.writeback {
|
|
if reg.deref {
|
|
writeback = true;
|
|
} else {
|
|
arg_cb(InstructionPart::opaque("!"))?;
|
|
}
|
|
}
|
|
}
|
|
args::Argument::RegList(reg_list) => {
|
|
arg_cb(InstructionPart::basic("{"))?;
|
|
let mut first = true;
|
|
for i in 0..16 {
|
|
if (reg_list.regs & (1 << i)) != 0 {
|
|
if !first {
|
|
arg_cb(InstructionPart::separator())?;
|
|
}
|
|
arg_cb(InstructionPart::opaque(
|
|
args::Register::parse(i)
|
|
.display(display_options.reg_names)
|
|
.to_string(),
|
|
))?;
|
|
first = false;
|
|
}
|
|
}
|
|
arg_cb(InstructionPart::basic("}"))?;
|
|
if reg_list.user_mode {
|
|
arg_cb(InstructionPart::opaque("^"))?;
|
|
}
|
|
}
|
|
args::Argument::UImm(value)
|
|
| args::Argument::CoOpcode(value)
|
|
| args::Argument::SatImm(value) => {
|
|
arg_cb(InstructionPart::basic("#"))?;
|
|
arg_cb(InstructionPart::unsigned(value))?;
|
|
}
|
|
args::Argument::SImm(value)
|
|
| args::Argument::OffsetImm(args::OffsetImm { post_indexed: _, value }) => {
|
|
arg_cb(InstructionPart::basic("#"))?;
|
|
arg_cb(InstructionPart::signed(value))?;
|
|
}
|
|
args::Argument::BranchDest(value) => {
|
|
arg_cb(InstructionPart::branch_dest(cur_addr.wrapping_add_signed(value)))?;
|
|
}
|
|
args::Argument::CoOption(value) => {
|
|
arg_cb(InstructionPart::basic("{"))?;
|
|
arg_cb(InstructionPart::unsigned(value))?;
|
|
arg_cb(InstructionPart::basic("}"))?;
|
|
}
|
|
args::Argument::CoprocNum(value) => {
|
|
arg_cb(InstructionPart::opaque(format!("p{}", value)))?;
|
|
}
|
|
args::Argument::ShiftImm(shift) => {
|
|
arg_cb(InstructionPart::opaque(shift.op.to_string()))?;
|
|
arg_cb(InstructionPart::basic(" #"))?;
|
|
arg_cb(InstructionPart::unsigned(shift.imm))?;
|
|
}
|
|
args::Argument::ShiftReg(shift) => {
|
|
arg_cb(InstructionPart::opaque(shift.op.to_string()))?;
|
|
arg_cb(InstructionPart::basic(" "))?;
|
|
arg_cb(InstructionPart::opaque(
|
|
shift.reg.display(display_options.reg_names).to_string(),
|
|
))?;
|
|
}
|
|
args::Argument::OffsetReg(offset) => {
|
|
if !offset.add {
|
|
arg_cb(InstructionPart::basic("-"))?;
|
|
}
|
|
arg_cb(InstructionPart::opaque(
|
|
offset.reg.display(display_options.reg_names).to_string(),
|
|
))?;
|
|
}
|
|
args::Argument::CpsrMode(mode) => {
|
|
arg_cb(InstructionPart::basic("#"))?;
|
|
arg_cb(InstructionPart::unsigned(mode.mode))?;
|
|
if mode.writeback {
|
|
arg_cb(InstructionPart::opaque("!"))?;
|
|
}
|
|
}
|
|
args::Argument::CoReg(_)
|
|
| args::Argument::StatusReg(_)
|
|
| args::Argument::StatusMask(_)
|
|
| args::Argument::Shift(_)
|
|
| args::Argument::CpsrFlags(_)
|
|
| args::Argument::Endian(_) => {
|
|
arg_cb(InstructionPart::opaque(
|
|
arg.display(display_options, None).to_string(),
|
|
))?;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
if deref {
|
|
arg_cb(InstructionPart::basic("]"))?;
|
|
if writeback {
|
|
arg_cb(InstructionPart::opaque("!"))?;
|
|
}
|
|
}
|
|
|
|
let branch_dest = get_pc_relative_load_address(ins, cur_addr);
|
|
if let Some(branch_dest) = branch_dest {
|
|
arg_cb(InstructionPart::basic(" (->"))?;
|
|
arg_cb(InstructionPart::branch_dest(branch_dest))?;
|
|
arg_cb(InstructionPart::basic(")"))?;
|
|
}
|
|
|
|
Ok(())
|
|
}
|
|
|
|
fn find_reloc_arg(
|
|
parsed_ins: &unarm::ParsedIns,
|
|
relocation: Option<ResolvedRelocation>,
|
|
) -> Option<usize> {
|
|
if let Some(resolved) = relocation {
|
|
match resolved.relocation.flags {
|
|
// Calls
|
|
RelocationFlags::Elf(elf::R_ARM_THM_XPC22)
|
|
| RelocationFlags::Elf(elf::R_ARM_THM_PC22)
|
|
| RelocationFlags::Elf(elf::R_ARM_PC24)
|
|
| RelocationFlags::Elf(elf::R_ARM_XPC25)
|
|
| RelocationFlags::Elf(elf::R_ARM_CALL) => {
|
|
parsed_ins.args.iter().rposition(|a| matches!(a, args::Argument::BranchDest(_)))
|
|
}
|
|
// Data
|
|
RelocationFlags::Elf(elf::R_ARM_ABS32) => {
|
|
parsed_ins.args.iter().rposition(|a| matches!(a, args::Argument::UImm(_)))
|
|
}
|
|
_ => None,
|
|
}
|
|
} else {
|
|
None
|
|
}
|
|
}
|
|
|
|
fn get_pc_relative_load_address(ins: unarm::Ins, address: u32) -> Option<u32> {
|
|
match ins {
|
|
unarm::Ins::Arm(ins)
|
|
if ins.op == arm::Opcode::Ldr
|
|
&& ins.modifier_addr_ldr_str() == arm::AddrLdrStr::Imm
|
|
&& ins.field_rn_deref().reg == args::Register::Pc =>
|
|
{
|
|
let offset = ins.field_offset_12().value;
|
|
Some(address.wrapping_add_signed(offset + 8))
|
|
}
|
|
unarm::Ins::Thumb(ins) if ins.op == thumb::Opcode::LdrPc => {
|
|
let offset = ins.field_rel_immed_8().value;
|
|
Some((address & !3).wrapping_add_signed(offset + 4))
|
|
}
|
|
_ => None,
|
|
}
|
|
}
|