SPR names & mfspr/mtspr simplified mnemonics
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ca92a30920
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20abce13e4
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@ -1165,6 +1165,8 @@ pub enum Field {
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tbr(OpaqueU),
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mtfsf_FM(OpaqueU),
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mtfsf_IMM(OpaqueU),
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spr_SPRG(OpaqueU),
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spr_BAT(OpaqueU),
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TO(OpaqueU),
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L(OpaqueU),
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xer,
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@ -1212,6 +1214,8 @@ impl Field {
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Field::tbr(x) => Some(Argument::OpaqueU(*x)),
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Field::mtfsf_FM(x) => Some(Argument::OpaqueU(*x)),
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Field::mtfsf_IMM(x) => Some(Argument::OpaqueU(*x)),
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Field::spr_SPRG(x) => Some(Argument::OpaqueU(*x)),
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Field::spr_BAT(x) => Some(Argument::OpaqueU(*x)),
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Field::TO(x) => Some(Argument::OpaqueU(*x)),
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Field::L(x) => Some(Argument::OpaqueU(*x)),
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_ => None,
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@ -1257,6 +1261,8 @@ impl Field {
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Field::tbr(_) => "tbr",
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Field::mtfsf_FM(_) => "mtfsf_FM",
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Field::mtfsf_IMM(_) => "mtfsf_IMM",
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Field::spr_SPRG(_) => "spr_SPRG",
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Field::spr_BAT(_) => "spr_BAT",
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Field::TO(_) => "TO",
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Field::L(_) => "L",
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Field::xer => "xer",
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@ -5699,11 +5705,141 @@ impl Ins {
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if (((((self.code >> 11u8) & 0x3ff) & 0b11111_00000u32) >> 5u32)
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| ((((self.code >> 11u8) & 0x3ff) & 0b00000_11111u32) << 5u32))
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as u32
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== 397
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== 19
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{
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return SimplifiedIns {
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mnemonic: "mfdar",
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args: vec![Argument::GPR(GPR(((self.code >> 21u8) & 0x1f) as _))],
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ins: self,
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};
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}
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if (((((self.code >> 11u8) & 0x3ff) & 0b11111_00000u32) >> 5u32)
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| ((((self.code >> 11u8) & 0x3ff) & 0b00000_11111u32) << 5u32))
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as u32
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== 22
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{
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return SimplifiedIns {
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mnemonic: "mfdec",
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args: vec![Argument::GPR(GPR(((self.code >> 21u8) & 0x1f) as _))],
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ins: self,
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};
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}
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if (((((self.code >> 11u8) & 0x3ff) & 0b11111_00000u32) >> 5u32)
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| ((((self.code >> 11u8) & 0x3ff) & 0b00000_11111u32) << 5u32))
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as u32
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== 25
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{
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return SimplifiedIns {
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mnemonic: "mfsdr1",
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args: vec![Argument::GPR(GPR(((self.code >> 21u8) & 0x1f) as _))],
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ins: self,
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};
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}
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if (((((self.code >> 11u8) & 0x3ff) & 0b11111_00000u32) >> 5u32)
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| ((((self.code >> 11u8) & 0x3ff) & 0b00000_11111u32) << 5u32))
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as u32
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== 26
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{
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return SimplifiedIns {
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mnemonic: "mfsrr0",
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args: vec![Argument::GPR(GPR(((self.code >> 21u8) & 0x1f) as _))],
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ins: self,
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};
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}
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if (((((self.code >> 11u8) & 0x3ff) & 0b11111_00000u32) >> 5u32)
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| ((((self.code >> 11u8) & 0x3ff) & 0b00000_11111u32) << 5u32))
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as u32
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== 27
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{
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return SimplifiedIns {
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mnemonic: "mfsrr1",
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args: vec![Argument::GPR(GPR(((self.code >> 21u8) & 0x1f) as _))],
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ins: self,
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};
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}
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if (((((self.code >> 11u8) & 0x3ff) & 0b11111_00000u32) >> 5u32)
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| ((((self.code >> 11u8) & 0x3ff) & 0b00000_11111u32) << 5u32))
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as u32
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& 0b1111111100
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== 272
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{
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return SimplifiedIns {
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mnemonic: "mfsprg",
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args: vec![
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Argument::GPR(GPR(((self.code >> 21u8) & 0x1f) as _)),
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Argument::OpaqueU(OpaqueU(((self.code >> 16u8) & 0x3) as _)),
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],
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ins: self,
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};
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}
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if (((((self.code >> 11u8) & 0x3ff) & 0b11111_00000u32) >> 5u32)
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| ((((self.code >> 11u8) & 0x3ff) & 0b00000_11111u32) << 5u32))
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as u32
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== 282
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{
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return SimplifiedIns {
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mnemonic: "mfear",
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args: vec![Argument::GPR(GPR(((self.code >> 21u8) & 0x1f) as _))],
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ins: self,
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};
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}
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if (((((self.code >> 11u8) & 0x3ff) & 0b11111_00000u32) >> 5u32)
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| ((((self.code >> 11u8) & 0x3ff) & 0b00000_11111u32) << 5u32))
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as u32
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& 0b1111111001
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== 528
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{
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return SimplifiedIns {
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mnemonic: "mfibatu",
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args: vec![
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Argument::GPR(GPR(((self.code >> 21u8) & 0x1f) as _)),
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Argument::OpaqueU(OpaqueU(((self.code >> 17u8) & 0x3) as _)),
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],
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ins: self,
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};
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}
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if (((((self.code >> 11u8) & 0x3ff) & 0b11111_00000u32) >> 5u32)
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| ((((self.code >> 11u8) & 0x3ff) & 0b00000_11111u32) << 5u32))
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as u32
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& 0b1111111001
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== 529
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{
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return SimplifiedIns {
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mnemonic: "mfibatl",
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args: vec![
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Argument::GPR(GPR(((self.code >> 21u8) & 0x1f) as _)),
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Argument::OpaqueU(OpaqueU(((self.code >> 17u8) & 0x3) as _)),
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],
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ins: self,
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};
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}
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if (((((self.code >> 11u8) & 0x3ff) & 0b11111_00000u32) >> 5u32)
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| ((((self.code >> 11u8) & 0x3ff) & 0b00000_11111u32) << 5u32))
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as u32
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& 0b1111111001
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== 536
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{
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return SimplifiedIns {
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mnemonic: "mfdbatu",
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args: vec![Argument::GPR(GPR(((self.code >> 21u8) & 0x1f) as _))],
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args: vec![
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Argument::GPR(GPR(((self.code >> 21u8) & 0x1f) as _)),
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Argument::OpaqueU(OpaqueU(((self.code >> 17u8) & 0x3) as _)),
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],
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ins: self,
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};
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}
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if (((((self.code >> 11u8) & 0x3ff) & 0b11111_00000u32) >> 5u32)
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| ((((self.code >> 11u8) & 0x3ff) & 0b00000_11111u32) << 5u32))
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as u32
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& 0b1111111001
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== 537
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{
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return SimplifiedIns {
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mnemonic: "mfdbatl",
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args: vec![
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Argument::GPR(GPR(((self.code >> 21u8) & 0x1f) as _)),
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Argument::OpaqueU(OpaqueU(((self.code >> 17u8) & 0x3) as _)),
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],
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ins: self,
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};
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}
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@ -5756,11 +5892,163 @@ impl Ins {
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if (((((self.code >> 11u8) & 0x3ff) & 0b11111_00000u32) >> 5u32)
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| ((((self.code >> 11u8) & 0x3ff) & 0b00000_11111u32) << 5u32))
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as u32
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== 397
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== 19
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{
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return SimplifiedIns {
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mnemonic: "mtdar",
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args: vec![Argument::GPR(GPR(((self.code >> 21u8) & 0x1f) as _))],
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ins: self,
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};
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}
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if (((((self.code >> 11u8) & 0x3ff) & 0b11111_00000u32) >> 5u32)
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| ((((self.code >> 11u8) & 0x3ff) & 0b00000_11111u32) << 5u32))
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as u32
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== 22
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{
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return SimplifiedIns {
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mnemonic: "mtdec",
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args: vec![Argument::GPR(GPR(((self.code >> 21u8) & 0x1f) as _))],
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ins: self,
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};
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}
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if (((((self.code >> 11u8) & 0x3ff) & 0b11111_00000u32) >> 5u32)
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| ((((self.code >> 11u8) & 0x3ff) & 0b00000_11111u32) << 5u32))
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as u32
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== 25
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{
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return SimplifiedIns {
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mnemonic: "mtsdr1",
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args: vec![Argument::GPR(GPR(((self.code >> 21u8) & 0x1f) as _))],
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ins: self,
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};
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}
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if (((((self.code >> 11u8) & 0x3ff) & 0b11111_00000u32) >> 5u32)
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| ((((self.code >> 11u8) & 0x3ff) & 0b00000_11111u32) << 5u32))
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as u32
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== 26
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{
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return SimplifiedIns {
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mnemonic: "mtsrr0",
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args: vec![Argument::GPR(GPR(((self.code >> 21u8) & 0x1f) as _))],
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ins: self,
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};
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}
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if (((((self.code >> 11u8) & 0x3ff) & 0b11111_00000u32) >> 5u32)
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| ((((self.code >> 11u8) & 0x3ff) & 0b00000_11111u32) << 5u32))
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as u32
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== 27
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{
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return SimplifiedIns {
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mnemonic: "mtsrr1",
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args: vec![Argument::GPR(GPR(((self.code >> 21u8) & 0x1f) as _))],
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ins: self,
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};
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}
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if (((((self.code >> 11u8) & 0x3ff) & 0b11111_00000u32) >> 5u32)
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| ((((self.code >> 11u8) & 0x3ff) & 0b00000_11111u32) << 5u32))
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as u32
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& 0b1111111100
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== 272
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{
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return SimplifiedIns {
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mnemonic: "mtsprg",
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args: vec![
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Argument::OpaqueU(OpaqueU(((self.code >> 16u8) & 0x3) as _)),
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Argument::GPR(GPR(((self.code >> 21u8) & 0x1f) as _)),
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],
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ins: self,
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};
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}
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if (((((self.code >> 11u8) & 0x3ff) & 0b11111_00000u32) >> 5u32)
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| ((((self.code >> 11u8) & 0x3ff) & 0b00000_11111u32) << 5u32))
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as u32
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== 282
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{
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return SimplifiedIns {
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mnemonic: "mtear",
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args: vec![Argument::GPR(GPR(((self.code >> 21u8) & 0x1f) as _))],
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ins: self,
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};
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}
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if (((((self.code >> 11u8) & 0x3ff) & 0b11111_00000u32) >> 5u32)
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| ((((self.code >> 11u8) & 0x3ff) & 0b00000_11111u32) << 5u32))
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as u32
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== 284
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{
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return SimplifiedIns {
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mnemonic: "mttbl",
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args: vec![Argument::GPR(GPR(((self.code >> 21u8) & 0x1f) as _))],
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ins: self,
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};
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}
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if (((((self.code >> 11u8) & 0x3ff) & 0b11111_00000u32) >> 5u32)
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| ((((self.code >> 11u8) & 0x3ff) & 0b00000_11111u32) << 5u32))
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as u32
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== 285
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{
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return SimplifiedIns {
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mnemonic: "mttbu",
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args: vec![Argument::GPR(GPR(((self.code >> 21u8) & 0x1f) as _))],
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ins: self,
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};
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}
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if (((((self.code >> 11u8) & 0x3ff) & 0b11111_00000u32) >> 5u32)
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| ((((self.code >> 11u8) & 0x3ff) & 0b00000_11111u32) << 5u32))
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as u32
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& 0b1111111001
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== 528
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{
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return SimplifiedIns {
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mnemonic: "mtibatu",
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args: vec![
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Argument::OpaqueU(OpaqueU(((self.code >> 17u8) & 0x3) as _)),
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Argument::GPR(GPR(((self.code >> 21u8) & 0x1f) as _)),
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],
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ins: self,
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};
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}
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if (((((self.code >> 11u8) & 0x3ff) & 0b11111_00000u32) >> 5u32)
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| ((((self.code >> 11u8) & 0x3ff) & 0b00000_11111u32) << 5u32))
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as u32
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& 0b1111111001
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== 529
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{
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return SimplifiedIns {
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mnemonic: "mtibatl",
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args: vec![
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Argument::OpaqueU(OpaqueU(((self.code >> 17u8) & 0x3) as _)),
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Argument::GPR(GPR(((self.code >> 21u8) & 0x1f) as _)),
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],
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ins: self,
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};
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}
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if (((((self.code >> 11u8) & 0x3ff) & 0b11111_00000u32) >> 5u32)
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| ((((self.code >> 11u8) & 0x3ff) & 0b00000_11111u32) << 5u32))
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as u32
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& 0b1111111001
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== 536
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{
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return SimplifiedIns {
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mnemonic: "mtdbatu",
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args: vec![Argument::GPR(GPR(((self.code >> 21u8) & 0x1f) as _))],
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args: vec![
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Argument::OpaqueU(OpaqueU(((self.code >> 17u8) & 0x3) as _)),
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Argument::GPR(GPR(((self.code >> 21u8) & 0x1f) as _)),
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],
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ins: self,
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};
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}
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if (((((self.code >> 11u8) & 0x3ff) & 0b11111_00000u32) >> 5u32)
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| ((((self.code >> 11u8) & 0x3ff) & 0b00000_11111u32) << 5u32))
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as u32
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& 0b1111111001
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== 537
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{
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return SimplifiedIns {
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mnemonic: "mtdbatl",
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args: vec![
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Argument::OpaqueU(OpaqueU(((self.code >> 17u8) & 0x3) as _)),
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Argument::GPR(GPR(((self.code >> 21u8) & 0x1f) as _)),
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],
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ins: self,
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};
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}
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@ -6029,6 +6317,14 @@ impl Ins {
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((self.code >> 12u8) & 0xf) as _
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}
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#[inline(always)]
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pub fn field_spr_SPRG(&self) -> usize {
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((self.code >> 16u8) & 0x3) as _
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}
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#[inline(always)]
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pub fn field_spr_BAT(&self) -> usize {
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((self.code >> 17u8) & 0x3) as _
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}
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#[inline(always)]
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pub fn field_TO(&self) -> usize {
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((self.code >> 21u8) & 0x1f) as _
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}
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@ -104,7 +104,82 @@ field_arg!(FPR, u8, "f{}");
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// Segment register.
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field_arg!(SR, u8);
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// Special-purpose register.
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field_arg!(SPR, u16);
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field_arg_no_display!(SPR, u16);
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impl Display for SPR {
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fn fmt(&self, f: &mut Formatter<'_>) -> std::fmt::Result {
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f.write_str(match self.0 {
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1 => "XER",
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8 => "LR",
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9 => "CTR",
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18 => "DSISR",
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19 => "DAR",
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22 => "DEC",
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25 => "SDR1",
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26 => "SRR0",
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27 => "SRR1",
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272 => "SPRG0",
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273 => "SPRG1",
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274 => "SPRG2",
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275 => "SPRG3",
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282 => "EAR",
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287 => "PVR",
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528 => "IBAT0U",
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529 => "IBAT0L",
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530 => "IBAT1U",
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531 => "IBAT1L",
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532 => "IBAT2U",
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533 => "IBAT2L",
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534 => "IBAT3U",
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535 => "IBAT3L",
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536 => "DBAT0U",
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537 => "DBAT0L",
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538 => "DBAT1U",
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539 => "DBAT1L",
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540 => "DBAT2U",
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541 => "DBAT2L",
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542 => "DBAT3U",
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543 => "DBAT3L",
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912 => "GQR0",
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913 => "GQR1",
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914 => "GQR2",
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915 => "GQR3",
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916 => "GQR4",
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917 => "GQR5",
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918 => "GQR6",
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919 => "GQR7",
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920 => "HID2",
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921 => "WPAR",
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922 => "DMA_U",
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923 => "DMA_L",
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936 => "UMMCR0",
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937 => "UPMC1",
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938 => "UPMC2",
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939 => "USIA",
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940 => "UMMCR1",
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941 => "UPMC3",
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942 => "UPMC4",
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943 => "USDA",
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952 => "MMCR0",
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953 => "PMC1",
|
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954 => "PMC2",
|
||||
955 => "SIA",
|
||||
956 => "MMCR1",
|
||||
957 => "PMC3",
|
||||
958 => "PMC4",
|
||||
959 => "SDA",
|
||||
1008 => "HID0",
|
||||
1009 => "HID1",
|
||||
1010 => "IABR",
|
||||
1013 => "DABR",
|
||||
1017 => "L2CR",
|
||||
1019 => "ICTC",
|
||||
1020 => "THRM1",
|
||||
1021 => "THRM2",
|
||||
1022 => "THRM3",
|
||||
_ => return write!(f, "{}", self.0),
|
||||
})
|
||||
}
|
||||
}
|
||||
// Condition register field.
|
||||
field_arg!(CRField, u8, "cr{}");
|
||||
// Condition register bit (index + condition case).
|
||||
|
|
|
|||
|
|
@ -496,7 +496,10 @@ fn test_ins_mfmsr() {
|
|||
|
||||
#[test]
|
||||
fn test_ins_mfspr() {
|
||||
assert_asm!(0x7E1A02A6, "mfspr r16, 26");
|
||||
assert_asm!(0x7E1A02A6, "mfsrr0 r16");
|
||||
assert_asm!(0x7C70FAA6, "mfspr r3, HID0");
|
||||
assert_asm!(0x7C7482A6, "mfibatu r3, 2");
|
||||
assert_asm!(0x7C7782A6, "mfibatl r3, 3");
|
||||
}
|
||||
|
||||
#[test]
|
||||
|
|
@ -537,7 +540,16 @@ fn test_ins_mtmsr() {
|
|||
|
||||
#[test]
|
||||
fn test_ins_mtspr() {
|
||||
assert_asm!(0x7E75FBA6, "mtspr 1013, r19");
|
||||
assert_asm!(0x7E75FBA6, "mtspr DABR, r19");
|
||||
assert_asm!(0x7C70FBA6, "mtspr HID0, r3");
|
||||
assert_asm!(0x7C7603A6, "mtdec r3");
|
||||
assert_asm!(0x7C7043A6, "mtsprg 0, r3");
|
||||
assert_asm!(0x7C7143A6, "mtsprg 1, r3");
|
||||
assert_asm!(0x7C7343A6, "mtsprg 3, r3");
|
||||
assert_asm!(0x7C7083A6, "mtibatu 0, r3");
|
||||
assert_asm!(0x7C7483A6, "mtibatu 2, r3");
|
||||
assert_asm!(0x7C7783A6, "mtibatl 3, r3");
|
||||
assert_asm!(0x7C7D83A6, "mtdbatl 2, r3");
|
||||
}
|
||||
|
||||
#[test]
|
||||
|
|
|
|||
104
isa.yaml
104
isa.yaml
|
|
@ -141,6 +141,14 @@ fields:
|
|||
arg: OpaqueU
|
||||
desc: Immediate for mtfsfi
|
||||
bits: 16..20
|
||||
- name: spr_SPRG
|
||||
arg: OpaqueU
|
||||
desc: SPRG index for m[tf]sprg
|
||||
bits: 14..16
|
||||
- name: spr_BAT
|
||||
arg: OpaqueU
|
||||
desc: IBAT/DBAT index for m[tf][id]bat[ul]
|
||||
bits: 13..15
|
||||
- name: TO
|
||||
arg: OpaqueU
|
||||
desc: Bitset for tw and twi
|
||||
|
|
@ -2099,10 +2107,58 @@ mnemonics:
|
|||
opcode: mtspr
|
||||
args: [ rS ]
|
||||
condition: spr == 18
|
||||
- name: mtdbatu
|
||||
- name: mtdar
|
||||
opcode: mtspr
|
||||
args: [ rS ]
|
||||
condition: spr == 397
|
||||
condition: spr == 19
|
||||
- name: mtdec
|
||||
opcode: mtspr
|
||||
args: [ rS ]
|
||||
condition: spr == 22
|
||||
- name: mtsdr1
|
||||
opcode: mtspr
|
||||
args: [ rS ]
|
||||
condition: spr == 25
|
||||
- name: mtsrr0
|
||||
opcode: mtspr
|
||||
args: [ rS ]
|
||||
condition: spr == 26
|
||||
- name: mtsrr1
|
||||
opcode: mtspr
|
||||
args: [ rS ]
|
||||
condition: spr == 27
|
||||
- name: mtsprg
|
||||
opcode: mtspr
|
||||
args: [ spr_SPRG, rS ]
|
||||
condition: spr & 0b1111111100 == 272
|
||||
- name: mtear
|
||||
opcode: mtspr
|
||||
args: [ rS ]
|
||||
condition: spr == 282
|
||||
- name: mttbl
|
||||
opcode: mtspr
|
||||
args: [ rS ]
|
||||
condition: spr == 284
|
||||
- name: mttbu
|
||||
opcode: mtspr
|
||||
args: [ rS ]
|
||||
condition: spr == 285
|
||||
- name: mtibatu
|
||||
opcode: mtspr
|
||||
args: [ spr_BAT, rS ]
|
||||
condition: spr & 0b1111111001 == 528
|
||||
- name: mtibatl
|
||||
opcode: mtspr
|
||||
args: [ spr_BAT, rS ]
|
||||
condition: spr & 0b1111111001 == 529
|
||||
- name: mtdbatu
|
||||
opcode: mtspr
|
||||
args: [ spr_BAT, rS ]
|
||||
condition: spr & 0b1111111001 == 536
|
||||
- name: mtdbatl
|
||||
opcode: mtspr
|
||||
args: [ spr_BAT, rS ]
|
||||
condition: spr & 0b1111111001 == 537
|
||||
|
||||
# Move from special-purpose register
|
||||
- name: mfxer
|
||||
|
|
@ -2121,10 +2177,50 @@ mnemonics:
|
|||
opcode: mfspr
|
||||
args: [ rD ]
|
||||
condition: spr == 18
|
||||
- name: mfdbatu
|
||||
- name: mfdar
|
||||
opcode: mfspr
|
||||
args: [ rD ]
|
||||
condition: spr == 397
|
||||
condition: spr == 19
|
||||
- name: mfdec
|
||||
opcode: mfspr
|
||||
args: [ rD ]
|
||||
condition: spr == 22
|
||||
- name: mfsdr1
|
||||
opcode: mfspr
|
||||
args: [ rD ]
|
||||
condition: spr == 25
|
||||
- name: mfsrr0
|
||||
opcode: mfspr
|
||||
args: [ rD ]
|
||||
condition: spr == 26
|
||||
- name: mfsrr1
|
||||
opcode: mfspr
|
||||
args: [ rD ]
|
||||
condition: spr == 27
|
||||
- name: mfsprg
|
||||
opcode: mfspr
|
||||
args: [ rD, spr_SPRG ]
|
||||
condition: spr & 0b1111111100 == 272
|
||||
- name: mfear
|
||||
opcode: mfspr
|
||||
args: [ rD ]
|
||||
condition: spr == 282
|
||||
- name: mfibatu
|
||||
opcode: mfspr
|
||||
args: [ rD, spr_BAT ]
|
||||
condition: spr & 0b1111111001 == 528
|
||||
- name: mfibatl
|
||||
opcode: mfspr
|
||||
args: [ rD, spr_BAT ]
|
||||
condition: spr & 0b1111111001 == 529
|
||||
- name: mfdbatu
|
||||
opcode: mfspr
|
||||
args: [ rD, spr_BAT ]
|
||||
condition: spr & 0b1111111001 == 536
|
||||
- name: mfdbatl
|
||||
opcode: mfspr
|
||||
args: [ rD, spr_BAT ]
|
||||
condition: spr & 0b1111111001 == 537
|
||||
|
||||
# Branch Conditional
|
||||
# bc branch always
|
||||
|
|
|
|||
Loading…
Reference in New Issue