Codegen updates & instruction aliases

disasm/src/disasm.rs

@@ -294,7 +294,7 @@ impl From<u8> for OpaqueU {
     }
 }
 // Vector register.
-field_arg!(VR, u8, "vr{}");
+field_arg!(VR, u8, "v{}");
 
 #[derive(Debug, Default, Copy, Clone, Eq, Hash, PartialEq)]
 pub enum Argument {
@@ -373,7 +373,7 @@ impl Display for ParsedIns {
             } else if !writing_offset {
                 write!(f, ", ")?;
             }
-            write!(f, "{}", argument)?;
+            write!(f, "{argument}")?;
             if let Argument::Offset(_) = argument {
                 write!(f, "(")?;
                 writing_offset = true;

disasm/tests/test_altivec.rs

@@ -1,4 +1,4 @@
-use ppc750cl::{Argument, Ins, InsIter, Opcode, GPR};
+use ppc750cl::Ins;
 
 macro_rules! assert_asm {
     ($ins:ident, $disasm:literal) => {{
@@ -10,20 +10,10 @@ macro_rules! assert_asm {
     }};
 }
 
-macro_rules! assert_basic {
-    ($ins:ident, $disasm:literal) => {{
-        assert_eq!(format!("{}", $ins.basic_form()), $disasm)
-    }};
-    ($code:literal, $disasm:literal) => {{
-        let ins = Ins::new($code);
-        assert_eq!(format!("{}", ins.basic()), $disasm)
-    }};
-}
-
 #[test]
 fn test_vec_dss() {
     assert_asm!(0x7C60066C, "dss 3");
-    assert_asm!(0x7E60066C, "dssall");
+    assert_asm!(0x7E00066C, "dssall");
 }
 
 #[test]
@@ -40,790 +30,790 @@ fn test_vec_dstst(){
 
 #[test]
 fn test_vec_lvebx() {
-    assert_asm!(0x7C64380E, "lvebx vr3, r4, r7");
+    assert_asm!(0x7C64380E, "lvebx v3, r4, r7");
 }
 
 #[test]
 fn test_vec_lvehx() {
-    assert_asm!(0x7CA8F84E, "lvehx vr5, r8, r31");
+    assert_asm!(0x7CA8F84E, "lvehx v5, r8, r31");
 }
 
 #[test]
 fn test_vec_lvewx() {
-    assert_asm!(0x7D09508E, "lvewx vr8, r9, r10");
+    assert_asm!(0x7D09508E, "lvewx v8, r9, r10");
 }
 
 #[test]
 fn test_vec_lvsl() {
-    assert_asm!(0x7CA6480C, "lvsl vr5, r6, r9");
+    assert_asm!(0x7CA6480C, "lvsl v5, r6, r9");
 }
 
 #[test]
 fn test_vec_lvsr() {
-    assert_asm!(0x7C60284C, "lvsr vr3, r0, r5");
+    assert_asm!(0x7C60284C, "lvsr v3, r0, r5");
 }
 
 #[test]
 fn test_vec_lvx() {
-    assert_asm!(0x7CF2E8CE, "lvx vr7, r18, r29");
+    assert_asm!(0x7CF2E8CE, "lvx v7, r18, r29");
 }
 
 #[test]
 fn test_vec_lvxl() {
-    assert_asm!(0x7D17FACE, "lvxl vr8, r23, r31");
+    assert_asm!(0x7D17FACE, "lvxl v8, r23, r31");
 }
 
 #[test]
 fn test_vec_mfvscr() {
-    assert_asm!(0x13E00604, "mfvscr vr31");
+    assert_asm!(0x13E00604, "mfvscr v31");
 }
 
 #[test]
 fn test_vec_mtvscr() {
-    assert_asm!(0x1000CE44, "mtvscr vr25");
+    assert_asm!(0x1000CE44, "mtvscr v25");
 }
 
 #[test]
 fn test_vec_stvebx() {
-    assert_asm!(0x7CE3210E, "stvebx vr7, r3, r4");
+    assert_asm!(0x7CE3210E, "stvebx v7, r3, r4");
 }
 
 #[test]
 fn test_vec_stvehx() {
-    assert_asm!(0x7F25514E, "stvehx vr25, r5, r10");
+    assert_asm!(0x7F25514E, "stvehx v25, r5, r10");
 }
 
 #[test]
 fn test_vec_stvewx() {
-    assert_asm!(0x7E08498E, "stvewx vr16, r8, r9");
+    assert_asm!(0x7E08498E, "stvewx v16, r8, r9");
 }
 
 #[test]
 fn test_vec_stvx() {
-    assert_asm!(0x7FE039CE, "stvx vr31, r0, r7");
+    assert_asm!(0x7FE039CE, "stvx v31, r0, r7");
 }
 
 #[test]
 fn test_vec_stvxl() {
-    assert_asm!(0x7E8EF3CE, "stvxl vr20, r14, r30");
+    assert_asm!(0x7E8EF3CE, "stvxl v20, r14, r30");
 }
 
 #[test]
 fn test_vec_vaddcuw() {
-    assert_asm!(0x10A63980, "vaddcuw vr5, vr6, vr7");
+    assert_asm!(0x10A63980, "vaddcuw v5, v6, v7");
 }
 
 #[test]
 fn test_vec_vaddfp() {
-    assert_asm!(0x13BEF80A, "vaddfp vr29, vr30, vr31");
+    assert_asm!(0x13BEF80A, "vaddfp v29, v30, v31");
 }
 
 #[test]
 fn test_vec_vaddsbs() {
-    assert_asm!(0x10035300, "vaddsbs vr0, vr3, vr10");
+    assert_asm!(0x10035300, "vaddsbs v0, v3, v10");
 }
 
 #[test]
 fn test_vec_vaddsws() {
-    assert_asm!(0x11043B80, "vaddsws vr8, vr4, vr7");
+    assert_asm!(0x11043B80, "vaddsws v8, v4, v7");
 }
 
 #[test]
 fn test_vec_vaddubm() {
-    assert_asm!(0x100CE000, "vaddubm vr0, vr12, vr28");
+    assert_asm!(0x100CE000, "vaddubm v0, v12, v28");
 }
 
 #[test]
 fn test_vec_vaddubs() {
-    assert_asm!(0x10AACA00, "vaddubs vr5, vr10, vr25");
+    assert_asm!(0x10AACA00, "vaddubs v5, v10, v25");
 }
 
 #[test]
 fn test_vec_vadduhm() {
-    assert_asm!(0x1112E040, "vadduhm vr8, vr18, vr28");
+    assert_asm!(0x1112E040, "vadduhm v8, v18, v28");
 }
 
 #[test]
 fn test_vec_vadduhs() {
-    assert_asm!(0x1071EA40, "vadduhs vr3, vr17, vr29");
+    assert_asm!(0x1071EA40, "vadduhs v3, v17, v29");
 }
 
 #[test]
 fn test_vec_vadduwm() {
-    assert_asm!(0x10D6F080, "vadduwm vr6, vr22, vr30");
+    assert_asm!(0x10D6F080, "vadduwm v6, v22, v30");
 }
 
 #[test]
 fn test_vec_vadduws() {
-    assert_asm!(0x1109B280, "vadduws vr8, vr9, vr22");
+    assert_asm!(0x1109B280, "vadduws v8, v9, v22");
 }
 
 #[test]
 fn test_vec_vand() {
-    assert_asm!(0x1156BC04, "vand vr10, vr22, vr23");
+    assert_asm!(0x1156BC04, "vand v10, v22, v23");
 }
 
 #[test]
 fn test_vec_vandc() {
-    assert_asm!(0x10F4F444, "vandc vr7, vr20, vr30");
+    assert_asm!(0x10F4F444, "vandc v7, v20, v30");
 }
 
 #[test]
 fn test_vec_vavgsb() {
-    assert_asm!(0x10BC1D02, "vavgsb vr5, vr28, vr3");
+    assert_asm!(0x10BC1D02, "vavgsb v5, v28, v3");
 }
 
 #[test]
 fn test_vec_vavgsh() {
-    assert_asm!(0x106DBD42, "vavgsh vr3, vr13, vr23");
+    assert_asm!(0x106DBD42, "vavgsh v3, v13, v23");
 }
 
 #[test]
 fn test_vec_vavgsw() {
-    assert_asm!(0x112CAD82, "vavgsw vr9, vr12, vr21");
+    assert_asm!(0x112CAD82, "vavgsw v9, v12, v21");
 }
 
 #[test]
 fn test_vec_vavgub() {
-    assert_asm!(0x100FF402, "vavgub vr0, vr15, vr30");
+    assert_asm!(0x100FF402, "vavgub v0, v15, v30");
 }
 
 #[test]
 fn test_vec_vavguh() {
-    assert_asm!(0x108EC442, "vavguh vr4, vr14, vr24");
+    assert_asm!(0x108EC442, "vavguh v4, v14, v24");
 }
 
 #[test]
 fn test_vec_vavguw() {
-    assert_asm!(0x10674482, "vavguw vr3, vr7, vr8");
+    assert_asm!(0x10674482, "vavguw v3, v7, v8");
 }
 
 #[test]
 fn test_vec_vcfsx() {
-    assert_asm!(0x101D534A, "vcfsx vr0, vr10, 0x1d");
+    assert_asm!(0x101D534A, "vcfsx v0, v10, 0x1d");
 }
 
 #[test]
 fn test_vec_vcfux() {
-    assert_asm!(0x10B03B0A, "vcfux vr5, vr7, 0x10");
+    assert_asm!(0x10B03B0A, "vcfux v5, v7, 0x10");
 }
 
 #[test]
 fn test_vec_vcmpbfp() {
-    assert_asm!(0x106963C6, "vcmpbfp vr3, vr9, vr12");
-    assert_asm!(0x10E84FC6, "vcmpbfp. vr7, vr8, vr9");
+    assert_asm!(0x106963C6, "vcmpbfp v3, v9, v12");
+    assert_asm!(0x10E84FC6, "vcmpbfp. v7, v8, v9");
 }
 
 #[test]
 fn test_vec_vcmpeqfp() {
-    assert_asm!(0x108640C6, "vcmpeqfp vr4, vr6, vr8");
-    assert_asm!(0x10A304C6, "vcmpeqfp. vr5, vr3, vr0");
+    assert_asm!(0x108640C6, "vcmpeqfp v4, v6, v8");
+    assert_asm!(0x10A304C6, "vcmpeqfp. v5, v3, v0");
 }
 
 #[test]
 fn test_vec_vcmpequb() {
-    assert_asm!(0x1011D806, "vcmpequb vr0, vr17, vr27");
-    assert_asm!(0x10649C06, "vcmpequb. vr3, vr4, vr19");
+    assert_asm!(0x1011D806, "vcmpequb v0, v17, v27");
+    assert_asm!(0x10649C06, "vcmpequb. v3, v4, v19");
 }
 
 #[test]
 fn test_vec_vcmpequh() {
-    assert_asm!(0x10A86046, "vcmpequh vr5, vr8, vr12");
-    assert_asm!(0x10E60446, "vcmpequh. vr7, vr6, vr0");
+    assert_asm!(0x10A86046, "vcmpequh v5, v8, v12");
+    assert_asm!(0x10E60446, "vcmpequh. v7, v6, v0");
 }
 
 #[test]
 fn test_vec_vcmpequw() {
-    assert_asm!(0x10664086, "vcmpequw vr3, vr6, vr8");
-    assert_asm!(0x10A85486, "vcmpequw. vr5, vr8, vr10");
+    assert_asm!(0x10664086, "vcmpequw v3, v6, v8");
+    assert_asm!(0x10A85486, "vcmpequw. v5, v8, v10");
 }
 
 #[test]
 fn test_vec_vcmpgefp() {
-    assert_asm!(0x100329C6, "vcmpgefp vr0, vr3, vr5");
-    assert_asm!(0x108545C6, "vcmpgefp. vr4, vr5, vr8");
+    assert_asm!(0x100329C6, "vcmpgefp v0, v3, v5");
+    assert_asm!(0x108545C6, "vcmpgefp. v4, v5, v8");
 }
 
 #[test]
 fn test_vec_vcmpgtfp() {
-    assert_asm!(0x10A0CAC6, "vcmpgtfp vr5, vr0, vr25");
-    assert_asm!(0x10E3A6C6, "vcmpgtfp. vr7, vr3, vr20");
+    assert_asm!(0x10A0CAC6, "vcmpgtfp v5, v0, v25");
+    assert_asm!(0x10E3A6C6, "vcmpgtfp. v7, v3, v20");
 }
 
 #[test]
 fn test_vec_vcmpgtsb() {
-    assert_asm!(0x10602306, "vcmpgtsb vr3, vr0, vr4");
-    assert_asm!(0x10E88706, "vcmpgtsb. vr7, vr8, vr16");
+    assert_asm!(0x10602306, "vcmpgtsb v3, v0, v4");
+    assert_asm!(0x10E88706, "vcmpgtsb. v7, v8, v16");
 }
 
 #[test]
 fn test_vec_vcmpgtsh() {
-    assert_asm!(0x10A69B46, "vcmpgtsh vr5, vr6, vr19");
-    assert_asm!(0x1192C746, "vcmpgtsh. vr12, vr18, vr24");
+    assert_asm!(0x10A69B46, "vcmpgtsh v5, v6, v19");
+    assert_asm!(0x1192C746, "vcmpgtsh. v12, v18, v24");
 }
 
 #[test]
 fn test_vec_vcmpgtsw() {
-    assert_asm!(0x1140F386, "vcmpgtsw vr10, vr0, vr30");
-    assert_asm!(0x1297DF86, "vcmpgtsw. vr20, vr23, vr27");
+    assert_asm!(0x1140F386, "vcmpgtsw v10, v0, v30");
+    assert_asm!(0x1297DF86, "vcmpgtsw. v20, v23, v27");
 }
 
 #[test]
 fn test_vec_vcmpgtub() {
-    assert_asm!(0x10A88206, "vcmpgtub vr5, vr8, vr16");
-    assert_asm!(0x13CAA606, "vcmpgtub. vr30, vr10, vr20");
+    assert_asm!(0x10A88206, "vcmpgtub v5, v8, v16");
+    assert_asm!(0x13CAA606, "vcmpgtub. v30, v10, v20");
 }
 
 #[test]
 fn test_vec_vcmpgtuh() {
-    assert_asm!(0x101BFA46, "vcmpgtuh vr0, vr27, vr31");
-    assert_asm!(0x10853646, "vcmpgtuh. vr4, vr5, vr6");
+    assert_asm!(0x101BFA46, "vcmpgtuh v0, v27, v31");
+    assert_asm!(0x10853646, "vcmpgtuh. v4, v5, v6");
 }
 
 #[test]
 fn test_vec_vcmpgtuw() {
-    assert_asm!(0x1070D286, "vcmpgtuw vr3, vr16, vr26");
-    assert_asm!(0x10FAFE86, "vcmpgtuw. vr7, vr26, vr31");
+    assert_asm!(0x1070D286, "vcmpgtuw v3, v16, v26");
+    assert_asm!(0x10FAFE86, "vcmpgtuw. v7, v26, v31");
 }
 
 #[test]
 fn test_vec_vctsxs() {
-    assert_asm!(0x10743BCA, "vctsxs vr3, vr7, 0x14");
+    assert_asm!(0x10743BCA, "vctsxs v3, v7, 0x14");
 }
 
 #[test]
 fn test_vec_vctuxs() {
-    assert_asm!(0x10AB638A, "vctuxs vr5, vr12, 0xb");
+    assert_asm!(0x10AB638A, "vctuxs v5, v12, 0xb");
 }
 
 #[test]
 fn test_vec_vexptefp() {
-    assert_asm!(0x10E0518A, "vexptefp vr7, vr10");
+    assert_asm!(0x10E0518A, "vexptefp v7, v10");
 }
 
 #[test]
 fn test_vec_vlogefp() {
-    assert_asm!(0x100031CA, "vlogefp vr0, vr6");
+    assert_asm!(0x100031CA, "vlogefp v0, v6");
 }
 
 #[test]
 fn test_vec_vmaddfp() {
-    assert_asm!(0x1003396E, "vmaddfp vr0, vr3, vr5, vr7");
+    assert_asm!(0x1003396E, "vmaddfp v0, v3, v5, v7");
 }
 
 #[test]
 fn test_vec_vmaxfp() {
-    assert_asm!(0x10C84C0A, "vmaxfp vr6, vr8, vr9");
+    assert_asm!(0x10C84C0A, "vmaxfp v6, v8, v9");
 }
 
 #[test]
 fn test_vec_vmaxsb() {
-    assert_asm!(0x100AB102, "vmaxsb vr0, vr10, vr22");
+    assert_asm!(0x100AB102, "vmaxsb v0, v10, v22");
 }
 
 #[test]
 fn test_vec_vmaxsh() {
-    assert_asm!(0x1298E142, "vmaxsh vr20, vr24, vr28");
+    assert_asm!(0x1298E142, "vmaxsh v20, v24, v28");
 }
 
 #[test]
 fn test_vec_vmaxsw() {
-    assert_asm!(0x13DF6182, "vmaxsw vr30, vr31, vr12");
+    assert_asm!(0x13DF6182, "vmaxsw v30, v31, v12");
 }
 
 #[test]
 fn test_vec_vmaxub() {
-    assert_asm!(0x1198F002, "vmaxub vr12, vr24, vr30");
+    assert_asm!(0x1198F002, "vmaxub v12, v24, v30");
 }
 
 #[test]
 fn test_vec_vmaxuh() {
-    assert_asm!(0x1236D842, "vmaxuh vr17, vr22, vr27");
+    assert_asm!(0x1236D842, "vmaxuh v17, v22, v27");
 }
 
 #[test]
 fn test_vec_vmaxuw() {
-    assert_asm!(0x114CC082, "vmaxuw vr10, vr12, vr24");
+    assert_asm!(0x114CC082, "vmaxuw v10, v12, v24");
 }
 
 #[test]
 fn test_vec_vmhaddshs() {
-    assert_asm!(0x10A63A20, "vmhaddshs vr5, vr6, vr7, vr8");
+    assert_asm!(0x10A63A20, "vmhaddshs v5, v6, v7, v8");
 }
 
 #[test]
 fn test_vec_vmhraddshs() {
-    assert_asm!(0x112A63A1, "vmhraddshs vr9, vr10, vr12, vr14");
+    assert_asm!(0x112A63A1, "vmhraddshs v9, v10, v12, v14");
 }
 
 #[test]
 fn test_vec_vminfp() {
-    assert_asm!(0x106AAC4A, "vminfp vr3, vr10, vr21");
+    assert_asm!(0x106AAC4A, "vminfp v3, v10, v21");
 }
 
 #[test]
 fn test_vec_vminsb() {
-    assert_asm!(0x10643B02, "vminsb vr3, vr4, vr7");
+    assert_asm!(0x10643B02, "vminsb v3, v4, v7");
 }
 
 #[test]
 fn test_vec_vminsh() {
-    assert_asm!(0x10E9B342, "vminsh vr7, vr9, vr22");
+    assert_asm!(0x10E9B342, "vminsh v7, v9, v22");
 }
 
 #[test]
 fn test_vec_vminsw() {
-    assert_asm!(0x118F9382, "vminsw vr12, vr15, vr18");
+    assert_asm!(0x118F9382, "vminsw v12, v15, v18");
 }
 
 #[test]
 fn test_vec_vminub() {
-    assert_asm!(0x108ED202, "vminub vr4, vr14, vr26");
+    assert_asm!(0x108ED202, "vminub v4, v14, v26");
 }
 
 #[test]
 fn test_vec_vminuh() {
-    assert_asm!(0x11F19A42, "vminuh vr15, vr17, vr19");
+    assert_asm!(0x11F19A42, "vminuh v15, v17, v19");
 }
 
 #[test]
 fn test_vec_vminuw() {
-    assert_asm!(0x1254F282, "vminuw vr18, vr20, vr30");
+    assert_asm!(0x1254F282, "vminuw v18, v20, v30");
 }
 
 #[test]
 fn test_vec_vmladduhm() {
-    assert_asm!(0x10608762, "vmladduhm vr3, vr0, vr16, vr29");
+    assert_asm!(0x10608762, "vmladduhm v3, v0, v16, v29");
 }
 
 #[test]
 fn test_vec_vmrghb() {
-    assert_asm!(0x10F4A80C, "vmrghb vr7, vr20, vr21");
+    assert_asm!(0x10F4A80C, "vmrghb v7, v20, v21");
 }
 
 #[test]
 fn test_vec_vmrghh() {
-    assert_asm!(0x110AC84C, "vmrghh vr8, vr10, vr25");
+    assert_asm!(0x110AC84C, "vmrghh v8, v10, v25");
 }
 
 #[test]
 fn test_vec_vmrghw() {
-    assert_asm!(0x1198E08C, "vmrghw vr12, vr24, vr28");
+    assert_asm!(0x1198E08C, "vmrghw v12, v24, v28");
 }
 
 #[test]
 fn test_vec_vmrglb() {
-    assert_asm!(0x1299F10C, "vmrglb vr20, vr25, vr30");
+    assert_asm!(0x1299F10C, "vmrglb v20, v25, v30");
 }
 
 #[test]
 fn test_vec_vmrglh() {
-    assert_asm!(0x131CF94C, "vmrglh vr24, vr28, vr31");
+    assert_asm!(0x131CF94C, "vmrglh v24, v28, v31");
 }
 
 #[test]
 fn test_vec_vmrglw() {
-    assert_asm!(0x13DF018C, "vmrglw vr30, vr31, vr0");
+    assert_asm!(0x13DF018C, "vmrglw v30, v31, v0");
 }
 
 #[test]
 fn test_vec_vmsummbm() {
-    assert_asm!(0x10044325, "vmsummbm vr0, vr4, vr8, vr12");
+    assert_asm!(0x10044325, "vmsummbm v0, v4, v8, v12");
 }
 
 #[test]
 fn test_vec_vmsumshm() {
-    assert_asm!(0x1114DFE8, "vmsumshm vr8, vr20, vr27, vr31");
+    assert_asm!(0x1114DFE8, "vmsumshm v8, v20, v27, v31");
 }
 
 #[test]
 fn test_vec_vmsumshs() {
-    assert_asm!(0x1150ADE9, "vmsumshs vr10, vr16, vr21, vr23");
+    assert_asm!(0x1150ADE9, "vmsumshs v10, v16, v21, v23");
 }
 
 #[test]
 fn test_vec_vmsumubm() {
-    assert_asm!(0x1198D7A4, "vmsumubm vr12, vr24, vr26, vr30");
+    assert_asm!(0x1198D7A4, "vmsumubm v12, v24, v26, v30");
 }
 
 #[test]
 fn test_vec_vmsumuhm() {
-    assert_asm!(0x13C503E6, "vmsumuhm vr30, vr5, vr0, vr15");
+    assert_asm!(0x13C503E6, "vmsumuhm v30, v5, v0, v15");
 }
 
 #[test]
 fn test_vec_vmsumuhs() {
-    assert_asm!(0x10032167, "vmsumuhs vr0, vr3, vr4, vr5");
+    assert_asm!(0x10032167, "vmsumuhs v0, v3, v4, v5");
 }
 
 #[test]
 fn test_vec_vmulesb() {
-    assert_asm!(0x110EC308, "vmulesb vr8, vr14, vr24");
+    assert_asm!(0x110EC308, "vmulesb v8, v14, v24");
 }
 
 #[test]
 fn test_vec_vmulesh() {
-    assert_asm!(0x10602B48, "vmulesh vr3, vr0, vr5");
+    assert_asm!(0x10602B48, "vmulesh v3, v0, v5");
 }
 
 #[test]
 fn test_vec_vmuleub() {
-    assert_asm!(0x10076208, "vmuleub vr0, vr7, vr12");
+    assert_asm!(0x10076208, "vmuleub v0, v7, v12");
 }
 
 #[test]
 fn test_vec_vmuleuh() {
-    assert_asm!(0x1200FA48, "vmuleuh vr16, vr0, vr31");
+    assert_asm!(0x1200FA48, "vmuleuh v16, v0, v31");
 }
 
 #[test]
 fn test_vec_vmulosb() {
-    assert_asm!(0x11E01908, "vmulosb vr15, vr0, vr3");
+    assert_asm!(0x11E01908, "vmulosb v15, v0, v3");
 }
 
 #[test]
 fn test_vec_vmulosh() {
-    assert_asm!(0x10685148, "vmulosh vr3, vr8, vr10");
+    assert_asm!(0x10685148, "vmulosh v3, v8, v10");
 }
 
 #[test]
 fn test_vec_vmuloub() {
-    assert_asm!(0x10854008, "vmuloub vr4, vr5, vr8");
+    assert_asm!(0x10854008, "vmuloub v4, v5, v8");
 }
 
 #[test]
 fn test_vec_vmulouh() {
-    assert_asm!(0x10A70048, "vmulouh vr5, vr7, vr0");
+    assert_asm!(0x10A70048, "vmulouh v5, v7, v0");
 }
 
 #[test]
 fn test_vec_vnmsubfp() {
-    assert_asm!(0x1060F42F, "vnmsubfp vr3, vr0, vr16, vr30");
+    assert_asm!(0x1060F42F, "vnmsubfp v3, v0, v16, v30");
 }
 
 #[test]
 fn test_vec_vnor() {
-    assert_asm!(0x10605504, "vnor vr3, vr0, vr10");
-    assert_asm!(0x10884504, "vnot vr4, vr8");
+    assert_asm!(0x10605504, "vnor v3, v0, v10");
+    assert_asm!(0x10884504, "vnot v4, v8");
 }
 
 #[test]
 fn test_vec_vor() {
-    assert_asm!(0x100D7C84, "vor vr0, vr13, vr15");
-    assert_asm!(0x1077BC84, "vmr vr3, vr23");
+    assert_asm!(0x100D7C84, "vor v0, v13, v15");
+    assert_asm!(0x1077BC84, "vmr v3, v23");
 }
 
 #[test]
 fn test_vec_vperm() {
-    assert_asm!(0x10a5302b, "vperm vr5, vr5, vr6, vr0");
+    assert_asm!(0x10a5302b, "vperm v5, v5, v6, v0");
 }
 
 #[test]
 fn test_vec_vpkpx() {
-    assert_asm!(0x10AFE30E, "vpkpx vr5, vr15, vr28");
+    assert_asm!(0x10AFE30E, "vpkpx v5, v15, v28");
 }
 
 #[test]
 fn test_vec_vpkshss() {
-    assert_asm!(0x1006498E, "vpkshss vr0, vr6, vr9");
+    assert_asm!(0x1006498E, "vpkshss v0, v6, v9");
 }
 
 #[test]
 fn test_vec_vpkshus() {
-    assert_asm!(0x1220990E, "vpkshus vr17, vr0, vr19");
+    assert_asm!(0x1220990E, "vpkshus v17, v0, v19");
 }
 
 #[test]
 fn test_vec_vpkswss() {
-    assert_asm!(0x1253A1CE, "vpkswss vr18, vr19, vr20");
+    assert_asm!(0x1253A1CE, "vpkswss v18, v19, v20");
 }
 
 #[test]
 fn test_vec_vpkswus() {
-    assert_asm!(0x128AF14E, "vpkswus vr20, vr10, vr30");
+    assert_asm!(0x128AF14E, "vpkswus v20, v10, v30");
 }
 
 #[test]
 fn test_vec_vpkuhum() {
-    assert_asm!(0x10BBA00E, "vpkuhum vr5, vr27, vr20");
+    assert_asm!(0x10BBA00E, "vpkuhum v5, v27, v20");
 }
 
 #[test]
 fn test_vec_vpkuhus() {
-    assert_asm!(0x11AE788E, "vpkuhus vr13, vr14, vr15");
+    assert_asm!(0x11AE788E, "vpkuhus v13, v14, v15");
 }
 
 #[test]
 fn test_vec_vpkuwum() {
-    assert_asm!(0x114B604E, "vpkuwum vr10, vr11, vr12");
+    assert_asm!(0x114B604E, "vpkuwum v10, v11, v12");
 }
 
 #[test]
 fn test_vec_vpkuwus() {
-    assert_asm!(0x1176F8CE, "vpkuwus vr11, vr22, vr31");
+    assert_asm!(0x1176F8CE, "vpkuwus v11, v22, v31");
 }
 
 #[test]
 fn test_vec_vrefp() {
-    assert_asm!(0x1180C10A, "vrefp vr12, vr24");
+    assert_asm!(0x1180C10A, "vrefp v12, v24");
 }
 
 #[test]
 fn test_vec_vrfim() {
-    assert_asm!(0x1240F2CA, "vrfim vr18, vr30");
+    assert_asm!(0x1240F2CA, "vrfim v18, v30");
 }
 
 #[test]
 fn test_vec_vrfin() {
-    assert_asm!(0x1140620A, "vrfin vr10, vr12");
+    assert_asm!(0x1140620A, "vrfin v10, v12");
 }
 
 #[test]
 fn test_vec_vrfip() {
-    assert_asm!(0x10E08A8A, "vrfip vr7, vr17");
+    assert_asm!(0x10E08A8A, "vrfip v7, v17");
 }
 
 #[test]
 fn test_vec_vrfiz() {
-    assert_asm!(0x1000A24A, "vrfiz vr0, vr20");
+    assert_asm!(0x1000A24A, "vrfiz v0, v20");
 }
 
 #[test]
 fn test_vec_vrlb() {
-    assert_asm!(0x10EF8804, "vrlb vr7, vr15, vr17");
+    assert_asm!(0x10EF8804, "vrlb v7, v15, v17");
 }
 
 #[test]
 fn test_vec_vrlh() {
-    assert_asm!(0x12129844, "vrlh vr16, vr18, vr19");
+    assert_asm!(0x12129844, "vrlh v16, v18, v19");
 }
 
 #[test]
 fn test_vec_vrlw() {
-    assert_asm!(0x11540084, "vrlw vr10, vr20, vr0");
+    assert_asm!(0x11540084, "vrlw v10, v20, v0");
 }
 
 #[test]
 fn test_vec_vrsqrtefp() {
-    assert_asm!(0x1060794A, "vrsqrtefp vr3, vr15");
+    assert_asm!(0x1060794A, "vrsqrtefp v3, v15");
 }
 
 #[test]
 fn test_vec_vsel() {
-    assert_asm!(0x100329AA, "vsel vr0, vr3, vr5, vr6");
+    assert_asm!(0x100329AA, "vsel v0, v3, v5, v6");
 }
 
 #[test]
 fn test_vec_vsl() {
-    assert_asm!(0x108CC1C4, "vsl vr4, vr12, vr24");
+    assert_asm!(0x108CC1C4, "vsl v4, v12, v24");
 }
 
 #[test]
 fn test_vec_vslb() {
-    assert_asm!(0x114E9104, "vslb vr10, vr14, vr18");
+    assert_asm!(0x114E9104, "vslb v10, v14, v18");
 }
 
 #[test]
 fn test_vec_vsldoi() {
-    assert_asm!(0x10601B6C, "vsldoi vr3, vr0, vr3, 13");
+    assert_asm!(0x10601B6C, "vsldoi v3, v0, v3, 13");
 }
 
 #[test]
 fn test_vec_vslh() {
-    assert_asm!(0x10AFC144, "vslh vr5, vr15, vr24");
+    assert_asm!(0x10AFC144, "vslh v5, v15, v24");
 }
 
 #[test]
 fn test_vec_vslo() {
-    assert_asm!(0x10F1DC0C, "vslo vr7, vr17, vr27");
+    assert_asm!(0x10F1DC0C, "vslo v7, v17, v27");
 }
 
 #[test]
 fn test_vec_vslw() {
-    assert_asm!(0x11128184, "vslw vr8, vr18, vr16");
+    assert_asm!(0x11128184, "vslw v8, v18, v16");
 }
 
 #[test]
 fn test_vec_vspltb() {
-    assert_asm!(0x115C620C, "vspltb vr10, vr12, 0x1c");
+    assert_asm!(0x115C620C, "vspltb v10, v12, 0x1c");
 }
 
 #[test]
 fn test_vec_vsplth() {
-    assert_asm!(0x11947A4C, "vsplth vr12, vr15, 0x14");
+    assert_asm!(0x11947A4C, "vsplth v12, v15, 0x14");
 }
 
 #[test]
 fn test_vec_vspltisb() {
-    assert_asm!(0x1076030C, "vspltisb vr3, -0xa");
+    assert_asm!(0x1076030C, "vspltisb v3, -0xa");
 }
 
 #[test]
 fn test_vec_vspltish() {
-    assert_asm!(0x11CE034C, "vspltish vr14, 0xe");
+    assert_asm!(0x11CE034C, "vspltish v14, 0xe");
 }
 
 #[test]
 fn test_vec_vspltisw() {
-    assert_asm!(0x124C038C, "vspltisw vr18, 0xc");
+    assert_asm!(0x124C038C, "vspltisw v18, 0xc");
 }
 
 #[test]
 fn test_vec_vspltw() {
-    assert_asm!(0x1018528C, "vspltw vr0, vr10, 0x18");
+    assert_asm!(0x1018528C, "vspltw v0, v10, 0x18");
 }
 
 #[test]
 fn test_vec_vsr() {
-    assert_asm!(0x116C6AC4, "vsr vr11, vr12, vr13");
+    assert_asm!(0x116C6AC4, "vsr v11, v12, v13");
 }
 
 #[test]
 fn test_vec_vsrab() {
-    assert_asm!(0x11D09304, "vsrab vr14, vr16, vr18");
+    assert_asm!(0x11D09304, "vsrab v14, v16, v18");
 }
 
 #[test]
 fn test_vec_vsrah() {
-    assert_asm!(0x10E8C344, "vsrah vr7, vr8, vr24");
+    assert_asm!(0x10E8C344, "vsrah v7, v8, v24");
 }
 
 #[test]
 fn test_vec_vsraw() {
-    assert_asm!(0x112CAB84, "vsraw vr9, vr12, vr21");
+    assert_asm!(0x112CAB84, "vsraw v9, v12, v21");
 }
 
 #[test]
 fn test_vec_vsrb() {
-    assert_asm!(0x1112D204, "vsrb vr8, vr18, vr26");
+    assert_asm!(0x1112D204, "vsrb v8, v18, v26");
 }
 
 #[test]
 fn test_vec_vsrh() {
-    assert_asm!(0x114C8244, "vsrh vr10, vr12, vr16");
+    assert_asm!(0x114C8244, "vsrh v10, v12, v16");
 }
 
 #[test]
 fn test_vec_vsro() {
-    assert_asm!(0x118F9C4C, "vsro vr12, vr15, vr19");
+    assert_asm!(0x118F9C4C, "vsro v12, v15, v19");
 }
 
 #[test]
 fn test_vec_vsrw() {
-    assert_asm!(0x100EA284, "vsrw vr0, vr14, vr20");
+    assert_asm!(0x100EA284, "vsrw v0, v14, v20");
 }
 
 #[test]
 fn test_vec_vsubcuw() {
-    assert_asm!(0x10AF8580, "vsubcuw vr5, vr15, vr16");
+    assert_asm!(0x10AF8580, "vsubcuw v5, v15, v16");
 }
 
 #[test]
 fn test_vec_vsubfp() {
-    assert_asm!(0x1080584A, "vsubfp vr4, vr0, vr11");
+    assert_asm!(0x1080584A, "vsubfp v4, v0, v11");
 }
 
 #[test]
 fn test_vec_vsubsbs() {
-    assert_asm!(0x10D2BF00, "vsubsbs vr6, vr18, vr23");
+    assert_asm!(0x10D2BF00, "vsubsbs v6, v18, v23");
 }
 
 #[test]
 fn test_vec_vsubshs() {
-    assert_asm!(0x10F16740, "vsubshs vr7, vr17, vr12");
+    assert_asm!(0x10F16740, "vsubshs v7, v17, v12");
 }
 
 #[test]
 fn test_vec_vsubsws() {
-    assert_asm!(0x118D5780, "vsubsws vr12, vr13, vr10");
+    assert_asm!(0x118D5780, "vsubsws v12, v13, v10");
 }
 
 #[test]
 fn test_vec_vsububm() {
-    assert_asm!(0x11402C00, "vsububm vr10, vr0, vr5");
+    assert_asm!(0x11402C00, "vsububm v10, v0, v5");
 }
 
 #[test]
 fn test_vec_vsububs() {
-    assert_asm!(0x10033600, "vsububs vr0, vr3, vr6");
+    assert_asm!(0x10033600, "vsububs v0, v3, v6");
 }
 
 #[test]
 fn test_vec_vsubuhm() {
-    assert_asm!(0x10EB6C40, "vsubuhm vr7, vr11, vr13");
+    assert_asm!(0x10EB6C40, "vsubuhm v7, v11, v13");
 }
 
 #[test]
 fn test_vec_vsubuhs() {
-    assert_asm!(0x110A6640, "vsubuhs vr8, vr10, vr12");
+    assert_asm!(0x110A6640, "vsubuhs v8, v10, v12");
 }
 
 #[test]
 fn test_vec_vsubuwm() {
-    assert_asm!(0x112BDC80, "vsubuwm vr9, vr11, vr27");
+    assert_asm!(0x112BDC80, "vsubuwm v9, v11, v27");
 }
 
 #[test]
 fn test_vec_vsubuws() {
-    assert_asm!(0x1149AE80, "vsubuws vr10, vr9, vr21");
+    assert_asm!(0x1149AE80, "vsubuws v10, v9, v21");
 }
 
 #[test]
 fn test_vec_vsumsws() {
-    assert_asm!(0x116C6F88, "vsumsws vr11, vr12, vr13");
+    assert_asm!(0x116C6F88, "vsumsws v11, v12, v13");
 }
 
 #[test]
 fn test_vec_vsum2sws() {
-    assert_asm!(0x11909688, "vsum2sws vr12, vr16, vr18");
+    assert_asm!(0x11909688, "vsum2sws v12, v16, v18");
 }
 
 #[test]
 fn test_vec_vsum4sbs() {
-    assert_asm!(0x11B19708, "vsum4sbs vr13, vr17, vr18");
+    assert_asm!(0x11B19708, "vsum4sbs v13, v17, v18");
 }
 
 #[test]
 fn test_vec_vsum4shs() {
-    assert_asm!(0x1296C648, "vsum4shs vr20, vr22, vr24");
+    assert_asm!(0x1296C648, "vsum4shs v20, v22, v24");
 }
 
 #[test]
 fn test_vec_vsum4ubs() {
-    assert_asm!(0x12F8CE08, "vsum4ubs vr23, vr24, vr25");
+    assert_asm!(0x12F8CE08, "vsum4ubs v23, v24, v25");
 }
 
 #[test]
 fn test_vec_vupkhpx() {
-    assert_asm!(0x10A0434E, "vupkhpx vr5, vr8");
+    assert_asm!(0x10A0434E, "vupkhpx v5, v8");
 }
 
 #[test]
 fn test_vec_vupkhsb() {
-    assert_asm!(0x10001A0E, "vupkhsb vr0, vr3");
+    assert_asm!(0x10001A0E, "vupkhsb v0, v3");
 }
 
 #[test]
 fn test_vec_vupkhsh() {
-    assert_asm!(0x11806A4E, "vupkhsh vr12, vr13");
+    assert_asm!(0x11806A4E, "vupkhsh v12, v13");
 }
 
 #[test]
 fn test_vec_vupklpx() {
-    assert_asm!(0x108083CE, "vupklpx vr4, vr16");
+    assert_asm!(0x108083CE, "vupklpx v4, v16");
 }
 
 #[test]
 fn test_vec_vupklsb() {
-    assert_asm!(0x11407A8E, "vupklsb vr10, vr15");
+    assert_asm!(0x11407A8E, "vupklsb v10, v15");
 }
 
 #[test]
 fn test_vec_vupklsh() {
-    assert_asm!(0x1180C2CE, "vupklsh vr12, vr24");
+    assert_asm!(0x1180C2CE, "vupklsh v12, v24");
 }
 
 #[test]
 fn test_vec_vxor() {
-    assert_asm!(0x10654CC4, "vxor vr3, vr5, vr9");
+    assert_asm!(0x10654CC4, "vxor v3, v5, v9");
 }

disasm/tests/test_vmx.rs

@@ -1,4 +1,4 @@
-use ppc750cl::{Argument, Ins, InsIter, Opcode, GPR};
+use ppc750cl::Ins;
 
 macro_rules! assert_asm {
     ($ins:ident, $disasm:literal) => {{
@@ -10,392 +10,392 @@ macro_rules! assert_asm {
     }};
 }
 
-macro_rules! assert_basic {
-    ($ins:ident, $disasm:literal) => {{
-        assert_eq!(format!("{}", $ins.basic_form()), $disasm)
-    }};
-    ($code:literal, $disasm:literal) => {{
-        let ins = Ins::new($code);
-        assert_eq!(format!("{}", ins.basic()), $disasm)
-    }};
-}
-
 #[test]
 fn test_vmx_lvewx128() {
-    assert_asm!(0x1243388F, "lvewx128 vr114, r3, r7");
+    assert_asm!(0x1243388F, "lvewx128 v114, r3, r7");
 }
 
 #[test]
 fn test_vmx_lvlx128() {
-    assert_asm!(0x1085440F, "lvlx128 vr100, r5, r8");
+    assert_asm!(0x1085440F, "lvlx128 v100, r5, r8");
 }
 
 #[test]
 fn test_vmx_lvrx128() {
-    assert_asm!(0x108EE44B, "lvrx128 vr68, r14, r28");
+    assert_asm!(0x108EE44B, "lvrx128 v68, r14, r28");
 }
 
 #[test]
 fn test_vmx_lvlxl128() {
-    assert_asm!(0x1105FE0B, "lvlxl128 vr72, r5, r31");
+    assert_asm!(0x1105FE0B, "lvlxl128 v72, r5, r31");
 }
 
 #[test]
 fn test_vmx_lvrxl128() {
-    assert_asm!(0x12A01E4B, "lvrxl128 vr85, r0, r3");
+    assert_asm!(0x12A01E4B, "lvrxl128 v85, r0, r3");
 }
 
 #[test]
 fn test_vmx_lvsl128() {
-    assert_asm!(0x138AF00B, "lvsl128 vr92, r10, r30");
+    assert_asm!(0x138AF00B, "lvsl128 v92, r10, r30");
 }
 
 #[test]
 fn test_vmx_lvsr128() {
-    assert_asm!(0x1016C04F, "lvsr128 vr96, r22, r24");
+    assert_asm!(0x1016C04F, "lvsr128 v96, r22, r24");
 }
 
 #[test]
 fn test_vmx_lvx128() {
-    assert_asm!(0x120938CF, "lvx128 vr112, r9, r7");
+    assert_asm!(0x120938CF, "lvx128 v112, r9, r7");
 }
 
 #[test]
 fn test_vmx_lvxl128() {
-    assert_asm!(0x12C322CF, "lvxl128 vr118, r3, r4");
+    assert_asm!(0x12C322CF, "lvxl128 v118, r3, r4");
 }
 
 #[test]
 fn test_vmx_stvewx128() {
-    assert_asm!(0x131BF98F, "stvewx128 vr120, r27, r31");
+    assert_asm!(0x131BF98F, "stvewx128 v120, r27, r31");
 }
 
 #[test]
 fn test_vmx_stvlx128() {
-    assert_asm!(0x12602D0B, "stvlx128 vr83, r0, r5");
+    assert_asm!(0x12602D0B, "stvlx128 v83, r0, r5");
 }
 
 #[test]
 fn test_vmx_stvlxl128() {
-    assert_asm!(0x12C3A70B, "stvlxl128 vr86, r3, r20");
+    assert_asm!(0x12C3A70B, "stvlxl128 v86, r3, r20");
 }
 
 #[test]
 fn test_vmx_stvrx128() {
-    assert_asm!(0x10B8F54B, "stvrx128 vr69, r24, r30");
+    assert_asm!(0x10B8F54B, "stvrx128 v69, r24, r30");
 }
 
 #[test]
 fn test_vmx_stvrxl128() {
-    assert_asm!(0x10C7074B, "stvrxl128 vr70, r7, r0");
+    assert_asm!(0x10C7074B, "stvrxl128 v70, r7, r0");
 }
 
 #[test]
 fn test_vmx_stvx128() {
-    assert_asm!(0x130341C3, "stvx128 vr24, r3, r8");
+    assert_asm!(0x130341C3, "stvx128 v24, r3, r8");
 }
 
 #[test]
 fn test_vmx_stvxl128() {
-    assert_asm!(0x13E553C3, "stvxl128 vr31, r5, r10");
+    assert_asm!(0x13E553C3, "stvxl128 v31, r5, r10");
 }
 
 #[test]
 fn test_vmx_vaddfp128() {
-    assert_asm!(0x151E301B, "vaddfp128 vr72, vr30, vr102");
+    assert_asm!(0x151E301B, "vaddfp128 v72, v30, v102");
 }
 
 #[test]
 fn test_vmx_vand128() {
-    assert_asm!(0x16900E12, "vand128 vr20, vr80, vr65");
+    assert_asm!(0x16900E12, "vand128 v20, v80, v65");
 }
 
 #[test]
 fn test_vmx_vandc128() {
-    assert_asm!(0x15EBFE52, "vandc128 vr15, vr75, vr95");
+    assert_asm!(0x15EBFE52, "vandc128 v15, v75, v95");
 }
 
 #[test]
-fn test_vmx_vcfpsxws128(){
-    assert_asm!(0x1A42D23B, "vcfpsxws128 vr82, vr122, 0x2");
+fn test_vmx_vctsxs128() {
+    assert_asm!(0x1A42D23B, "vctsxs128 v82, v122, 0x2");
 }
 
 #[test]
-fn test_vmx_vcfpuxws128(){
-    assert_asm!(0x1BEACA78, "vcfpuxws128 vr95, vr25, 0xa");
+fn test_vmx_vctuxs128() {
+    assert_asm!(0x1BEACA78, "vctuxs128 v95, v25, 0xa");
 }
 
 #[test]
 fn test_vmx_vcmpbfp128() {
-    assert_asm!(0x1BA5598E, "vcmpbfp128 vr125, vr5, vr75");
-    assert_asm!(0x198D79C2, "vcmpbfp128. vr12, vr13, vr79");
+    assert_asm!(0x1BA5598E, "vcmpbfp128 v125, v5, v75");
+    assert_asm!(0x198D79C2, "vcmpbfp128. v12, v13, v79");
 }
 
 #[test]
 fn test_vmx_vcmpeqfp128() {
-    assert_asm!(0x1800D80B, "vcmpeqfp128 vr64, vr0, vr123");
-    assert_asm!(0x1ACD1C43, "vcmpeqfp128. vr22, vr77, vr99");
+    assert_asm!(0x1800D80B, "vcmpeqfp128 v64, v0, v123");
+    assert_asm!(0x1ACD1C43, "vcmpeqfp128. v22, v77, v99");
 }
 
 #[test]
 fn test_vmx_vcmpequw128() {
-    assert_asm!(0x18D0D60A, "vcmpequw128 vr70, vr80, vr90");
-    assert_asm!(0x18800A40, "vcmpequw128. vr4, vr0, vr1");
+    assert_asm!(0x18D0D60A, "vcmpequw128 v70, v80, v90");
+    assert_asm!(0x18800A40, "vcmpequw128. v4, v0, v1");
 }
 
 #[test]
 fn test_vmx_vcmpgefp128() {
-    assert_asm!(0x1A8A1483, "vcmpgefp128 vr20, vr74, vr98");
-    assert_asm!(0x18EB7CEF, "vcmpgefp128. vr103, vr107, vr111");
+    assert_asm!(0x1A8A1483, "vcmpgefp128 v20, v74, v98");
+    assert_asm!(0x18EB7CEF, "vcmpgefp128. v103, v107, v111");
 }
 
 #[test]
 fn test_vmx_vcmpgtfp128() {
-    assert_asm!(0x1BD48102, "vcmpgtfp128 vr30, vr20, vr80");
-    assert_asm!(0x1B586D68, "vcmpgtfp128. vr90, vr120, vr13");
+    assert_asm!(0x1BD48102, "vcmpgtfp128 v30, v20, v80");
+    assert_asm!(0x1B586D68, "vcmpgtfp128. v90, v120, v13");
 }
 
 #[test]
-fn test_vmx_vcsxwfp128(){
-    assert_asm!(0x18749ABC, "vcsxwfp128 vr99, vr19, -0xc");
+fn test_vmx_vcfsx128() {
+    assert_asm!(0x18749ABC, "vcfsx128 v99, v19, -0xc");
 }
 
 #[test]
-fn test_vmx_vcuxwfp128(){
-    assert_asm!(0x1A6D1AF8, "vcuxwfp128 vr83, vr3, 0xd");
+fn test_vmx_vcfux128() {
+    assert_asm!(0x1A6D1AF8, "vcfux128 v83, v3, 0xd");
 }
 
 #[test]
 fn test_vmx_vexptefp128() {
-    assert_asm!(0x198056B0, "vexptefp128 vr12, vr10");
+    assert_asm!(0x198056B0, "vexptefp128 v12, v10");
 }
 
 #[test]
 fn test_vmx_vlogefp128() {
-    assert_asm!(0x1900FEFB, "vlogefp128 vr72, vr127");
+    assert_asm!(0x1900FEFB, "vlogefp128 v72, v127");
 }
 
 #[test]
 fn test_vmx_vmaddcfp128() {
-    assert_asm!(0x163B1912, "vmaddcfp128 vr17, vr27, vr67");
+    assert_asm!(0x163B1912, "vmaddcfp128 v17, v27, v67");
 }
 
 #[test]
 fn test_vmx_vmaddfp128() {
-    assert_asm!(0x16B3ECFB, "vmaddfp128 vr85, vr115, vr125");
+    assert_asm!(0x16B3ECFB, "vmaddfp128 v85, v115, v125");
 }
 
 #[test]
 fn test_vmx_vmaxfp128() {
-    assert_asm!(0x1B274683, "vmaxfp128 vr25, vr71, vr104");
+    assert_asm!(0x1B274683, "vmaxfp128 v25, v71, v104");
 }
 
 #[test]
 fn test_vmx_vminfp128() {
-    assert_asm!(0x1BE012C0, "vminfp128 vr31, vr0, vr2");
+    assert_asm!(0x1BE012C0, "vminfp128 v31, v0, v2");
 }
 
 #[test]
 fn test_vmx_vmrghw128() {
-    assert_asm!(0x18CA730B, "vmrghw128 vr70, vr10, vr110");
+    assert_asm!(0x18CA730B, "vmrghw128 v70, v10, v110");
 }
 
 #[test]
 fn test_vmx_vmrglw128() {
-    assert_asm!(0x1BD2D743, "vmrglw128 vr30, vr82, vr122");
+    assert_asm!(0x1BD2D743, "vmrglw128 v30, v82, v122");
 }
 
 #[test]
 fn test_vmx_vmsum3fp128() {
-    assert_asm!(0x14FBF993, "vmsum3fp128 vr7, vr27, vr127");
+    assert_asm!(0x14FBF993, "vmsum3fp128 v7, v27, v127");
 }
 
 #[test]
 fn test_vmx_vmsum4fp128() {
-    assert_asm!(0x14A869D0, "vmsum4fp128 vr5, vr8, vr13");
+    assert_asm!(0x14A869D0, "vmsum4fp128 v5, v8, v13");
 }
 
 #[test]
 fn test_vmx_vmulfp128() {
-    assert_asm!(0x1498DCBF, "vmulfp128 vr100, vr120, vr123");
+    assert_asm!(0x1498DCBF, "vmulfp128 v100, v120, v123");
 }
 
 #[test]
 fn test_vmx_vnmsubfp128() {
-    assert_asm!(0x17DBCD53, "vnmsubfp128 vr30, vr91, vr121");
+    assert_asm!(0x17DBCD53, "vnmsubfp128 v30, v91, v121");
 }
 
 #[test]
 fn test_vmx_vnor128() {
-    assert_asm!(0x176A6290, "vnor128 vr27, vr10, vr12");
+    assert_asm!(0x176A6290, "vnor128 v27, v10, v12");
 }
 
 #[test]
 fn test_vmx_vor128() {
-    assert_asm!(0x17EC3ADC, "vor128 vr127, vr12, vr7");
+    assert_asm!(0x17EC3ADC, "vor128 v127, v12, v7");
 }
 
 #[test]
 fn test_vmx_vperm128() {
-    assert_asm!(0x1661158F, "vperm128 vr115, vr65, vr98, vr6");
+    assert_asm!(0x1661158F, "vperm128 v115, v65, v98, v6");
 }
 
 #[test]
 fn test_vmx_vpermwi128() {
-    assert_asm!(0x19C342DE, "vpermwi128 vr110, vr72, 99");
+    assert_asm!(0x19C342DE, "vpermwi128 v110, v72, 99");
 }
 
 #[test]
 fn test_vmx_vpkd3d128() {
-    assert_asm!(0x1935DEDC, "vpkd3d128 vr105, vr27, 5, 1, 3");
+    assert_asm!(0x1935DEDC, "vpkd3d128 v105, v27, 5, 1, 3");
 }
 
 #[test]
 fn test_vmx_vpkshss128() {
-    assert_asm!(0x16C0F62B, "vpkshss128 vr86, vr96, vr126");
+    assert_asm!(0x16C0F62B, "vpkshss128 v86, v96, v126");
 }
 
 #[test]
 fn test_vmx_vpkshus128() {
-    assert_asm!(0x153D6E48, "vpkshus128 vr73, vr93, vr13");
+    assert_asm!(0x153D6E48, "vpkshus128 v73, v93, v13");
 }
 
 #[test]
 fn test_vmx_vpkswss128() {
-    assert_asm!(0x16FE7280, "vpkswss128 vr23, vr30, vr14");
+    assert_asm!(0x16FE7280, "vpkswss128 v23, v30, v14");
 }
 
 #[test]
 fn test_vmx_vpkswus128() {
-    assert_asm!(0x161836C3, "vpkswus128 vr16, vr88, vr102");
+    assert_asm!(0x161836C3, "vpkswus128 v16, v88, v102");
 }
 
 #[test]
 fn test_vmx_vpkuhum128() {
-    assert_asm!(0x14E3BF02, "vpkuhum128 vr7, vr67, vr87");
+    assert_asm!(0x14E3BF02, "vpkuhum128 v7, v67, v87");
 }
 
 #[test]
 fn test_vmx_vpkuhus128() {
-    assert_asm!(0x1600A348, "vpkuhus128 vr80, vr0, vr20");
+    assert_asm!(0x1600A348, "vpkuhus128 v80, v0, v20");
 }
 
 #[test]
 fn test_vmx_vpkuwum128() {
-    assert_asm!(0x16EACB83, "vpkuwum128 vr23, vr10, vr121");
+    assert_asm!(0x16EACB83, "vpkuwum128 v23, v10, v121");
 }
 
 #[test]
 fn test_vmx_vpkuwus128() {
-    assert_asm!(0x17E72FC3, "vpkuwus128 vr31, vr71, vr101");
+    assert_asm!(0x17E72FC3, "vpkuwus128 v31, v71, v101");
 }
 
 #[test]
 fn test_vmx_vrefp128() {
-    assert_asm!(0x1800F638, "vrefp128 vr64, vr30");
+    assert_asm!(0x1800F638, "vrefp128 v64, v30");
 }
 
 #[test]
 fn test_vmx_vrfim128() {
-    assert_asm!(0x18802B30, "vrfim128 vr4, vr5");
+    assert_asm!(0x18802B30, "vrfim128 v4, v5");
 }
 
 #[test]
 fn test_vmx_vrfin128() {
-    assert_asm!(0x1A200B73, "vrfin128 vr17, vr97");
+    assert_asm!(0x1A200B73, "vrfin128 v17, v97");
 }
 
 #[test]
 fn test_vmx_vrfip128() {
-    assert_asm!(0x1B605BB2, "vrfip128 vr27, vr75");
+    assert_asm!(0x1B605BB2, "vrfip128 v27, v75");
 }
 
 #[test]
 fn test_vmx_vrfiz128() {
-    assert_asm!(0x1A8053F0, "vrfiz128 vr20, vr10");
+    assert_asm!(0x1A8053F0, "vrfiz128 v20, v10");
 }
 
 #[test]
 fn test_vmx_vrlimi128() {
-    assert_asm!(0x18796798, "vrlimi128 vr67, vr12, 0x19, 2")
+    assert_asm!(0x18796798, "vrlimi128 v67, v12, 0x19, 2")
 }
 
 #[test]
 fn test_vmx_vrlw128() {
-    assert_asm!(0x1B002050, "vrlw128 vr24, vr0, vr4");
+    assert_asm!(0x1B002050, "vrlw128 v24, v0, v4");
 }
 
 #[test]
 fn test_vmx_vrsqrtefp128() {
-    assert_asm!(0x19800673, "vrsqrtefp128 vr12, vr96");
+    assert_asm!(0x19800673, "vrsqrtefp128 v12, v96");
 }
 
 #[test]
 fn test_vmx_vsel128() {
-    assert_asm!(0x146CDF5A, "vsel128 vr67, vr76, vr91");
+    assert_asm!(0x146CDF5A, "vsel128 v67, v76, v91");
 }
 
 #[test]
 fn test_vmx_vsldoi128() {
-    assert_asm!(0x130BFF30, "vsldoi128 vr24, vr107, vr31, 12");
+    assert_asm!(0x130BFF30, "vsldoi128 v24, v107, v31, 12");
 }
 
 #[test]
 fn test_vmx_vslo128() {
-    assert_asm!(0x14E08B90, "vslo128 vr7, vr0, vr17");
+    assert_asm!(0x14E08B90, "vslo128 v7, v0, v17");
 }
 
 #[test]
 fn test_vmx_vslw128() {
-    assert_asm!(0x1A1AC0D2, "vslw128 vr16, vr26, vr88");
+    assert_asm!(0x1A1AC0D2, "vslw128 v16, v26, v88");
 }
 
 #[test]
 fn test_vmx_vspltisw128() {
-    assert_asm!(0x1B68A772, "vspltisw128 vr27, vr84, 0x8");
+    assert_asm!(0x1B68A772, "vspltisw128 v27, v84, 0x8");
 }
 
 #[test]
 fn test_vmx_vspltw128() {
-    assert_asm!(0x1996EF32, "vspltw128 vr12, vr93, 0x16");
+    assert_asm!(0x1996EF32, "vspltw128 v12, v93, 0x16");
 }
 
 #[test]
 fn test_vmx_vsraw128() {
-    assert_asm!(0x19B71950, "vsraw128 vr13, vr23, vr3");
+    assert_asm!(0x19B71950, "vsraw128 v13, v23, v3");
 }
 
 #[test]
 fn test_vmx_vsro128() {
-    assert_asm!(0x17C3E3D3, "vsro128 vr30, vr3, vr124");
+    assert_asm!(0x17C3E3D3, "vsro128 v30, v3, v124");
 }
 
 #[test]
 fn test_vmx_vsrw128() {
-    assert_asm!(0x1B9271D3, "vsrw128 vr28, vr18, vr110");
+    assert_asm!(0x1B9271D3, "vsrw128 v28, v18, v110");
 }
 
 #[test]
 fn test_vmx_vsubfp128() {
-    assert_asm!(0x17692C50, "vsubfp128 vr27, vr73, vr5");
+    assert_asm!(0x17692C50, "vsubfp128 v27, v73, v5");
 }
 
 #[test]
 fn test_vmx_vupkd3d128() {
-    assert_asm!(0x19FECFF0, "vupkd3d128 vr15, vr25, 0x1e");
+    assert_asm!(0x19FECFF0, "vupkd3d128 v15, v25, 0x1e");
 }
 
 #[test]
 fn test_vmx_vupkhsb128() {
-    assert_asm!(0x1B60FB83, "vupkhsb128 vr27, vr127");
+    assert_asm!(0x1B60FB83, "vupkhsb128 v27, v127");
+}
+
+#[test]
+fn test_vmx_vupkhsh128() {
+    assert_asm!(0x186017a0, "vupkhsh128 v3, v2");
 }
 
 #[test]
 fn test_vmx_vupklsb128() {
-    assert_asm!(0x1A00A3C3, "vupklsb128 vr16, vr116");
+    assert_asm!(0x1A00A3C3, "vupklsb128 v16, v116");
+}
+
+#[test]
+fn test_vmx_vupklsh128() {
+    assert_asm!(0x186017e0, "vupklsh128 v3, v2");
 }
 
 #[test]
 fn test_vmx_vxor128() {
-    assert_asm!(0x17E3EF32, "vxor128 vr31, vr99, vr93");
+    assert_asm!(0x17E3EF32, "vxor128 v31, v99, v93");
 }

fuzz/src/main.rs

@@ -65,7 +65,7 @@ impl MultiFuzzer {
                 last = now;
                 let progress = 100f32 * ((now as f32) / (0x1_0000_0000u64 as f32));
                 let avg = now as f32 / elapsed.as_secs_f32() / this.threads.len() as f32;
-                println!("{}/s\t{:05.2}%\tn=0x{:08x} (avg {}/s)", per_second, progress, now, avg);
+                println!("{per_second}/s\t{progress:05.2}%\tn=0x{now:08x} (avg {avg}/s)");
             }
         });
     }
@@ -104,7 +104,7 @@ impl Fuzzer {
             let mut parsed = ppc750cl::ParsedIns::default();
             for x in range.clone() {
                 ppc750cl::Ins::new(x).parse_simplified(&mut parsed);
-                writeln!(&mut devnull, "{}", parsed).unwrap();
+                writeln!(&mut devnull, "{parsed}").unwrap();
                 if x % (1 << 19) == 0 {
                     counter.store(x, Ordering::Relaxed);
                 }

genisa/src/asm.rs

@@ -94,7 +94,7 @@ pub fn gen_asm(isa: &Isa, max_args: usize) -> Result<TokenStream> {
             pattern |= modifier.mask();
         }
         let name = format!("{}{}", mnemonic.name(), suffix);
-        func_map.entry(name, &format!("(gen_{}, {:#x})", to_ident(&mnemonic.name()), pattern));
+        func_map.entry(name, &format!("(gen_{}, {:#x})", to_ident(mnemonic.name()), pattern));
     }
 
     let func_map = syn::parse_str::<TokenStream>(&func_map.build().to_string())?;
@@ -219,7 +219,7 @@ fn gen_mnemonic(mnemonic: &Mnemonic, isa: &Isa, check_arg_count: bool) -> Result
     };
     let mut args = TokenStream::new();
     for (i, arg) in mnemonic.args.iter().enumerate() {
-        let comment = format!(" {}", arg);
+        let comment = format!(" {arg}");
         let operations = gen_argument(&mnemonic.args, i, isa, mnemonic.replace_assemble.get(arg))?;
         args.extend(quote! {
             #[comment = #comment]

genisa/src/condition.rs

@@ -74,7 +74,7 @@ pub fn parse_conditions<'a>(condition: &'a str, isa: &'a Isa) -> Result<Vec<Cond
         };
         let field = isa
             .find_field(field)
-            .with_context(|| format!("Condition  references unknown field {}", field))?;
+            .with_context(|| format!("Condition references unknown field {field}"))?;
         let value = if let Ok(value) = parse_unsigned(value) {
             ConditionValue::ConstantUnsigned(value)
         } else if let Ok(value) = parse_signed(value) {

genisa/src/disasm.rs

@@ -40,7 +40,6 @@ pub fn gen_disasm(isa: &Isa, max_args: usize) -> Result<TokenStream> {
         entries.push(entry);
     }
     ensure!(sorted_ops.len() == isa.opcodes.len());
-    // ensure!(sorted_ops.len() <= 255);
     let opcode_max = Literal::u16_unsuffixed((sorted_ops.len() - 1) as u16);
 
     // Generate the opcode entries table
@@ -383,12 +382,18 @@ pub fn gen_disasm(isa: &Isa, max_args: usize) -> Result<TokenStream> {
         static BASIC_MNEMONICS: [MnemonicFunction; #opcode_count] = [#basic_functions_ref];
         #[inline]
         pub fn parse_basic(out: &mut ParsedIns, ins: Ins) {
-            BASIC_MNEMONICS.get(ins.op as usize).copied().unwrap_or(mnemonic_illegal)(out, ins)
+            match BASIC_MNEMONICS.get(ins.op as usize) {
+                Some(f) => f(out, ins),
+                None => mnemonic_illegal(out, ins),
+            }
         }
         static SIMPLIFIED_MNEMONICS: [MnemonicFunction; #opcode_count] = [#simplified_functions_ref];
         #[inline]
         pub fn parse_simplified(out: &mut ParsedIns, ins: Ins) {
-            SIMPLIFIED_MNEMONICS.get(ins.op as usize).copied().unwrap_or(mnemonic_illegal)(out, ins)
+            match SIMPLIFIED_MNEMONICS.get(ins.op as usize) {
+                Some(f) => f(out, ins),
+                None => mnemonic_illegal(out, ins),
+            }
         }
 
         type DefsUsesFunction = fn(&mut Arguments, Ins);
@@ -396,12 +401,18 @@ pub fn gen_disasm(isa: &Isa, max_args: usize) -> Result<TokenStream> {
         static DEFS_FUNCTIONS: [DefsUsesFunction; #opcode_count] = [#defs_refs];
         #[inline]
         pub fn parse_defs(out: &mut Arguments, ins: Ins) {
-            DEFS_FUNCTIONS.get(ins.op as usize).copied().unwrap_or(defs_uses_empty)(out, ins)
+            match DEFS_FUNCTIONS.get(ins.op as usize) {
+                Some(f) => f(out, ins),
+                None => defs_uses_empty(out, ins),
+            }
         }
         static USES_FUNCTIONS: [DefsUsesFunction; #opcode_count] = [#uses_refs];
         #[inline]
         pub fn parse_uses(out: &mut Arguments, ins: Ins) {
-            USES_FUNCTIONS.get(ins.op as usize).copied().unwrap_or(defs_uses_empty)(out, ins)
+            match USES_FUNCTIONS.get(ins.op as usize) {
+                Some(f) => f(out, ins),
+                None => defs_uses_empty(out, ins),
+            }
         }
     })
 }
@@ -474,7 +485,7 @@ fn gen_mnemonic(
         }
         let names_len = Literal::usize_unsuffixed(names.len());
         Ok(quote! { {
-            const MODIFIERS: [&str; #names_len] = [#(#names),*];
+            static MODIFIERS: [&str; #names_len] = [#(#names),*];
             ParsedIns { mnemonic: MODIFIERS[#bitset], args: #arguments }
         } })
     }

genisa/src/isa.rs

@@ -397,7 +397,7 @@ pub fn to_variant(key: &str) -> String {
         s.push(match c {
             'a'..='z' => c.to_ascii_uppercase(),
             'A'..='Z' => c,
-            _ => panic!("invalid identifier: {}", key),
+            _ => panic!("invalid identifier: {key}"),
         });
         loop {
             let c = match chars.next() {
@@ -411,7 +411,7 @@ pub fn to_variant(key: &str) -> String {
                     s.push('_');
                     break;
                 }
-                _ => panic!("invalid character in variant: {}", key),
+                _ => panic!("invalid character in variant: {key}"),
             }
         }
     }
@@ -459,7 +459,7 @@ where
     T: std::fmt::LowerHex,
 {
     fn to_tokens(&self, tokens: &mut TokenStream) {
-        let s = format!("{:#x}", self);
+        let s = format!("{self:#x}");
         tokens.extend(TokenStream::from_str(&s).unwrap());
     }
 }
@@ -486,7 +486,7 @@ where
     T: PrimInt + std::fmt::LowerHex,
 {
     fn to_tokens(&self, tokens: &mut TokenStream) {
-        let s = format!("{:#x}", self);
+        let s = format!("{self:#x}");
         tokens.extend(TokenStream::from_str(&s).unwrap());
     }
 }

genisa/src/main.rs

@@ -22,9 +22,7 @@ fn main() -> Result<()> {
     simple_logger::SimpleLogger::new().env().init()?;
 
     let isa = load_isa(Path::new("isa.yaml"))?;
-    // Make sure we can fit the opcodes into a u8
-    // ensure!(isa.opcodes.len() <= 255);
-    log::info!("num opcodes: {}", isa.opcodes.len());
+    log::info!("Opcode count: {}", isa.opcodes.len());
 
     // Sanity check the opcodes and mnemonics
     // Calculate the bitmask for each opcode and compare it to the stored bitmask

isa.yaml

@@ -2528,6 +2528,7 @@ opcodes:
     uses: [ vA, vB ]
 
   - name: vcfsx
+    aliases: [ vcsxwfp ]
     desc: Vector Convert from Signed Fixed-Point Word
     bitmask: 0xfc0007ff
     pattern: 0x1000034a
@@ -2536,6 +2537,7 @@ opcodes:
     uses: [ vB, vuimm ]
 
   - name: vcfux
+    aliases: [ vcuxwfp ]
     desc: Vector Convert from Unsigned Fixed-Point Word
     bitmask: 0xfc0007ff
     pattern: 0x1000030a
@@ -2661,6 +2663,7 @@ opcodes:
     uses: [ vA, vB ]
 
   - name: vctsxs
+    aliases: [ vcfpsxws ]
     desc: Vector Convert to Signed Fixed-Point Word Saturate
     bitmask: 0xfc0007ff
     pattern: 0x100003ca
@@ -2669,6 +2672,7 @@ opcodes:
     uses: [ vB, vuimm ]
 
   - name: vctuxs
+    aliases: [ vcfpuxws ]
     desc: Vector Convert to Unsigned Fixed-Point Word Saturate
     bitmask: 0xfc0007ff
     pattern: 0x1000038a
@@ -3672,16 +3676,18 @@ opcodes:
     defs: [ VDS128 ]
     uses: [ VA128, VB128 ]
 
-  - name: vcfpsxws128
-    desc: Vector128 Convert From Floating-Point to Signed Fixed-Point Word Saturate
+  - name: vctsxs128
+    aliases: [ vcfpsxws128 ]
+    desc: Vector128 Convert to Signed Fixed-Point Word Saturate
     bitmask: 0xfc0007f0
     pattern: 0x18000230
     args: [ VDS128, VB128, vsimm ]
     defs: [ VDS128 ]
     uses: [ VB128 ]
 
-  - name: vcfpuxws128
-    desc: Vector128 Convert From Floating-Point to Unsigned Fixed-Point Word Saturate
+  - name: vctuxs128
+    aliases: [ vcfpuxws128 ]
+    desc: Vector128 Convert to Unsigned Fixed-Point Word Saturate
     bitmask: 0xfc0007f0
     pattern: 0x18000270
     args: [ VDS128, VB128, vuimm ]
@@ -3733,16 +3739,18 @@ opcodes:
     defs: [ VDS128 ]
     uses: [ VA128, VB128 ]
 
-  - name: vcsxwfp128
-    desc: Vector128 Convert From Signed Fixed-Point Word to Floating-Point
+  - name: vcfsx128
+    aliases: [ vcsxwfp128 ]
+    desc: Vector128 Convert From Signed Fixed-Point Word
     bitmask: 0xfc0007f0
     pattern: 0x180002b0
     args: [ VDS128, VB128, vsimm ]
     defs: [ VDS128 ]
     uses: [ VB128 ]
 
-  - name: vcuxwfp128
-    desc: Vector128 Convert From Unsigned Fixed-Point Word to Floating-Point
+  - name: vcfux128
+    aliases: [ vcuxwfp128 ]
+    desc: Vector128 Convert From Unsigned Fixed-Point Word
     bitmask: 0xfc0007f0
     pattern: 0x180002f0
     args: [ VDS128, VB128, vuimm ]
@@ -4109,6 +4117,14 @@ opcodes:
     defs: [ VDS128 ]
     uses: [ VB128 ]
 
+  - name: vupkhsh128
+    desc: Vector128 Unpack High Signed Half Word
+    bitmask: 0xfc1f07f0
+    pattern: 0x180007a0
+    args: [ VDS128, VB128 ]
+    defs: [ VDS128 ]
+    uses: [ VB128 ]
+
   - name: vupklsb128
     desc: Vector128 Unpack Low Signed Byte
     bitmask: 0xfc1f07f0
@@ -4117,6 +4133,14 @@ opcodes:
     defs: [ VDS128 ]
     uses: [ VB128 ]
 
+  - name: vupklsh128
+    desc: Vector128 Unpack Low Signed Half Word
+    bitmask: 0xfc1f07f0
+    pattern: 0x180007e0
+    args: [ VDS128, VB128 ]
+    defs: [ VDS128 ]
+    uses: [ VB128 ]
+
   - name: vxor128
     desc: Vector128 Logical XOR
     bitmask: 0xfc0003d0
@@ -4799,7 +4823,7 @@ mnemonics:
     condition: ds_A == 0
   - name: dssall
     opcode: dss
-    condition: ds_A == 1
+    condition: ds_A == 1 && STRM == 0
   - name: vnot
     opcode: vnor
     args: [ vD, vA ]
@@ -4808,16 +4832,3 @@ mnemonics:
     opcode: vor
     args: [ vD, vA ]
     condition: vB == vA
-
-# missing instructions (there seem to be no documentation on these anywhere)
-# vctsxs128
-# vcfpsxws
-# vctuxs128
-# vcfpuxws
-# vcsxwfp
-# vcfux128
-# vcuxwfp
-# vdot3fp
-# vdot4fp
-# vupkhsh128
-# vupklsh128