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isa: fix `srw` argument order

This commit is contained in:
InusualZ 2022-05-31 19:30:33 -04:00
parent 2364d17751
commit 49673468fc
3 changed files with 3 additions and 2 deletions
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2
disasm/src/generated.rs
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@ -2189,8 +2189,8 @@ impl Ins {
Field::SH(OpaqueU(((self.code >> 11u8) & 0x1f) as _)),
],
Opcode::Srw => vec![
Field::rS(GPR(((self.code >> 21u8) & 0x1f) as _)),
Field::rA(GPR(((self.code >> 16u8) & 0x1f) as _)),
Field::rS(GPR(((self.code >> 21u8) & 0x1f) as _)),
Field::rB(GPR(((self.code >> 11u8) & 0x1f) as _)),
],
Opcode::Stb => vec![

1
disasm/tests/test_disasm.rs
View File

@ -816,6 +816,7 @@ fn test_ins_srawi() {
#[test]
fn test_ins_srw() {
assert_asm!(0x7C001C30, "srw r0, r0, r3");
assert_asm!(0x7C600430, "srw r0, r3, r0");
}
#[test]

2
isa.yaml
View File

@ -1635,7 +1635,7 @@ opcodes:
bitmask: 0xfc0007fe
pattern: 0x7c000430
modifiers: [ Rc ]
args: [ rS, rA, rB ]
args: [ rA, rS, rB ]
defs: [ rA ]
uses: [ rA, rB ]