more tests
This commit is contained in:
Richard Patel
parent
b6ad3f4f2c
commit
8a57bd9eb2
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@ -7,14 +7,17 @@ pub struct FormattedIns(pub Ins);
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impl Display for FormattedIns {
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fn fmt(&self, f: &mut Formatter<'_>) -> std::fmt::Result {
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let simple = self.0.clone().simplified();
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write!(f, "{}{} ", simple.mnemonic, simple.modifiers)?;
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write!(f, "{}{}", simple.mnemonic, simple.modifiers)?;
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let mut writing_offset = false;
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for (i, arg) in simple.args.iter().enumerate() {
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if i > 0 {
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if i == 0 {
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write!(f, " ")?;
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}
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if i > 0 && !writing_offset {
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write!(f, ", ")?;
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}
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if let Argument::Offset(_) = arg {
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write!(f, "(")?;
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if let Argument::Offset(val) = arg {
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write!(f, "{}(", val)?;
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writing_offset = true;
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continue;
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} else {
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@ -1836,7 +1836,6 @@ impl Ins {
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],
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Opcode::PsAbs => vec![
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Field::frD(FPR(((self.code >> 21u8) & 0x1f) as _)),
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Field::frA(FPR(((self.code >> 16u8) & 0x1f) as _)),
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Field::frB(FPR(((self.code >> 11u8) & 0x1f) as _)),
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],
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Opcode::PsAdd => vec![
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@ -2048,12 +2047,12 @@ impl Ins {
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Field::rB(GPR(((self.code >> 11u8) & 0x1f) as _)),
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],
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Opcode::Stfd => vec![
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Field::rS(GPR(((self.code >> 21u8) & 0x1f) as _)),
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Field::frS(FPR(((self.code >> 21u8) & 0x1f) as _)),
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Field::offset(Offset(((self.code >> 0u8) & 0xffff) as _)),
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Field::rA(GPR(((self.code >> 16u8) & 0x1f) as _)),
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],
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Opcode::Stfdu => vec![
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Field::rS(GPR(((self.code >> 21u8) & 0x1f) as _)),
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Field::frS(FPR(((self.code >> 21u8) & 0x1f) as _)),
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Field::offset(Offset(((self.code >> 0u8) & 0xffff) as _)),
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Field::rA(GPR(((self.code >> 16u8) & 0x1f) as _)),
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],
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@ -2073,12 +2072,12 @@ impl Ins {
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Field::rB(GPR(((self.code >> 11u8) & 0x1f) as _)),
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],
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Opcode::Stfs => vec![
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Field::rS(GPR(((self.code >> 21u8) & 0x1f) as _)),
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Field::frS(FPR(((self.code >> 21u8) & 0x1f) as _)),
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Field::offset(Offset(((self.code >> 0u8) & 0xffff) as _)),
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Field::rA(GPR(((self.code >> 16u8) & 0x1f) as _)),
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],
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Opcode::Stfsu => vec![
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Field::rS(GPR(((self.code >> 21u8) & 0x1f) as _)),
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Field::frS(FPR(((self.code >> 21u8) & 0x1f) as _)),
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Field::offset(Offset(((self.code >> 0u8) & 0xffff) as _)),
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Field::rA(GPR(((self.code >> 16u8) & 0x1f) as _)),
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],
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@ -3368,10 +3367,7 @@ impl Ins {
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uses
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}
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Opcode::PsAbs => {
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let mut uses = vec![
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Field::frA(FPR(((self.code >> 16u8) & 0x1f) as _)),
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Field::frB(FPR(((self.code >> 11u8) & 0x1f) as _)),
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];
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let mut uses = vec![Field::frB(FPR(((self.code >> 11u8) & 0x1f) as _))];
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uses
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}
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Opcode::PsAdd => {
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@ -3652,7 +3648,7 @@ impl Ins {
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uses
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}
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Opcode::Stfd => {
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let mut uses = vec![Field::rS(GPR(((self.code >> 21u8) & 0x1f) as _))];
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let mut uses = vec![Field::frS(FPR(((self.code >> 21u8) & 0x1f) as _))];
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if ((self.code >> 16u8) & 0x1f) != 0 {
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uses.push(Field::rA(GPR(((self.code >> 16u8) & 0x1f) as _)));
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}
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@ -3660,7 +3656,7 @@ impl Ins {
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}
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Opcode::Stfdu => {
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let mut uses = vec![
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Field::rS(GPR(((self.code >> 21u8) & 0x1f) as _)),
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Field::frS(FPR(((self.code >> 21u8) & 0x1f) as _)),
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Field::rA(GPR(((self.code >> 16u8) & 0x1f) as _)),
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];
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uses
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@ -3694,7 +3690,7 @@ impl Ins {
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uses
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}
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Opcode::Stfs => {
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let mut uses = vec![Field::rS(GPR(((self.code >> 21u8) & 0x1f) as _))];
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let mut uses = vec![Field::frS(FPR(((self.code >> 21u8) & 0x1f) as _))];
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if ((self.code >> 16u8) & 0x1f) != 0 {
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uses.push(Field::rA(GPR(((self.code >> 16u8) & 0x1f) as _)));
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}
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@ -3702,7 +3698,7 @@ impl Ins {
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}
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Opcode::Stfsu => {
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let mut uses = vec![
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Field::rS(GPR(((self.code >> 21u8) & 0x1f) as _)),
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Field::frS(FPR(((self.code >> 21u8) & 0x1f) as _)),
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Field::rA(GPR(((self.code >> 16u8) & 0x1f) as _)),
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];
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uses
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@ -101,7 +101,7 @@ impl<N: PrimInt> UpperHex for ReallySigned<N> {
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// General-purpose register.
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field_arg!(GPR, u8, "r{}");
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// Floating-point register (direct or paired-singles mode).
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field_arg!(FPR, u8, "fr{}");
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field_arg!(FPR, u8, "f{}");
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// Segment register.
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field_arg!(SR, u8);
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// Special-purpose register.
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@ -109,15 +109,15 @@ field_arg!(SPR, u16);
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// Condition register field.
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field_arg!(CRField, u8, "crb{}");
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// Condition register bit (index + condition case).
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field_arg!(CRBit, u8, "crf{}");
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field_arg!(CRBit, u8, "cr{}");
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// Paired-single graphics quantization register
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field_arg!(GQR, u8);
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field_arg!(GQR, u8, "qr{}");
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// Unsigned immediate.
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field_arg!(Uimm, u16, "{:#x}");
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// Signed immediate.
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field_arg!(Simm, i16, "{:#x}", ReallySigned);
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// Offset for indirect memory reference.
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field_arg!(Offset, i32, "{:#x}", ReallySigned);
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field_arg!(Offset, i16, "{:#x}", ReallySigned);
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// Branch destination.
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field_arg!(BranchDest, i32, "{:#x}", ReallySigned);
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// Opaque zero or one argument.
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@ -35,25 +35,7 @@ fn test_ins_addi() {
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assert_asm!(0x38010018, "addi r0, r1, 0x18");
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assert_asm!(0x38010140, "addi r0, r1, 0x140");
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assert_asm!(0x38049000, "addi r0, r4, -0x7000");
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//assert_asm!(0x38a00000, "li r5, 0");
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}
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#[test]
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fn test_ins_psq_lx() {
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let ins = Ins::new(0x1000000C, 0x8000_0000u32);
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assert_eq!(ins.op, PsqLx);
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assert_eq!(
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ins.fields(),
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vec![
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frD(FPR(0)),
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rA(GPR(0)),
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rB(GPR(0)),
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ps_W(OpaqueU(0)),
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ps_l(GQR(0))
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]
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);
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assert_eq!(ins.defs(), vec![frD(FPR(0))]);
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assert_eq!(ins.uses(), vec![rB(GPR(0))]);
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assert_asm!(0x38a00000, "li r5, 0x0");
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}
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#[test]
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@ -75,7 +57,7 @@ fn test_ins_addic() {
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fn test_ins_addis() {
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assert_asm!(0x3C030000, "addis r0, r3, 0x0");
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assert_asm!(0x3C038000, "addis r0, r3, 0x8000");
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//assert_asm!(0x3D00EFCE, "lis r8, 0xefce");
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assert_asm!(0x3D00EFCE, "lis r8, 0xefce");
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}
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#[test]
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@ -89,8 +71,6 @@ fn test_ins_and() {
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assert_asm!(0x7C001839, "and. r0, r0, r3");
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}
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/*
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#[test]
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fn test_ins_andc() {
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assert_asm!(0x7C001878, "andc r0, r0, r3");
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@ -98,14 +78,14 @@ fn test_ins_andc() {
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#[test]
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fn test_ins_andi_() {
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assert_asm!(0x70000009, "andi. r0, r0, 9");
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assert_asm!(0x70000009, "andi. r0, r0, 0x9");
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}
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#[test]
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fn test_ins_andis_() {
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assert_asm!(0x77c802ff, "andis. r8, r30, 0x2ff");
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}
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/*
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#[test]
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fn test_ins_b() {
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assert_asm!(0x48000000, "b 0x0");
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@ -143,13 +123,17 @@ fn test_ins_bc() {
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assert_asm!(0x419C0008, "blt cr7, 0x8");
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assert_asm!(0x4200F560, "bdnz -0xaa0");
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}
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*/
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/*
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#[test]
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fn test_ins_bcctr() {
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assert_asm!(0x4E800420, "bctr");
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assert_asm!(0x4E800421, "bctrl");
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}
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*/
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/*
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#[test]
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fn test_ins_bclr() {
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assert_asm!(0x4C800020, "bgelr");
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@ -163,12 +147,14 @@ fn test_ins_bclr() {
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assert_asm!(0x4E800020, "blr");
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assert_asm!(0x4E800021, "blrl");
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}
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*/
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#[test]
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fn test_ins_cmp() {
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assert_asm!(0x7C030000, "cmpw r3, r0");
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}
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/*
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#[test]
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fn test_ins_cmpi() {
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assert_asm!(0x2C050D00, "cmpwi r5, 0xd00");
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@ -185,40 +171,43 @@ fn test_ins_cmpli() {
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assert_asm!(0x2803FFF3, "cmplwi r3, 0xfff3");
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assert_asm!(0x2884F8F0, "cmplwi cr1, r4, 0xf8f0");
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}
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*/
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#[test]
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fn test_ins_cntlzw() {
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assert_asm!(0x7C030034, "cntlzw r3, r0");
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}
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/*
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#[test]
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fn test_ins_cror() {
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assert_asm!(0x4C411382, "cror cr2, cr1, cr2");
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}
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*/
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#[test]
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fn test_ins_dcbf() {
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assert_asm!(0x7C0028AC, "dcbf 0, r5");
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assert_asm!(0x7C0028AC, "dcbf r0, r5");
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}
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#[test]
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fn test_ins_dcbi() {
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assert_asm!(0x7C001BAC, "dcbi 0, r3");
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assert_asm!(0x7C001BAC, "dcbi r0, r3");
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}
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#[test]
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fn test_ins_dcbst() {
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assert_asm!(0x7C00286C, "dcbst 0, r5");
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assert_asm!(0x7C00286C, "dcbst r0, r5");
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}
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#[test]
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fn test_ins_dcbt() {
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assert_asm!(0x7C001A2C, "dcbt 0, r3");
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assert_asm!(0x7C001A2C, "dcbt r0, r3");
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}
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#[test]
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fn test_ins_dcbz() {
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assert_asm!(0x7C001FEC, "dcbz 0, r3");
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assert_asm!(0x7C001FEC, "dcbz r0, r3");
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}
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#[test]
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@ -361,7 +350,7 @@ fn test_ins_fsubs() {
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#[test]
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fn test_ins_icbi() {
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assert_asm!(0x7C001FAC, "icbi 0, r3");
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assert_asm!(0x7C001FAC, "icbi r0, r3");
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}
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#[test]
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@ -437,8 +426,8 @@ fn test_ins_lha() {
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#[test]
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fn test_ins_lhau() {
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assert_asm!(0xAC060006, "lhau r0, 6(r6)");
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assert_asm!(0xAC06FFFA, "lhau r0, -6(r6)");
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assert_asm!(0xAC060006, "lhau r0, 0x6(r6)");
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assert_asm!(0xAC06FFFA, "lhau r0, -0x6(r6)");
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}
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#[test]
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@ -454,7 +443,7 @@ fn test_ins_lhz() {
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#[test]
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fn test_ins_lhzu() {
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assert_asm!(0xA40A0004, "lhzu r0, 4(r10)");
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assert_asm!(0xA40A0004, "lhzu r0, 0x4(r10)");
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}
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#[test]
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@ -474,7 +463,7 @@ fn test_ins_lmw() {
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#[test]
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fn test_ins_lwbrx() {
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assert_asm!(0x7D80242C, "lwbrx r12, 0, r4");
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assert_asm!(0x7D80242C, "lwbrx r12, r0, r4");
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}
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#[test]
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@ -501,13 +490,15 @@ fn test_ins_lwzx() {
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#[test]
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fn test_ins_mfcr() {
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assert_asm!(0x7C000026, "mfcr r0");
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assert_asm!(0x7C000026, "mfcr cr0");
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}
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/*
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#[test]
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fn test_ins_mffs() {
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assert_asm!(0xFC00048E, "mffs f0");
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}
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*/
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#[test]
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fn test_ins_mfmsr() {
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@ -516,7 +507,7 @@ fn test_ins_mfmsr() {
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#[test]
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fn test_ins_mfspr() {
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assert_asm!(0x7E1A02A6, "mfspr r16, 0x1a");
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assert_asm!(0x7E1A02A6, "mfspr r16, 832");
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}
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#[test]
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@ -526,7 +517,7 @@ fn test_ins_mfsr() {
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#[test]
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fn test_ins_mftb() {
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assert_asm!(0x7C8C42E6, "mftb r4, 0x10c");
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assert_asm!(0x7C8C42E6, "mftb r4, 392");
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}
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#[test]
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@ -557,7 +548,7 @@ fn test_ins_mtmsr() {
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#[test]
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fn test_ins_mtspr() {
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assert_asm!(0x7E75FBA6, "mtspr 0x3f5, r19");
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assert_asm!(0x7E75FBA6, "mtspr 703, r19");
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}
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#[test]
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@ -626,21 +617,40 @@ fn test_ins_psq_l() {
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assert_asm!(0xE02500AC, "psq_l f1, 0xac(r5), 0, qr0");
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}
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/*
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#[test]
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fn test_ins_psq_lu() {
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assert_asm!(0xE5435010, "psq_lu f10, 0x10(r3), 0, qr5");
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}
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*/
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#[test]
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fn test_ins_psq_lx() {
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let ins = Ins::new(0x1000000C, 0x8000_0000u32);
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assert_eq!(ins.op, PsqLx);
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assert_eq!(
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ins.fields(),
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vec![
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frD(FPR(0)),
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rA(GPR(0)),
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rB(GPR(0)),
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ps_W(OpaqueU(0)),
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ps_l(GQR(0))
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]
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);
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assert_eq!(ins.defs(), vec![frD(FPR(0))]);
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assert_eq!(ins.uses(), vec![rB(GPR(0))]);
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assert_asm!(0x1000000C, "psq_lx f0, r0, r0, 0, qr0");
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}
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/*
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#[test]
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fn test_ins_psq_st() {
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assert_asm!(0xF1230210, "psq_st f9, 0x210(r3), 0, qr0");
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assert_asm!(0xF1238008, "psq_st f9, 8(r3), 1, qr0");
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}
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*/
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#[test]
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fn test_ins_psq_stu() {
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@ -779,20 +789,20 @@ fn test_ins_rfi() {
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#[test]
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fn test_ins_rlwimi() {
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assert_asm!(0x500306FE, "rlwimi r3, r0, 0, 0x1b, 0x1f");
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assert_asm!(0x50032D74, "rlwimi r3, r0, 5, 0x15, 0x1a");
|
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assert_asm!(0x500306FE, "rlwimi r3, r0, 0, 27, 31");
|
||||
assert_asm!(0x50032D74, "rlwimi r3, r0, 5, 21, 26");
|
||||
}
|
||||
|
||||
#[test]
|
||||
fn test_ins_rlwinm() {
|
||||
assert_asm!(0x54000423, "rlwinm. r0, r0, 0, 0x10, 0x11");
|
||||
assert_asm!(0x54000432, "rlwinm r0, r0, 0, 0x10, 0x19");
|
||||
assert_asm!(0x54000423, "rlwinm. r0, r0, 0, 16, 17");
|
||||
assert_asm!(0x54000432, "rlwinm r0, r0, 0, 16, 25");
|
||||
}
|
||||
|
||||
#[test]
|
||||
fn test_ins_rlwnm() {
|
||||
assert_asm!(0x5D6A67FE, "rlwnm r10, r11, r12, 0x1f, 0x1f");
|
||||
assert_asm!(0x5FC52EFE, "rlwnm r5, r30, r5, 0x1b, 0x1f");
|
||||
assert_asm!(0x5D6A67FE, "rlwnm r10, r11, r12, 31, 31");
|
||||
assert_asm!(0x5FC52EFE, "rlwnm r5, r30, r5, 27, 31");
|
||||
}
|
||||
|
||||
#[test]
|
||||
|
|
@ -824,13 +834,13 @@ fn test_ins_srw() {
|
|||
#[test]
|
||||
fn test_ins_stb() {
|
||||
assert_asm!(0x980105EC, "stb r0, 0x5ec(r1)");
|
||||
assert_asm!(0x98030000, "stb r0, 0(r3)");
|
||||
assert_asm!(0x98030000, "stb r0, 0x0(r3)");
|
||||
}
|
||||
|
||||
#[test]
|
||||
fn test_ins_stbu() {
|
||||
assert_asm!(0x9D2A7428, "stbu r9, 0x7428(r10)");
|
||||
assert_asm!(0x9D66FFFF, "stbu r11, -1(r6)");
|
||||
assert_asm!(0x9D66FFFF, "stbu r11, -0x1(r6)");
|
||||
}
|
||||
|
||||
#[test]
|
||||
|
|
@ -854,10 +864,12 @@ fn test_ins_stfdu() {
|
|||
assert_asm!(0xDC24FFC0, "stfdu f1, -0x40(r4)");
|
||||
}
|
||||
|
||||
/*
|
||||
#[test]
|
||||
fn test_ins_stfdx() {
|
||||
assert_asm!(0x7C4405AE, "stfdx f2, r4, r0");
|
||||
}
|
||||
*/
|
||||
|
||||
#[test]
|
||||
fn test_ins_stfs() {
|
||||
|
|
@ -878,7 +890,7 @@ fn test_ins_sth() {
|
|||
|
||||
#[test]
|
||||
fn test_ins_sthbrx() {
|
||||
assert_asm!(0x7C60072C, "sthbrx r3, 0, r0");
|
||||
assert_asm!(0x7C60072C, "sthbrx r3, r0, r0");
|
||||
}
|
||||
|
||||
#[test]
|
||||
|
|
@ -909,7 +921,7 @@ fn test_ins_stw() {
|
|||
|
||||
#[test]
|
||||
fn test_ins_stwbrx() {
|
||||
assert_asm!(0x7C00FD2C, "stwbrx r0, 0, r31");
|
||||
assert_asm!(0x7C00FD2C, "stwbrx r0, r0, r31");
|
||||
}
|
||||
|
||||
#[test]
|
||||
|
|
@ -972,4 +984,3 @@ fn test_ins_xori() {
|
|||
fn test_ins_xoris() {
|
||||
assert_asm!(0x6E3D8000, "xoris r29, r17, 0x8000");
|
||||
}
|
||||
*/
|
||||
|
|
|
|||
20
isa.yaml
20
isa.yaml
|
|
@ -1319,9 +1319,9 @@ opcodes:
|
|||
bitmask: 0xfc1f07fe
|
||||
pattern: 0x10000210
|
||||
modifiers: [ Rc ]
|
||||
args: [ frD, frA, frB ]
|
||||
args: [ frD, frB ]
|
||||
defs: [ frD ]
|
||||
uses: [ frA, frB ]
|
||||
uses: [ frB ]
|
||||
|
||||
- name: ps_add
|
||||
desc: Paired Single Add
|
||||
|
|
@ -1678,16 +1678,16 @@ opcodes:
|
|||
desc: Store Floating-Point Double
|
||||
bitmask: 0xfc000000
|
||||
pattern: 0xd8000000
|
||||
args: [ rS, offset, rA ]
|
||||
uses: [ rS, rA.nz ]
|
||||
args: [ frS, offset, rA ]
|
||||
uses: [ frS, rA.nz ]
|
||||
|
||||
- name: stfdu
|
||||
desc: Store Floating-Point Double with Update
|
||||
bitmask: 0xfc000000
|
||||
pattern: 0xdc000000
|
||||
args: [ rS, offset, rA ]
|
||||
args: [ frS, offset, rA ]
|
||||
defs: [ rA ]
|
||||
uses: [ rS, rA ]
|
||||
uses: [ frS, rA ]
|
||||
|
||||
- name: stfdux
|
||||
desc: Store Floating-Point Double with Update Indexed
|
||||
|
|
@ -1715,16 +1715,16 @@ opcodes:
|
|||
desc: Store Floating-Point Single
|
||||
bitmask: 0xfc000000
|
||||
pattern: 0xd0000000
|
||||
args: [ rS, offset, rA ]
|
||||
uses: [ rS, rA.nz ]
|
||||
args: [ frS, offset, rA ]
|
||||
uses: [ frS, rA.nz ]
|
||||
|
||||
- name: stfsu
|
||||
desc: Store Floating-Point Single with Update
|
||||
bitmask: 0xfc000000
|
||||
pattern: 0xd4000000
|
||||
args: [ rS, offset, rA ]
|
||||
args: [ frS, offset, rA ]
|
||||
defs: [ rA ]
|
||||
uses: [ rS, rA ]
|
||||
uses: [ frS, rA ]
|
||||
|
||||
- name: stfsux
|
||||
desc: Store Floating-Point Single with Update Indexed
|
||||
|
|
|
|||
Loading…
Reference in New Issue