Implement all print instructions
This commit is contained in:
Richard Patel
parent
a08ef23ab6
commit
ae8503b217
537
src/main.rs
537
src/main.rs
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@ -319,6 +319,7 @@ impl Ins {
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ins_bit!(lk, 31);
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ins_bit!(l, 10);
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ins_bit!(oe, 21);
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ins_bit!(w, 16);
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// Registers
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ins_field!(s, u8, 6..11);
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@ -341,8 +342,15 @@ impl Ins {
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ins_field!(uimm, u16, 16..32);
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ins_field!(bo, u8, 6..11);
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ins_field!(bi, u8, 11..16);
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ins_field!(sh, u8, 16..21);
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ins_field!(mb, u8, 21..26);
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ins_field!(me, u8, 26..31);
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//ins_field!(bd, u16, 16..30);
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ins_field!(li, u32, 6..30);
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ins_field!(to, u8, 6..11);
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// Paired-single fields.
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ins_field!(ps_l, u8, 17..20);
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ins_field!(ps_d, u16, 20..32);
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fn disasm(x: u32) -> Self {
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let family = bits(x, 0..6);
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@ -1371,6 +1379,38 @@ impl Ins {
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(true, false) => "mullwuo",
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(true, true) => "mullwuo.",
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},
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Opcode::Stbux => "stbux",
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Opcode::Stbx => "stbx",
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Opcode::Sthux => "sthux",
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Opcode::Sthx => "sthx",
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Opcode::Sthbrx => "sthbrx",
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Opcode::Stswi => "stswx",
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Opcode::Stwbrx => "stwbrx",
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Opcode::Stwcx_ => "stwcx.",
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Opcode::Stwx => "stwx",
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Opcode::Stwux => "stwux",
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Opcode::Subf => match (self.oe(), self.rc()) {
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(false, false) => "subfu",
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(false, true) => "subfu.",
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(true, false) => "subfo",
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(true, true) => "subfo.",
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},
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Opcode::Subfc => match (self.oe(), self.rc()) {
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(false, false) => "subfcu",
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(false, true) => "subfcu.",
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(true, false) => "subfco",
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(true, true) => "subfco.",
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},
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Opcode::Subfe => match (self.oe(), self.rc()) {
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(false, false) => "subfeu",
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(false, true) => "subfeu.",
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(true, false) => "subfeo",
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(true, true) => "subfeo.",
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},
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Opcode::Xor => match self.rc() {
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false => "xor",
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true => "xor.",
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},
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_ => disasm_unreachable!(self.code),
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};
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format!("{} r{}, r{}, r{}", name, self.d(), self.a(), self.b())
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@ -1380,6 +1420,10 @@ impl Ins {
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match self.op {
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Opcode::Eieio => "eieio",
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Opcode::Isync => "isync",
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Opcode::Rfi => "rfi",
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Opcode::Sc => "sc",
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Opcode::Sync => "sync",
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Opcode::Tlbsync => "tlbsync",
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_ => disasm_unreachable!(self.code),
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}
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.to_owned()
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@ -1392,6 +1436,7 @@ impl Ins {
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Opcode::Addic_ => "addic.",
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Opcode::Addis => "addis",
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Opcode::Mulli => "mulli",
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Opcode::Subfic => "subfic",
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_ => disasm_unreachable!(self.code),
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};
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format!("{} r{}, r{}, {}", name, self.d(), self.a(), self.simm())
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@ -1403,6 +1448,8 @@ impl Ins {
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Opcode::Andis_ => "andis.",
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Opcode::Ori => "ori",
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Opcode::Oris => "oris",
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Opcode::Xori => "xori",
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Opcode::Xoris => "xoris",
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_ => disasm_unreachable!(self.code),
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};
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format!("{} r{}, r{}, {}", name, self.d(), self.a(), self.uimm())
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@ -1419,6 +1466,13 @@ impl Ins {
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Opcode::Lmw => "lmw",
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Opcode::Lwz => "lwz",
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Opcode::Lwzu => "lwzu",
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Opcode::Stb => "stb",
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Opcode::Stbu => "stbu",
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Opcode::Sth => "sth",
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Opcode::Sthu => "sthu",
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Opcode::Stmw => "stmw",
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Opcode::Stw => "stw",
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Opcode::Stwu => "stwu",
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_ => disasm_unreachable!(self.code),
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};
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format!("{} r{}, {}(r{})", name, self.d(), self.simm(), self.a())
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@ -1430,6 +1484,10 @@ impl Ins {
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Opcode::Lfdu => "lfdu",
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Opcode::Lfs => "lfs",
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Opcode::Lfsu => "lfsu",
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Opcode::Stfd => "stfd",
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Opcode::Stfdu => "stfdu",
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Opcode::Stfs => "stfs",
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Opcode::Stfsu => "stfsu",
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_ => disasm_unreachable!(self.code),
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};
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format!("{} fr{}, {}(r{})", name, self.d(), self.simm(), self.a())
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@ -1441,6 +1499,11 @@ impl Ins {
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Opcode::Lfdx => "lfdx",
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Opcode::Lfsux => "lfsux",
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Opcode::Lfsx => "lfsx",
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Opcode::Stfdux => "stfdux",
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Opcode::Stfdx => "stfdx",
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Opcode::Stfiwx => "stfiwx",
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Opcode::Stfsux => "stfsux",
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Opcode::Stfsx => "stfsx",
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_ => disasm_unreachable!(self.code),
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};
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format!("{} fr{}, r{}, r{}", name, self.d(), self.a(), self.b())
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@ -1472,6 +1535,7 @@ impl Ins {
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Opcode::Mfcr => "mfcr",
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Opcode::Mfmsr => "mfmsr",
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Opcode::Mtmsr => "mtmsr",
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Opcode::Tlbie => "tblie",
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_ => disasm_unreachable!(self.code),
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};
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format!("{} r{}", name, self.d())
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@ -1497,6 +1561,18 @@ impl Ins {
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(true, false) => "nego",
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(true, true) => "nego.",
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},
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Opcode::Subfme => match (self.oe(), self.rc()) {
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(false, false) => "subfme",
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(false, true) => "subfme.",
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(true, false) => "subfmeo",
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(true, true) => "subfmeo.",
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},
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Opcode::Subfze => match (self.oe(), self.rc()) {
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(false, false) => "subfze",
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(false, true) => "subfze.",
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(true, false) => "subfzeo",
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(true, true) => "subfzeo.",
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},
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_ => disasm_unreachable!(self.code),
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};
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format!("{} r{}, r{}", name, self.d(), self.a())
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@ -1542,114 +1618,81 @@ impl Ins {
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}
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fn to_string_form_fr13(&self) -> String {
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let name_suffix = if self.rc() { "." } else { "" };
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let name = match self.op {
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Opcode::Fabs => match self.rc() {
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false => "fabs",
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true => "fabs.",
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},
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Opcode::Fnabs => match self.rc() {
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false => "fnabs",
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true => "fnabs.",
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},
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Opcode::Fmr => match self.rc() {
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false => "fmr",
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true => "fmr.",
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},
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Opcode::Fneg => match self.rc() {
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false => "fneg",
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true => "fneg.",
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},
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Opcode::Fres => match self.rc() {
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false => "fres",
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true => "fres.",
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},
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Opcode::Frsp => match self.rc() {
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false => "frsp",
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true => "frsp.",
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},
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Opcode::Frsqrte => match self.rc() {
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false => "frsqrte",
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true => "frsqrte.",
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},
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Opcode::Fabs => "fabs",
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Opcode::Fnabs => "fnabs",
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Opcode::Fmr => "fmr",
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Opcode::Fneg => "fneg",
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Opcode::Fres => "fres",
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Opcode::Frsp => "frsp",
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Opcode::Frsqrte => "frsqrte",
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Opcode::PsAbs => "ps_abs",
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Opcode::PsMr => "ps_mr",
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Opcode::PsNabs => "ps_nabs",
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Opcode::PsNeg => "ps_neg",
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Opcode::PsRes => "ps_res",
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Opcode::PsRsqrte => "ps_rsqrte",
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Opcode::PsSum0 => "ps_sum0",
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Opcode::PsSum1 => "ps_sum1",
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_ => disasm_unreachable!(self.code),
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};
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format!("{} fr{}, fr{}", name, self.d(), self.b())
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format!("{}{} fr{}, fr{}", name, name_suffix, self.d(), self.b())
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}
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fn to_string_form_fr123(&self) -> String {
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let name_suffix = if self.rc() { "." } else { "" };
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let name = match self.op {
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Opcode::Fadd => match self.rc() {
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false => "fadd",
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true => "fadd.",
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},
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Opcode::Fadds => match self.rc() {
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false => "fadds",
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true => "fadds.",
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},
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Opcode::Fdiv => match self.rc() {
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false => "fdiv",
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true => "fdiv.",
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},
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Opcode::Fdivs => match self.rc() {
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false => "fdivs",
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true => "fdivs.",
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},
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Opcode::Fsub => match self.rc() {
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false => "fsub",
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true => "fsub.",
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},
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Opcode::Fsubs => match self.rc() {
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false => "fsubs",
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true => "fsubs.",
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},
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_ => disasm_unreachable!(self.code),
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};
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format!("{} fr{}, fr{}, fr{}", name, self.d(), self.a(), self.b())
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}
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fn to_string_form_fr1243(&self) -> String {
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let name = match self.op {
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Opcode::Fmadd => match self.rc() {
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false => "fmadd",
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true => "fmadd.",
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},
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Opcode::Fmadds => match self.rc() {
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false => "fmadds",
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true => "fmadds.",
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},
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Opcode::Fmsub => match self.rc() {
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false => "fmsub",
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true => "fmsub.",
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},
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Opcode::Fmsubs => match self.rc() {
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false => "fmsubs",
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true => "fmsubs.",
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},
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Opcode::Fnmadd => match self.rc() {
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false => "fnmadd",
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true => "fnmadd.",
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},
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Opcode::Fnmadds => match self.rc() {
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false => "fnmadds",
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true => "fnmadds.",
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},
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Opcode::Fnmsub => match self.rc() {
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false => "fnmsub",
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true => "fnmsub.",
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},
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Opcode::Fnmsubs => match self.rc() {
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false => "fnmsubs",
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true => "fnmsubs.",
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},
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Opcode::Fsel => match self.rc() {
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false => "fsel",
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true => "fsel.",
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},
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Opcode::Fadd => "fadd",
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Opcode::Fadds => "fadds",
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Opcode::Fdiv => "fdiv",
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Opcode::Fdivs => "fdivs",
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Opcode::Fsub => "fsub",
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Opcode::Fsubs => "fsubs",
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Opcode::PsAdd => "ps_add",
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Opcode::PsDiv => "ps_div",
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Opcode::PsMerge00 => "ps_merge00",
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Opcode::PsMerge01 => "ps_merge01",
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Opcode::PsMerge10 => "ps_merge10",
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Opcode::PsMerge11 => "ps_merge11",
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Opcode::PsSub => "ps_sub",
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_ => disasm_unreachable!(self.code),
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};
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format!(
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"{} fr{}, fr{}, fr{}, fr{}",
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"{}{} fr{}, fr{}, fr{}",
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name,
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name_suffix,
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self.d(),
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self.a(),
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self.b()
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)
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}
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fn to_string_form_fr1243(&self) -> String {
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let name_suffix = if self.rc() { "." } else { "" };
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let name = match self.op {
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Opcode::Fmadd => "fmadd",
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Opcode::Fmadds => "fmadds",
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Opcode::Fmsub => "fmsub",
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Opcode::Fmsubs => "fmsubs",
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Opcode::Fnmadd => "fnmadd",
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Opcode::Fnmadds => "fnmadds",
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Opcode::Fnmsub => "fnmsub",
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Opcode::Fnmsubs => "fnmsubs",
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Opcode::Fsel => "fsel",
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Opcode::PsMadd => "ps_madd",
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Opcode::PsMadds0 => "ps_madds0",
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Opcode::PsMadds1 => "ps_madds1",
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Opcode::PsMsub => "ps_msub",
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Opcode::PsNmadd => "ps_nmadd",
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Opcode::PsNmsub => "ps_nmsub",
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Opcode::PsSel => "ps_sel",
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_ => disasm_unreachable!(self.code),
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};
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format!(
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"{}{} fr{}, fr{}, fr{}, fr{}",
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name,
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name_suffix,
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self.d(),
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self.a(),
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self.c(),
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@ -1658,24 +1701,33 @@ impl Ins {
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}
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fn to_string_form_fr124(&self) -> String {
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let name_suffix = if self.rc() { "." } else { "" };
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let name = match self.op {
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Opcode::Fmul => match self.rc() {
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false => "fmul",
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true => "fmul.",
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},
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Opcode::Fmuls => match self.rc() {
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false => "fmuls",
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true => "fmuls.",
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},
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Opcode::Fmul => "fmul",
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Opcode::Fmuls => "fmuls",
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Opcode::PsMadd => "ps_madd",
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Opcode::PsMuls0 => "ps_muls0",
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Opcode::PsMuls1 => "ps_muls1",
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_ => disasm_unreachable!(self.code),
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};
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format!("{} fr{}, fr{}, fr{}", name, self.d(), self.a(), self.c())
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format!(
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"{}{} fr{}, fr{}, fr{}",
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name,
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name_suffix,
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self.d(),
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self.a(),
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self.c()
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)
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}
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fn to_string_form_condreg1_fr23(&self) -> String {
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let name = match self.op {
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Opcode::Fcmpo => "fcmpo",
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Opcode::Fcmpu => "fcmpu",
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Opcode::PsCmpo0 => "ps_cmpo0",
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Opcode::PsCmpo1 => "ps_cmpo1",
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Opcode::PsCmpu0 => "ps_cmpu0",
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Opcode::PsCmpu1 => "ps_cmpu1",
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_ => disasm_unreachable!(self.code),
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};
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format!(
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@ -1853,35 +1905,65 @@ impl Ins {
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}
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fn to_string_form_reg213(&self) -> String {
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let name_suffix = if self.rc() { "." } else { "" };
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let name = match self.op {
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Opcode::Eqv => match self.rc() {
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false => "eqv",
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true => "eqv.",
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},
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Opcode::Nand => match self.rc() {
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false => "nand",
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true => "nand.",
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},
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Opcode::Nor => match self.rc() {
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false => "nor",
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true => "nor.",
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},
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Opcode::Or => match self.rc() {
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false => "or",
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true => "or.",
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},
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Opcode::Orc => match self.rc() {
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false => "orc",
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true => "orc.",
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},
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Opcode::Eqv => "eqv",
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Opcode::Nand => "nand",
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Opcode::Nor => "nor",
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Opcode::Or => "or",
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Opcode::Orc => "orc",
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Opcode::Slw => "slw",
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Opcode::Sraw => "sraw",
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Opcode::Srw => "srw",
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_ => disasm_unreachable!(self.code),
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};
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format!("{} r{}, r{}, r{}", name, self.a(), self.s(), self.b())
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format!(
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"{}{} r{}, r{}, r{}",
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name,
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name_suffix,
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self.a(),
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self.s(),
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self.b()
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)
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}
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fn to_string_rlw_imm(&self) -> String {
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let name_prefix = if self.rc() { "." } else { "" };
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let name = match self.op {
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Opcode::Rlwimi => "rlwimi",
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Opcode::Rlwinm => "rlwinm",
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_ => disasm_unreachable!(self.code),
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};
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format!(
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"{}{} r{}, r{}, {}, {}, {}",
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name,
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name_prefix,
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self.a(),
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self.s(),
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self.sh(),
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self.mb(),
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self.me()
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)
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}
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fn to_string_rlw_reg(&self) -> String {
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assert_eq!(self.op, Opcode::Rlwnm);
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let name_prefix = if self.rc() { "." } else { "" };
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format!(
|
||||
"rlwnm{} r{}, r{}, r{}, {}, {}",
|
||||
name_prefix,
|
||||
self.a(),
|
||||
self.s(),
|
||||
self.b(),
|
||||
self.mb(),
|
||||
self.me()
|
||||
)
|
||||
}
|
||||
|
||||
fn to_string_form_reg12_nb(&self) -> String {
|
||||
let name = match self.op {
|
||||
Opcode::Lswi => "lswi",
|
||||
Opcode::Stswi => "stswi",
|
||||
_ => disasm_unreachable!(self.code),
|
||||
};
|
||||
format!("{} r{}, r{}, {}", name, self.d(), self.a(), self.b())
|
||||
|
|
@ -1924,6 +2006,44 @@ impl Ins {
|
|||
assert_eq!(self.op, Opcode::Mtcrf);
|
||||
format!("mtcrf {} r{}", self.crm(), self.s())
|
||||
}
|
||||
|
||||
fn to_string_psq(&self) -> String {
|
||||
let name = match self.op {
|
||||
Opcode::PsqL => "psq_l",
|
||||
Opcode::PsqLu => "psq_lu",
|
||||
Opcode::PsqSt => "psq_st",
|
||||
Opcode::PsqStu => "psq_stu",
|
||||
_ => disasm_unreachable!(self.code),
|
||||
};
|
||||
format!(
|
||||
"{} fr{}, {}(r{}), {}, {}",
|
||||
name,
|
||||
self.d(),
|
||||
self.ps_d(),
|
||||
self.a(),
|
||||
self.w(),
|
||||
self.ps_l()
|
||||
)
|
||||
}
|
||||
|
||||
fn to_string_psq_x(&self) -> String {
|
||||
let name = match self.op {
|
||||
Opcode::PsqLx => "psq_lx",
|
||||
Opcode::PsqLux => "psq_lux",
|
||||
Opcode::PsqStx => "psq_stx",
|
||||
Opcode::PsqStux => "psq_stux",
|
||||
_ => disasm_unreachable!(self.code),
|
||||
};
|
||||
format!(
|
||||
"{} fr{}, r{}, r{}, {}, {}",
|
||||
name,
|
||||
self.d(),
|
||||
self.a(),
|
||||
self.b(),
|
||||
self.w(),
|
||||
self.ps_l()
|
||||
)
|
||||
}
|
||||
}
|
||||
|
||||
impl ToString for Ins {
|
||||
|
|
@ -1932,11 +2052,20 @@ impl ToString for Ins {
|
|||
Opcode::Illegal => "<illegal>".to_string(),
|
||||
|
||||
// Standalone instructions
|
||||
Opcode::Eieio | Opcode::Isync => self.to_string_noargs(),
|
||||
Opcode::Eieio
|
||||
| Opcode::Isync
|
||||
| Opcode::Rfi
|
||||
| Opcode::Sc
|
||||
| Opcode::Sync
|
||||
| Opcode::Tlbsync => self.to_string_noargs(),
|
||||
|
||||
// General purpose register only
|
||||
Opcode::Mfcr | Opcode::Mfmsr | Opcode::Mtmsr => self.to_string_form_reg1(),
|
||||
Opcode::Addme | Opcode::Addze | Opcode::Neg => self.to_string_form_reg12(),
|
||||
Opcode::Mfcr | Opcode::Mfmsr | Opcode::Mtmsr | Opcode::Tlbie => {
|
||||
self.to_string_form_reg1()
|
||||
}
|
||||
Opcode::Addme | Opcode::Addze | Opcode::Neg | Opcode::Subfme | Opcode::Subfze => {
|
||||
self.to_string_form_reg12()
|
||||
}
|
||||
Opcode::Mfsrin | Opcode::Mtsrin => self.to_string_form_reg13(),
|
||||
Opcode::Cntlzw | Opcode::Extsb | Opcode::Extsh => self.to_string_form_reg21(),
|
||||
Opcode::Dcbf
|
||||
|
|
@ -1970,18 +2099,47 @@ impl ToString for Ins {
|
|||
| Opcode::Lwzx
|
||||
| Opcode::Mulhw
|
||||
| Opcode::Mulhwu
|
||||
| Opcode::Mullw => self.to_string_form_reg123(),
|
||||
Opcode::Eqv | Opcode::Nand | Opcode::Nor | Opcode::Or | Opcode::Orc => {
|
||||
self.to_string_form_reg213()
|
||||
}
|
||||
| Opcode::Mullw
|
||||
| Opcode::Stbx
|
||||
| Opcode::Stbux
|
||||
| Opcode::Sthbrx
|
||||
| Opcode::Sthx
|
||||
| Opcode::Sthux
|
||||
| Opcode::Stswx
|
||||
| Opcode::Stwbrx
|
||||
| Opcode::Stwcx_
|
||||
| Opcode::Stwx
|
||||
| Opcode::Stwux
|
||||
| Opcode::Subf
|
||||
| Opcode::Subfc
|
||||
| Opcode::Subfe
|
||||
| Opcode::Xor => self.to_string_form_reg123(),
|
||||
Opcode::Eqv
|
||||
| Opcode::Nand
|
||||
| Opcode::Nor
|
||||
| Opcode::Or
|
||||
| Opcode::Orc
|
||||
| Opcode::Slw
|
||||
| Opcode::Sraw
|
||||
| Opcode::Srw => self.to_string_form_reg213(),
|
||||
|
||||
// General purpose shifts
|
||||
Opcode::Rlwimi | Opcode::Rlwinm => self.to_string_rlw_imm(),
|
||||
Opcode::Rlwnm => self.to_string_rlw_reg(),
|
||||
|
||||
// General purpose register misc
|
||||
Opcode::Addi | Opcode::Addic | Opcode::Addic_ | Opcode::Addis | Opcode::Mulli => {
|
||||
self.to_string_form_reg12_simm()
|
||||
}
|
||||
Opcode::Andi_ | Opcode::Andis_ | Opcode::Ori | Opcode::Oris => {
|
||||
self.to_string_form_reg12_uimm()
|
||||
}
|
||||
Opcode::Addi
|
||||
| Opcode::Addic
|
||||
| Opcode::Addic_
|
||||
| Opcode::Addis
|
||||
| Opcode::Mulli
|
||||
| Opcode::Subfic => self.to_string_form_reg12_simm(),
|
||||
Opcode::Andi_
|
||||
| Opcode::Andis_
|
||||
| Opcode::Ori
|
||||
| Opcode::Oris
|
||||
| Opcode::Xori
|
||||
| Opcode::Xoris => self.to_string_form_reg12_uimm(),
|
||||
Opcode::Lbz
|
||||
| Opcode::Lbzu
|
||||
| Opcode::Lha
|
||||
|
|
@ -1990,13 +2148,36 @@ impl ToString for Ins {
|
|||
| Opcode::Lhzu
|
||||
| Opcode::Lmw
|
||||
| Opcode::Lwz
|
||||
| Opcode::Lwzu => self.to_string_form_reg12_offset(),
|
||||
Opcode::Lswi => self.to_string_form_reg12_nb(),
|
||||
| Opcode::Lwzu
|
||||
| Opcode::Stb
|
||||
| Opcode::Stbu
|
||||
| Opcode::Sth
|
||||
| Opcode::Sthu
|
||||
| Opcode::Stmw
|
||||
| Opcode::Stw
|
||||
| Opcode::Stwu => self.to_string_form_reg12_offset(),
|
||||
Opcode::Lswi | Opcode::Stswi => self.to_string_form_reg12_nb(),
|
||||
Opcode::Mfspr | Opcode::Mftb => self.to_string_form_reg1_spr(),
|
||||
Opcode::Mtspr => self.to_string_form_spr_reg1(),
|
||||
Opcode::Mfsr => self.to_string_form_reg1_sr(),
|
||||
Opcode::Mtsr => self.to_string_form_sr_reg1(),
|
||||
Opcode::Mtcrf => self.to_string_mtcrf(),
|
||||
Opcode::Srawi => {
|
||||
let name_suffix = if self.rc() { "." } else { "" };
|
||||
format!(
|
||||
"srawi{} r{}, r{}, {}",
|
||||
name_suffix,
|
||||
self.s(),
|
||||
self.a(),
|
||||
self.sh()
|
||||
)
|
||||
}
|
||||
Opcode::Tw => {
|
||||
format!("tw {}, r{}, r{}", self.to(), self.a(), self.b())
|
||||
}
|
||||
Opcode::Twi => {
|
||||
format!("twi {}, r{}, {}", self.to(), self.a(), self.simm())
|
||||
}
|
||||
|
||||
// Branch instructions
|
||||
Opcode::B => self.to_string_b(),
|
||||
|
|
@ -2016,14 +2197,29 @@ impl ToString for Ins {
|
|||
| Opcode::Fneg
|
||||
| Opcode::Fres
|
||||
| Opcode::Frsp
|
||||
| Opcode::Frsqrte => self.to_string_form_fr13(),
|
||||
| Opcode::Frsqrte
|
||||
| Opcode::PsAbs
|
||||
| Opcode::PsMr
|
||||
| Opcode::PsNabs
|
||||
| Opcode::PsNeg
|
||||
| Opcode::PsRes
|
||||
| Opcode::PsRsqrte => self.to_string_form_fr13(),
|
||||
Opcode::Fadd
|
||||
| Opcode::Fadds
|
||||
| Opcode::Fdiv
|
||||
| Opcode::Fdivs
|
||||
| Opcode::Fsub
|
||||
| Opcode::Fsubs => self.to_string_form_fr123(),
|
||||
Opcode::Fmul | Opcode::Fmuls => self.to_string_form_fr124(),
|
||||
| Opcode::Fsubs
|
||||
| Opcode::PsAdd
|
||||
| Opcode::PsDiv
|
||||
| Opcode::PsMerge00
|
||||
| Opcode::PsMerge01
|
||||
| Opcode::PsMerge10
|
||||
| Opcode::PsMerge11
|
||||
| Opcode::PsSub => self.to_string_form_fr123(),
|
||||
Opcode::Fmul | Opcode::Fmuls | Opcode::PsMul | Opcode::PsMuls0 | Opcode::PsMuls1 => {
|
||||
self.to_string_form_fr124()
|
||||
}
|
||||
Opcode::Fmadd
|
||||
| Opcode::Fmadds
|
||||
| Opcode::Fmsub
|
||||
|
|
@ -2032,17 +2228,42 @@ impl ToString for Ins {
|
|||
| Opcode::Fnmadds
|
||||
| Opcode::Fnmsub
|
||||
| Opcode::Fnmsubs
|
||||
| Opcode::Fsel => self.to_string_form_fr1243(),
|
||||
| Opcode::Fsel
|
||||
| Opcode::PsMadd
|
||||
| Opcode::PsMadds0
|
||||
| Opcode::PsMadds1
|
||||
| Opcode::PsMsub
|
||||
| Opcode::PsNmadd
|
||||
| Opcode::PsNmsub
|
||||
| Opcode::PsSel
|
||||
| Opcode::PsSum0
|
||||
| Opcode::PsSum1 => self.to_string_form_fr1243(),
|
||||
|
||||
// Floating point register misc instructions
|
||||
Opcode::Fctiw | Opcode::Fctiwz => self.to_string_form_condreg1_fr13(),
|
||||
Opcode::Fcmpo | Opcode::Fcmpu => self.to_string_form_condreg1_fr23(),
|
||||
Opcode::Lfd | Opcode::Lfdu | Opcode::Lfs | Opcode::Lfsu => {
|
||||
self.to_string_form_fr1_reg2_offset()
|
||||
}
|
||||
Opcode::Lfdux | Opcode::Lfdx | Opcode::Lfsux | Opcode::Lfsx => {
|
||||
self.to_string_form_fr1_reg23()
|
||||
}
|
||||
Opcode::Fcmpo
|
||||
| Opcode::Fcmpu
|
||||
| Opcode::PsCmpo0
|
||||
| Opcode::PsCmpo1
|
||||
| Opcode::PsCmpu0
|
||||
| Opcode::PsCmpu1 => self.to_string_form_condreg1_fr23(),
|
||||
Opcode::Lfd
|
||||
| Opcode::Lfdu
|
||||
| Opcode::Lfs
|
||||
| Opcode::Lfsu
|
||||
| Opcode::Stfd
|
||||
| Opcode::Stfdu
|
||||
| Opcode::Stfs
|
||||
| Opcode::Stfsu => self.to_string_form_fr1_reg2_offset(),
|
||||
Opcode::Lfdux
|
||||
| Opcode::Lfdx
|
||||
| Opcode::Lfsux
|
||||
| Opcode::Lfsx
|
||||
| Opcode::Stfdux
|
||||
| Opcode::Stfdx
|
||||
| Opcode::Stfiwx
|
||||
| Opcode::Stfsux
|
||||
| Opcode::Stfsx => self.to_string_form_fr1_reg23(),
|
||||
Opcode::Mtfsf => self.to_string_mtfsf(),
|
||||
|
||||
// Condition register only
|
||||
|
|
@ -2060,7 +2281,11 @@ impl ToString for Ins {
|
|||
// Condition register misc
|
||||
Opcode::Mtfsfi => self.to_string_mtfsfi(),
|
||||
|
||||
_ => todo!("can't format instruction 0x{:x}", self.code),
|
||||
// Paired-single instructions
|
||||
Opcode::PsqL | Opcode::PsqLu | Opcode::PsqSt | Opcode::PsqStu => self.to_string_psq(),
|
||||
Opcode::PsqLx | Opcode::PsqLux | Opcode::PsqStx | Opcode::PsqStux => {
|
||||
self.to_string_psq_x()
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -2140,6 +2365,10 @@ mod tests {
|
|||
Ins::disasm(0b000100_00001_00000_00000_0000000111_1).op,
|
||||
Opcode::Illegal
|
||||
);
|
||||
assert_eq!(
|
||||
Ins::disasm(0b1111100000000000000001001111000).op,
|
||||
Opcode::Illegal,
|
||||
);
|
||||
// TODO more tests
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue