isa.yaml: add fields
This commit is contained in:
Richard Patel
parent
e57fa2c659
commit
ec727af8dd
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@ -1,3 +1,88 @@
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fields:
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- name: "Rc"
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desc: "record"
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bits: "31"
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# Immediates
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- name: "simm"
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bits: "16..32"
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signed: true
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- name: "uimm"
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bits: "16..32"
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# Branch fields
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- name: "BO"
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bits: "6..11"
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- name: "BI"
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bits: "11..16"
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- name: "BD"
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desc: "branch destination"
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bits: "16..30"
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shift_left: 2
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- name: "LI"
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desc: "branch destination"
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bits: "6..30"
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shift_left: 2
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# Shift/rotate type fields
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- name: "SH"
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desc: "Shift"
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bits: "16..21"
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- name: "MB"
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desc: "Mask start"
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bits: "21..26"
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- name: "ME"
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desc: "Mask stop"
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bits: "26..31"
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# Branch bits
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- name: "AA"
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desc: "absolute"
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bits: "30"
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- name: "LK"
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desc: "save to link register"
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bits: "31"
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# Arithmetic bits
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- name: "OE"
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desc: "overflow"
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bits: "21"
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# Registers
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- name: "rS"
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bits: "6..11"
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- name: "rD"
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bits: "6..11"
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- name: "rA"
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bits: "11..16"
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- name: "rB"
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bits: "16..21"
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- name: "rC"
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bits: "21..26"
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# Condition registers
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- name: "crbD"
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bits: "6..11"
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- name: "crbA"
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bits: "11..16"
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- name: "crbB"
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bits: "16..21"
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# Condition register fields
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- name: "crfD"
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desc: "condition register field"
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bits: "6..9"
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- name: "crfS"
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desc: "condition register field"
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bits: "11..14"
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- name: "crm"
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desc: "condition register field mask"
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bits: "12..20"
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# Paired single fields
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- name: "ps_l"
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bits: "17..20"
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# Misc
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- name: "sr"
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desc: "Segment register"
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bits: "12..16"
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- name: "spr"
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desc: "Special-purpose register"
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bits: "11..21"
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split: true
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opcodes:
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- name: "add"
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desc: "Add"
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@ -148,7 +233,7 @@ opcodes:
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desc: "Compare"
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bitmask: 0xfc4007ff
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pattern: 0x7c000000
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args: [ "crfD", "L", "rA", "rB" ]
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args: [ "crfD", "cmpL", "rA", "rB" ]
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defs: [ "crfD" ]
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uses: [ "rA", "rB" ]
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@ -156,7 +241,7 @@ opcodes:
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desc: "Compare Immediate"
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bitmask: 0xfc400000
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pattern: 0x2c000000
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args: [ "crfD", "L", "rA", "simm" ]
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args: [ "crfD", "cmpL", "rA", "simm" ]
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defs: [ "crfD" ]
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uses: [ "rA" ]
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@ -164,7 +249,7 @@ opcodes:
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desc: "Compare Logical"
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bitmask: 0xfc4007ff
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pattern: 0x7c000040
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args: [ "crfD", "L", "rA", "rB" ]
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args: [ "crfD", "cmpL", "rA", "rB" ]
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defs: [ "crfD" ]
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uses: [ "rA", "rB" ]
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@ -172,7 +257,7 @@ opcodes:
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desc: "Compare Logical Immediate"
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bitmask: 0xfc400000
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pattern: 0x28000000
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args: [ "crfD", "L", "rA", "uimm" ]
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args: [ "crfD", "cmpL", "rA", "uimm" ]
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defs: [ "crfD" ]
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uses: [ "rA" ]
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@ -685,7 +770,7 @@ opcodes:
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- name: "lfdx"
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desc: "Load Floating-Point Double Indexed"
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bitmask: 0xfc0007ff
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pattern: 0x7c00045e
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pattern: 0x7c0004ae
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args: [ "frD", "rA", "rB" ]
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defs: [ "frD" ]
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uses: [ "rA.nz", "rB" ]
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@ -900,7 +985,7 @@ opcodes:
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- name: "mffs"
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desc: "Move from FPSCR"
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bitmask: 0xfc1ffffe
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pattern: 0x7c00048e
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pattern: 0xfc00048e
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modifier: [ "Rc" ]
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args: [ "crfD" ]
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defs: [ "crfD" ]
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@ -1109,7 +1194,7 @@ opcodes:
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desc: "Paired Single Quantized Load"
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bitmask: 0xfc000000
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pattern: 0xe0000000
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args: [ "frD", "offset", "rA", "W", "l" ]
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args: [ "frD", "offset", "rA", "W", "ps_l" ]
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defs: [ "frD" ]
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uses: [ "rA.nz" ]
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@ -1117,7 +1202,7 @@ opcodes:
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desc: "Paired Single Quantized Load with Update"
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bitmask: 0xfc000000
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pattern: 0xe4000000
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args: [ "frD", "offset", "rA", "W", "l" ]
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args: [ "frD", "offset", "rA", "W", "ps_l" ]
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defs: [ "frD", "rA" ]
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uses: [ "rA" ]
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@ -1125,7 +1210,7 @@ opcodes:
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desc: "Paired Single Quantized Load with Update Indexed"
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bitmask: 0xfc00007f
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pattern: 0x1000004c
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args: [ "frD", "rA", "rB", "W", "l" ]
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args: [ "frD", "rA", "rB", "W", "ps_l" ]
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defs: [ "frD", "rA" ]
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uses: [ "rA", "rB" ]
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@ -1133,7 +1218,7 @@ opcodes:
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desc: "Paired Single Quantized Load Indexed"
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bitmask: 0xfc00007f
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pattern: 0x1000000c
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args: [ "frD", "rA", "rB", "W", "l" ]
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args: [ "frD", "rA", "rB", "W", "ps_l" ]
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defs: [ "frD" ]
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uses: [ "rA.nz", "rB" ]
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@ -1141,14 +1226,14 @@ opcodes:
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desc: "Paired Single Quantized Store"
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bitmask: 0xfc000000
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pattern: 0xf0000000
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args: [ "frS", "offset", "rA", "W", "l" ]
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args: [ "frS", "offset", "rA", "W", "ps_l" ]
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uses: [ "frS", "rA.nz" ]
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- name: "psq_stu"
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desc: "Paired Single Quantized Store with Update"
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bitmask: 0xfc000000
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pattern: 0xf4000000
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args: [ "frS", "offset", "rA", "W", "l" ]
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args: [ "frS", "offset", "rA", "W", "ps_l" ]
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defs: [ "rA" ]
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uses: [ "frS", "rA" ]
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@ -1156,7 +1241,7 @@ opcodes:
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desc: "Paired Single Quantized Store with Update Indexed"
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bitmask: 0xfc00007f
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pattern: 0x1000004e
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args: [ "frS", "rA", "rB", "W", "l" ]
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args: [ "frS", "rA", "rB", "W", "ps_l" ]
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defs: [ "rA" ]
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uses: [ "frS", "rA", "rB" ]
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@ -1164,7 +1249,7 @@ opcodes:
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desc: "Paired Single Quantized Store Indexed"
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bitmask: 0xfc00007f
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pattern: 0x1000000e
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args: [ "frS", "rA", "rB", "W", "l" ]
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args: [ "frS", "rA", "rB", "W", "ps_l" ]
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uses: [ "frS", "rA.nz", "rB" ]
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- name: "ps_abs"
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@ -1805,12 +1890,215 @@ opcodes:
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uses: [ "rS" ]
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mnemonics:
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# Arithmetic
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- name: "lis"
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opcode: "addis"
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args: [ "rD", "uimm" ]
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match:
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- arg: rA
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value: 0
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- name: "li"
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opcode: "addi"
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args: [ "rD", "simm" ]
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match:
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- arg: rA
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value: 0
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- name: "mr"
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opcode: "or"
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args: [ "rA", "rS" ]
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condition: "S == B"
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- name: "nop"
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opcode: "ori"
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condition:
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- arg: "rA"
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value: 0
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- arg: "rS"
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value: 0
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- arg: "uimm"
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value: 0
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# Rotates/Shifts
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- name: "clrlwi"
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opcode: "rlwinm"
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args: [ "rA", "rS", "MB" ]
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condition: "SH == 0 && ME == 31"
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- name: "rotlwi"
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opcode: "rlwinm"
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args: [ "rA", "rS", "SH" ]
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condition: "MB == 0 && ME == 31"
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- name: "slwi"
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opcode: "rlwinm"
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args: [ "rA", "rS", "ME" ]
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condition: "MB == 0 && 31 - SH == ME"
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- name: "srwi"
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opcode: "rlwinm"
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args: [ "rA", "rS", "MB" ]
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condition: "ME == 31 && 32 - MB == SH"
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# Compares
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- name: "cmpw"
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opcode: "cmp"
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args: [ "rA", "rB" ]
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match:
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- arg: "crfD"
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value: 0
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- arg: "cmpL"
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value: 0
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- name: "cmpw"
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opcode: "cmp"
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args: [ "crfD", "rA", "rB" ]
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match:
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- arg: "cmpL"
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value: 0
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- name: "cmplw"
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opcode: "cmpl"
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args: [ "rA", "rB" ]
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match:
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- arg: "crfD"
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value: 0
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- arg: "cmpL"
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value: 0
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- name: "cmplw"
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opcode: "cmpl"
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args: [ "crfD", "rA", "rB" ]
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match:
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- arg: "cmpL"
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value: 0
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- name: "cmpwi"
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opcode: "cmpi"
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args: [ "rA", "simm" ]
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match:
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- arg: "crfD"
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value: 0
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- arg: "cmpL"
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value: 0
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- name: "cmpwi"
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opcode: "cmpi"
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args: [ "crfD", "rA", "simm" ]
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match:
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- arg: "crfD"
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value: 0
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- arg: "cmpL"
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value: 0
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- name: "cmplwi"
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opcode: "cmpli"
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args: [ "rA", "uimm" ]
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match:
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- arg: "crfD"
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value: 0
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- arg: "cmpL"
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value: 0
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- name: "cmplwi"
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opcode: "cmpli"
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args: [ "crfD", "rA", "uimm" ]
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match:
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- arg: "crfD"
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value: 0
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- arg: "cmpL"
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value: 0
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# Misc
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- name: "twgti"
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opcode: "twi"
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args: [ "rA", "simm" ]
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match:
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- arg: TO
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value: 8
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- name: "twllei"
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opcode: "twi"
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args: [ "rA", "simm" ]
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match:
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- arg: TO
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value: 6
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- name: "twui"
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args: [ "rA", "simm" ]
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match:
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- arg: TO
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value: 31
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# Branches
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- name: "blr"
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opcode: "bclr"
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match:
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- arg: BO
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value: 20
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- arg: BI
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value: 0
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# Move to special-purpose register
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- name: "mtxer"
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opcode: "mtspr"
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args: [ "rS" ]
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match:
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- arg: "spr"
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value: 1
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- name: "mtlr"
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opcode: "mtspr"
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args: [ "rS" ]
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match:
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- arg: "spr"
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value: 8
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- name: "mtctr"
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opcode: "mtspr"
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args: [ "rS" ]
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match:
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- arg: "spr"
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value: 9
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- name: "mtdsisr"
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opcode: "mtspr"
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args: [ "rS" ]
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match:
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- arg: "spr"
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value: 18
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- name: "mtdbatu"
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opcode: "mtspr"
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args: [ "rS" ]
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match:
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- arg: "spr"
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value: 397
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- name: "mttdu"
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opcode: "mtspr"
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args: [ "rS" ]
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match:
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- arg: "spr"
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value: 571
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# Move from special-purpose register
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- name: "mfxer"
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opcode: "mfspr"
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args: [ "rD" ]
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match:
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- arg: "spr"
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value: 1
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- name: "mflr"
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opcode: "mfspr"
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args: [ "rD" ]
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match:
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- arg: "spr"
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value: 8
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- name: "mfctr"
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opcode: "mfspr"
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args: [ "rD" ]
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match:
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- arg: "spr"
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value: 9
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- name: "mfdsisr"
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opcode: "mfspr"
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args: [ "rD" ]
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match:
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- arg: "spr"
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value: 18
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- name: "mfdbatu"
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opcode: "mfspr"
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args: [ "rD" ]
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match:
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- arg: "spr"
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value: 397
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- name: "mftdu"
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opcode: "mfspr"
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args: [ "rD" ]
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match:
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- arg: "spr"
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value: 571
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# Branch Conditional
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- name: "blt"
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