mirror of https://github.com/AxioDL/metaforce.git
Add shader mode for constant alpha overwrite
This commit is contained in:
parent
ae076c5a32
commit
7a60440d58
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@ -1 +1 @@
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Subproject commit 25dfeb64aae6321ec18b82b1608b3624f1f5279c
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Subproject commit 1e5e26ced8cdb7e91cc6e6076457bfe14cb75b51
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@ -143,6 +143,7 @@ public:
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bool noDepthWrite = false;
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bool noDepthWrite = false;
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bool noColorWrite = false;
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bool noColorWrite = false;
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bool noAlphaWrite = false;
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bool noAlphaWrite = false;
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bool noAlphaOverwrite = false;
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bool noReflection = false;
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bool noReflection = false;
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};
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};
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std::vector<ExtensionSlot> m_extensionSlots;
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std::vector<ExtensionSlot> m_extensionSlots;
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@ -164,6 +165,7 @@ public:
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bool noDepthWrite = false,
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bool noDepthWrite = false,
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bool noColorWrite = false,
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bool noColorWrite = false,
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bool noAlphaWrite = false,
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bool noAlphaWrite = false,
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bool noAlphaOverwrite = false,
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bool noReflection = false)
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bool noReflection = false)
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{
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{
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m_extensionSlots.emplace_back();
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m_extensionSlots.emplace_back();
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@ -181,6 +183,7 @@ public:
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slot.noDepthWrite = noDepthWrite;
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slot.noDepthWrite = noDepthWrite;
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slot.noColorWrite = noColorWrite;
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slot.noColorWrite = noColorWrite;
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slot.noAlphaWrite = noAlphaWrite;
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slot.noAlphaWrite = noAlphaWrite;
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slot.noAlphaOverwrite = noAlphaOverwrite;
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slot.noReflection = noReflection;
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slot.noReflection = noReflection;
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return m_extensionSlots.size() - 1;
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return m_extensionSlots.size() - 1;
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}
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}
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@ -15,9 +15,9 @@ std::string GLSL::EmitTexGenSource2(TexGenSrc src, int uvIdx) const
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switch (src)
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switch (src)
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{
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{
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case TexGenSrc::Position:
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case TexGenSrc::Position:
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return "posIn.xy";
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return "vtf.mvPos.xy";
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case TexGenSrc::Normal:
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case TexGenSrc::Normal:
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return "normIn.xy";
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return "vtf.mvNorm.xy";
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case TexGenSrc::UV:
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case TexGenSrc::UV:
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return hecl::Format("uvIn[%u]", uvIdx);
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return hecl::Format("uvIn[%u]", uvIdx);
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default: break;
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default: break;
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@ -30,9 +30,9 @@ std::string GLSL::EmitTexGenSource4(TexGenSrc src, int uvIdx) const
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switch (src)
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switch (src)
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{
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{
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case TexGenSrc::Position:
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case TexGenSrc::Position:
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return "vec4(posIn, 1.0)";
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return "vec4(vtf.mvPos.xyz, 1.0)";
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case TexGenSrc::Normal:
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case TexGenSrc::Normal:
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return "vec4(normIn, 1.0)";
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return "vec4(vtf.mvNorm.xyz, 1.0)";
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case TexGenSrc::UV:
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case TexGenSrc::UV:
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return hecl::Format("vec4(uvIn[%u], 0.0, 1.0)", uvIdx);
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return hecl::Format("vec4(uvIn[%u], 0.0, 1.0)", uvIdx);
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default: break;
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default: break;
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@ -546,7 +546,7 @@ struct GLSLBackendFactory : IShaderBackendFactory
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tag.getPrimType(), zTest, slot.noDepthWrite ? false : tag.getDepthWrite(), !slot.noColorWrite, !slot.noAlphaWrite,
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tag.getPrimType(), zTest, slot.noDepthWrite ? false : tag.getDepthWrite(), !slot.noColorWrite, !slot.noAlphaWrite,
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(slot.cullMode == hecl::Backend::CullMode::Original) ?
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(slot.cullMode == hecl::Backend::CullMode::Original) ?
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(tag.getBackfaceCulling() ? boo::CullMode::Backface : boo::CullMode::None) :
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(tag.getBackfaceCulling() ? boo::CullMode::Backface : boo::CullMode::None) :
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boo::CullMode(slot.cullMode));
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boo::CullMode(slot.cullMode), !slot.noAlphaOverwrite);
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if (!ret)
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if (!ret)
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Log.report(logvisor::Fatal, "unable to build shader");
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Log.report(logvisor::Fatal, "unable to build shader");
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returnFunc(ret);
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returnFunc(ret);
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@ -635,7 +635,7 @@ struct GLSLBackendFactory : IShaderBackendFactory
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tag.getPrimType(), zTest, slot.noDepthWrite ? false : tag.getDepthWrite(), !slot.noColorWrite, !slot.noAlphaWrite,
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tag.getPrimType(), zTest, slot.noDepthWrite ? false : tag.getDepthWrite(), !slot.noColorWrite, !slot.noAlphaWrite,
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(slot.cullMode == hecl::Backend::CullMode::Original) ?
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(slot.cullMode == hecl::Backend::CullMode::Original) ?
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(tag.getBackfaceCulling() ? boo::CullMode::Backface : boo::CullMode::None) :
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(tag.getBackfaceCulling() ? boo::CullMode::Backface : boo::CullMode::None) :
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boo::CullMode(slot.cullMode));
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boo::CullMode(slot.cullMode), !slot.noAlphaOverwrite);
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if (!ret)
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if (!ret)
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Log.report(logvisor::Fatal, "unable to build shader");
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Log.report(logvisor::Fatal, "unable to build shader");
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returnFunc(ret);
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returnFunc(ret);
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@ -817,7 +817,7 @@ struct SPIRVBackendFactory : IShaderBackendFactory
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!slot.noColorWrite, !slot.noAlphaWrite,
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!slot.noColorWrite, !slot.noAlphaWrite,
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(slot.cullMode == hecl::Backend::CullMode::Original) ?
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(slot.cullMode == hecl::Backend::CullMode::Original) ?
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(tag.getBackfaceCulling() ? boo::CullMode::Backface : boo::CullMode::None) :
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(tag.getBackfaceCulling() ? boo::CullMode::Backface : boo::CullMode::None) :
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boo::CullMode(slot.cullMode));
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boo::CullMode(slot.cullMode), !slot.noAlphaOverwrite);
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if (!ret)
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if (!ret)
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Log.report(logvisor::Fatal, "unable to build shader");
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Log.report(logvisor::Fatal, "unable to build shader");
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cachedSz += pipeBlob.vert.size() * sizeof(unsigned int);
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cachedSz += pipeBlob.vert.size() * sizeof(unsigned int);
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@ -932,7 +932,7 @@ struct SPIRVBackendFactory : IShaderBackendFactory
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!slot.noColorWrite, !slot.noAlphaWrite,
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!slot.noColorWrite, !slot.noAlphaWrite,
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(slot.cullMode == hecl::Backend::CullMode::Original) ?
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(slot.cullMode == hecl::Backend::CullMode::Original) ?
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(tag.getBackfaceCulling() ? boo::CullMode::Backface : boo::CullMode::None) :
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(tag.getBackfaceCulling() ? boo::CullMode::Backface : boo::CullMode::None) :
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boo::CullMode(slot.cullMode));
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boo::CullMode(slot.cullMode), !slot.noAlphaOverwrite);
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if (!ret)
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if (!ret)
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Log.report(logvisor::Fatal, "unable to build shader");
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Log.report(logvisor::Fatal, "unable to build shader");
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returnFunc(ret);
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returnFunc(ret);
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@ -14,9 +14,9 @@ std::string HLSL::EmitTexGenSource2(TexGenSrc src, int uvIdx) const
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switch (src)
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switch (src)
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{
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{
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case TexGenSrc::Position:
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case TexGenSrc::Position:
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return "v.posIn.xy\n";
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return "vtf.mvPos.xy\n";
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case TexGenSrc::Normal:
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case TexGenSrc::Normal:
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return "v.normIn.xy\n";
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return "vtf.mvNorm.xy\n";
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case TexGenSrc::UV:
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case TexGenSrc::UV:
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return hecl::Format("v.uvIn[%u]", uvIdx);
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return hecl::Format("v.uvIn[%u]", uvIdx);
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default: break;
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default: break;
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@ -29,9 +29,9 @@ std::string HLSL::EmitTexGenSource4(TexGenSrc src, int uvIdx) const
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switch (src)
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switch (src)
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{
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{
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case TexGenSrc::Position:
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case TexGenSrc::Position:
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return "float4(v.posIn, 1.0)\n";
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return "float4(vtf.mvPos.xyz, 1.0)\n";
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case TexGenSrc::Normal:
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case TexGenSrc::Normal:
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return "float4(v.normIn, 1.0)\n";
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return "float4(vtf.mvNorm.xyz, 1.0)\n";
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case TexGenSrc::UV:
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case TexGenSrc::UV:
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return hecl::Format("float4(v.uvIn[%u], 0.0, 1.0)", uvIdx);
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return hecl::Format("float4(v.uvIn[%u], 0.0, 1.0)", uvIdx);
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default: break;
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default: break;
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@ -544,7 +544,7 @@ struct HLSLBackendFactory : IShaderBackendFactory
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!slot.noColorWrite, !slot.noAlphaWrite,
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!slot.noColorWrite, !slot.noAlphaWrite,
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(slot.cullMode == hecl::Backend::CullMode::Original) ?
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(slot.cullMode == hecl::Backend::CullMode::Original) ?
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(tag.getBackfaceCulling() ? boo::CullMode::Backface : boo::CullMode::None) :
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(tag.getBackfaceCulling() ? boo::CullMode::Backface : boo::CullMode::None) :
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boo::CullMode(slot.cullMode));
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boo::CullMode(slot.cullMode), !slot.noAlphaOverwrite);
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if (!ret)
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if (!ret)
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Log.report(logvisor::Fatal, "unable to build shader");
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Log.report(logvisor::Fatal, "unable to build shader");
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if (thisPipeBlobs.vert)
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if (thisPipeBlobs.vert)
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@ -665,7 +665,7 @@ struct HLSLBackendFactory : IShaderBackendFactory
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!slot.noColorWrite, !slot.noAlphaWrite,
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!slot.noColorWrite, !slot.noAlphaWrite,
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(slot.cullMode == hecl::Backend::CullMode::Original) ?
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(slot.cullMode == hecl::Backend::CullMode::Original) ?
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(tag.getBackfaceCulling() ? boo::CullMode::Backface : boo::CullMode::None) :
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(tag.getBackfaceCulling() ? boo::CullMode::Backface : boo::CullMode::None) :
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boo::CullMode(slot.cullMode));
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boo::CullMode(slot.cullMode), !slot.noAlphaOverwrite);
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if (!ret)
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if (!ret)
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Log.report(logvisor::Fatal, "unable to build shader");
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Log.report(logvisor::Fatal, "unable to build shader");
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returnFunc(ret);
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returnFunc(ret);
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@ -14,9 +14,9 @@ std::string Metal::EmitTexGenSource2(TexGenSrc src, int uvIdx) const
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switch (src)
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switch (src)
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{
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{
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case TexGenSrc::Position:
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case TexGenSrc::Position:
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return "v.posIn.xy\n";
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return "vtf.mvPos.xy\n";
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case TexGenSrc::Normal:
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case TexGenSrc::Normal:
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return "v.normIn.xy\n";
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return "vtf.mvNorm.xy\n";
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case TexGenSrc::UV:
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case TexGenSrc::UV:
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return hecl::Format("v.uvIn%u", uvIdx);
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return hecl::Format("v.uvIn%u", uvIdx);
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default: break;
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default: break;
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@ -29,9 +29,9 @@ std::string Metal::EmitTexGenSource4(TexGenSrc src, int uvIdx) const
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switch (src)
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switch (src)
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{
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{
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case TexGenSrc::Position:
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case TexGenSrc::Position:
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return "float4(v.posIn, 1.0)\n";
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return "float4(vtf.mvPos.xyz, 1.0)\n";
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case TexGenSrc::Normal:
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case TexGenSrc::Normal:
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return "float4(v.normIn, 1.0)\n";
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return "float4(vtf.mvNorm.xyz, 1.0)\n";
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case TexGenSrc::UV:
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case TexGenSrc::UV:
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return hecl::Format("float4(v.uvIn%u, 0.0, 1.0)", uvIdx);
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return hecl::Format("float4(v.uvIn%u, 0.0, 1.0)", uvIdx);
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default: break;
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default: break;
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@ -576,7 +576,7 @@ struct MetalBackendFactory : IShaderBackendFactory
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!slot.noColorWrite, !slot.noAlphaWrite,
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!slot.noColorWrite, !slot.noAlphaWrite,
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(slot.cullMode == hecl::Backend::CullMode::Original) ?
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(slot.cullMode == hecl::Backend::CullMode::Original) ?
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(tag.getBackfaceCulling() ? boo::CullMode::Backface : boo::CullMode::None) :
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(tag.getBackfaceCulling() ? boo::CullMode::Backface : boo::CullMode::None) :
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boo::CullMode(slot.cullMode));
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boo::CullMode(slot.cullMode), !slot.noAlphaOverwrite);
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if (!ret)
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if (!ret)
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Log.report(logvisor::Fatal, "unable to build shader");
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Log.report(logvisor::Fatal, "unable to build shader");
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@ -665,7 +665,7 @@ struct MetalBackendFactory : IShaderBackendFactory
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!slot.noColorWrite, !slot.noAlphaWrite,
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!slot.noColorWrite, !slot.noAlphaWrite,
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(slot.cullMode == hecl::Backend::CullMode::Original) ?
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(slot.cullMode == hecl::Backend::CullMode::Original) ?
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(tag.getBackfaceCulling() ? boo::CullMode::Backface : boo::CullMode::None) :
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(tag.getBackfaceCulling() ? boo::CullMode::Backface : boo::CullMode::None) :
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boo::CullMode(slot.cullMode));
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boo::CullMode(slot.cullMode), !slot.noAlphaOverwrite);
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if (!ret)
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if (!ret)
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Log.report(logvisor::Fatal, "unable to build shader");
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Log.report(logvisor::Fatal, "unable to build shader");
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returnFunc(ret);
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returnFunc(ret);
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@ -71,6 +71,8 @@ uint64_t ShaderCacheExtensions::hashExtensions() const
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UpdateFieldHash(&st, slot.noDepthWrite);
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UpdateFieldHash(&st, slot.noDepthWrite);
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UpdateFieldHash(&st, slot.noColorWrite);
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UpdateFieldHash(&st, slot.noColorWrite);
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UpdateFieldHash(&st, slot.noAlphaWrite);
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UpdateFieldHash(&st, slot.noAlphaWrite);
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UpdateFieldHash(&st, slot.noAlphaOverwrite);
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UpdateFieldHash(&st, slot.noReflection);
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}
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}
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return XXH64_digest(&st);
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return XXH64_digest(&st);
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}
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}
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