mirror of https://github.com/AxioDL/metaforce.git
256 lines
7.2 KiB
C++
256 lines
7.2 KiB
C++
#include "hecl/Frontend.hpp"
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namespace hecl::Frontend
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{
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int IR::Instruction::getChildCount() const
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{
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switch (m_op)
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{
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case OpType::Call:
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return m_call.m_argInstIdxs.size();
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case OpType::Arithmetic:
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return 2;
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case OpType::Swizzle:
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return 1;
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default:
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LogModule.report(logvisor::Fatal, "invalid op type");
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}
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return -1;
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}
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const IR::Instruction& IR::Instruction::getChildInst(const IR& ir, size_t idx) const
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{
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switch (m_op)
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{
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case OpType::Call:
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return ir.m_instructions.at(m_call.m_argInstIdxs.at(idx));
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case OpType::Arithmetic:
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if (idx > 1)
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LogModule.report(logvisor::Fatal, "arithmetic child idx must be 0 or 1");
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return ir.m_instructions.at(m_arithmetic.m_instIdxs[idx]);
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case OpType::Swizzle:
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if (idx > 0)
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LogModule.report(logvisor::Fatal, "swizzle child idx must be 0");
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return ir.m_instructions.at(m_swizzle.m_instIdx);
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default:
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LogModule.report(logvisor::Fatal, "invalid op type");
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}
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return *this;
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}
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const atVec4f& IR::Instruction::getImmVec() const
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{
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if (m_op != OpType::LoadImm)
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LogModule.report(logvisor::Fatal, "invalid op type");
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return m_loadImm.m_immVec;
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}
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template <class Op>
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void IR::Instruction::Enumerate(typename Op::StreamT& s)
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{
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Do<Op>({"op"}, m_op, s);
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Do<Op>({"target"}, m_target, s);
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switch (m_op)
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{
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default: break;
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case OpType::Call:
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Do<Op>({"call"}, m_call, s);
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break;
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case OpType::LoadImm:
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Do<Op>({"loadImm"}, m_loadImm, s);
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break;
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case OpType::Arithmetic:
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Do<Op>({"arithmetic"}, m_arithmetic, s);
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break;
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case OpType::Swizzle:
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Do<Op>({"swizzle"}, m_swizzle, s);
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break;
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}
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}
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atInt8 IR::swizzleCompIdx(char aChar)
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{
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switch (aChar)
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{
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case 'x':
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case 'r':
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return 0;
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case 'y':
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case 'g':
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return 1;
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case 'z':
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case 'b':
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return 2;
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case 'w':
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case 'a':
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return 3;
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default:
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break;
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}
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return -1;
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}
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int IR::addInstruction(const IRNode& n, IR::RegID target)
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{
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if (n.kind == IRNode::Kind::None)
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return -1;
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switch (n.kind)
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{
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case IRNode::Kind::Call:
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{
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if (!n.str.compare("vec3") && n.children.size() >= 3)
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{
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atVec4f vec = {};
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auto it = n.children.cbegin();
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int i;
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for (i=0 ; i<3 ; ++i, ++it)
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{
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if (it->kind != IRNode::Kind::Imm)
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break;
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vec.vec[i] = it->val;
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}
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if (i == 3)
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{
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m_instructions.emplace_back(OpType::LoadImm, target, n.loc);
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Instruction::LoadImm& inst = m_instructions.back().m_loadImm;
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inst.m_immVec = vec;
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return m_instructions.size() - 1;
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}
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}
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else if (!n.str.compare("vec4") && n.children.size() >= 4)
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{
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atVec4f vec = {};
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auto it = n.children.cbegin();
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int i;
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for (i=0 ; i<4 ; ++i, ++it)
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{
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if (it->kind != IRNode::Kind::Imm)
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break;
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vec.vec[i] = it->val;
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}
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if (i == 4)
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{
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m_instructions.emplace_back(OpType::LoadImm, target, n.loc);
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Instruction::LoadImm& inst = m_instructions.back().m_loadImm;
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inst.m_immVec = vec;
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return m_instructions.size() - 1;
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}
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}
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std::vector<atUint16> argInstIdxs;
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argInstIdxs.reserve(n.children.size());
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IR::RegID tgt = target;
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for (auto& c : n.children)
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argInstIdxs.push_back(addInstruction(c, tgt++));
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m_instructions.emplace_back(OpType::Call, target, n.loc);
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Instruction::Call& inst = m_instructions.back().m_call;
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inst.m_name = n.str;
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inst.m_argInstCount = atUint16(argInstIdxs.size());
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inst.m_argInstIdxs = argInstIdxs;
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return m_instructions.size() - 1;
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}
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case IRNode::Kind::Imm:
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{
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m_instructions.emplace_back(OpType::LoadImm, target, n.loc);
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Instruction::LoadImm& inst = m_instructions.back().m_loadImm;
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inst.m_immVec.vec[0] = n.val;
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inst.m_immVec.vec[1] = n.val;
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inst.m_immVec.vec[2] = n.val;
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inst.m_immVec.vec[3] = n.val;
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return m_instructions.size() - 1;
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}
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case IRNode::Kind::Binop:
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{
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atUint16 left = addInstruction(*n.left, target);
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atUint16 right = addInstruction(*n.right, target + 1);
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m_instructions.emplace_back(OpType::Arithmetic, target, n.loc);
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Instruction::Arithmetic& inst = m_instructions.back().m_arithmetic;
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inst.m_op = Instruction::ArithmeticOpType(int(n.op) + 1);
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inst.m_instIdxs[0] = left;
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inst.m_instIdxs[1] = right;
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return m_instructions.size() - 1;
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}
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case IRNode::Kind::Swizzle:
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{
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atUint16 left = addInstruction(*n.left, target);
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m_instructions.emplace_back(OpType::Swizzle, target, n.loc);
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Instruction::Swizzle& inst = m_instructions.back().m_swizzle;
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for (int i=0 ; i<n.str.size() && i<4 ; ++i)
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inst.m_idxs[i] = swizzleCompIdx(n.str[i]);
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inst.m_instIdx = left;
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return m_instructions.size() - 1;
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}
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default:
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return -1;
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}
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}
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template <>
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void IR::Enumerate<BigDNA::Read>(typename Read::StreamT& reader)
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{
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m_hash = reader.readUint64Big();
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m_regCount = reader.readUint16Big();
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atUint16 instCount = reader.readUint16Big();
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m_instructions.clear();
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m_instructions.reserve(instCount);
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for (atUint16 i=0 ; i<instCount ; ++i)
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m_instructions.emplace_back(reader);
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/* Pre-resolve blending mode */
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const IR::Instruction& rootCall = m_instructions.back();
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m_doAlpha = false;
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if (!rootCall.m_call.m_name.compare("HECLOpaque"))
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{
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m_blendSrc = boo::BlendFactor::One;
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m_blendDst = boo::BlendFactor::Zero;
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}
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else if (!rootCall.m_call.m_name.compare("HECLAlpha"))
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{
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m_blendSrc = boo::BlendFactor::SrcAlpha;
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m_blendDst = boo::BlendFactor::InvSrcAlpha;
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m_doAlpha = true;
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}
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else if (!rootCall.m_call.m_name.compare("HECLAdditive"))
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{
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m_blendSrc = boo::BlendFactor::SrcAlpha;
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m_blendDst = boo::BlendFactor::One;
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m_doAlpha = true;
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}
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}
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template <>
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void IR::Enumerate<BigDNA::Write>(typename Write::StreamT& writer)
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{
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writer.writeUint64Big(m_hash);
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writer.writeUint16Big(m_regCount);
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writer.writeUint16Big(m_instructions.size());
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for (const Instruction& inst : m_instructions)
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inst.write(writer);
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}
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template <>
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void IR::Enumerate<BigDNA::BinarySize>(typename BinarySize::StreamT& sz)
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{
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sz += 12;
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for (const Instruction& inst : m_instructions)
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inst.binarySize(sz);
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}
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IR Frontend::compileSource(std::string_view source, std::string_view diagName)
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{
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m_diag.reset(diagName, source);
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m_parser.reset(source);
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auto insts = m_parser.parse();
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IR ir;
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std::string stripString;
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if (!insts.empty())
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stripString = insts.front().toString(true);
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ir.m_hash = Hash(stripString).val64();
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for (auto& inst : insts)
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ir.addInstruction(inst, 0);
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return ir;
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}
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}
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