parent
d9770c48b2
commit
53c6d74a6b
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@ -257,7 +257,8 @@ impl VM {
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self.gpr[ins.field_ra() as usize],
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);
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} else {
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let left = if ins.field_ra() == 0 && ins.op == Opcode::Addi {
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let load_zero = ins.field_ra() == 0 && ins.op == Opcode::Addi;
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let left = if load_zero {
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GprValue::Constant(0)
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} else {
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self.gpr[ins.field_ra() as usize].value
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@ -271,7 +272,7 @@ impl VM {
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),
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_ => GprValue::Unknown,
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};
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if ins.field_ra() == 0 {
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if load_zero {
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// li rD, SIMM
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self.gpr[ins.field_rd() as usize].set_direct(value);
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} else {
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