Version 3.4.2

arm: Fix .word reading 4 bytes when less than 4 remain (#285 )
Update test snapshots for new cwextab
2025-12-15 16:16:15 +00:00 · 2025-11-21 22:15:20 -07:00 · 2025-11-20 15:38:55 -07:00 · 2025-11-18 22:29:42 -07:00 · 2025-11-18 22:22:43 -07:00 · 2025-11-18 22:22:02 -07:00
36 changed files with 2067 additions and 1560 deletions
--- a/Cargo.lock
+++ b/Cargo.lock
--- a/Cargo.toml
+++ b/Cargo.toml
@@ -14,7 +14,7 @@ default-members = [
 resolver = "3"

 [workspace.package]
-version = "3.3.0"
+version = "3.4.2"
 authors = ["Luke Street <luke@street.dev>"]
 edition = "2024"
 license = "MIT OR Apache-2.0"
--- a/deny.toml
+++ b/deny.toml
@@ -75,6 +75,7 @@ ignore = [
    #{ crate = "a-crate-that-is-yanked@0.1.1", reason = "you can specify why you are ignoring the yanked crate" },
    { id = "RUSTSEC-2024-0436", reason = "Unmaintained paste crate is an indirect dependency" },
    { id = "RUSTSEC-2025-0052", reason = "Unmaintained async-std crate is an indirect dependency" },
+    { id = "RUSTSEC-2025-0119", reason = "Unmaintained number_prefix crate is an indirect dependency" },
 ]
 # If this is true, then cargo deny will use the git executable to fetch advisory database.
 # If this is false, then it uses a built-in git library.
--- a/objdiff-cli/Cargo.toml
+++ b/objdiff-cli/Cargo.toml
@@ -16,19 +16,19 @@ publish = false
 anyhow = "1.0"
 argp = "0.4"
 crossterm = "0.29"
-enable-ansi-support = "0.2"
+enable-ansi-support = "0.3"
 memmap2 = "0.9"
 objdiff-core = { path = "../objdiff-core", features = ["all"] }
 prost = "0.14"
 ratatui = "0.29"
-rayon = "1.10"
+rayon = "1.11"
 serde = { version = "1.0", features = ["derive"] }
 serde_json = "1.0"
 supports-color = "3.0"
 time = { version = "0.3", features = ["formatting", "local-offset"] }
 tracing = "0.1"
 tracing-subscriber = { version = "0.3", features = ["env-filter"] }
-typed-path = "0.11"
+typed-path = "0.12"

 [target.'cfg(target_env = "musl")'.dependencies]
 mimalloc = "0.1"
--- a/objdiff-cli/src/views/function_diff.rs
+++ b/objdiff-cli/src/views/function_diff.rs
@@ -378,7 +378,6 @@ impl UiView for FunctionDiffUi {
                    }
                    // Reload
                    KeyCode::Char('r') => {
-                        result.redraw = true;
                        return EventControlFlow::Reload;
                    }
                    // Scroll right
@@ -400,7 +399,6 @@ impl UiView for FunctionDiffUi {
                                FunctionRelocDiffs::DataValue => FunctionRelocDiffs::All,
                                FunctionRelocDiffs::All => FunctionRelocDiffs::None,
                            };
-                        result.redraw = true;
                        return EventControlFlow::Reload;
                    }
                    // Toggle three-way diff
--- a/objdiff-core/Cargo.toml
+++ b/objdiff-core/Cargo.toml
@@ -135,10 +135,10 @@ num-traits = { version = "0.2", default-features = false, optional = true }
 object = { version = "0.37", default-features = false, features = ["read_core", "elf", "coff"] }
 pbjson = { version = "0.8", default-features = false, optional = true }
 prost = { version = "0.14", default-features = false, features = ["derive"], optional = true }
-regex = { version = "1.11", default-features = false, features = [], optional = true }
+regex = { version = "1.12", default-features = false, features = [], optional = true }
 serde = { version = "1.0", default-features = false, features = ["derive"], optional = true }
 similar = { git = "https://github.com/encounter/similar.git", branch = "no_std", default-features = false, features = ["hashbrown"], optional = true }
-typed-path = { version = "0.11", default-features = false, optional = true }
+typed-path = { version = "0.12", default-features = false, optional = true }

 # config
 globset = { version = "0.4", default-features = false, optional = true }
@@ -155,13 +155,13 @@ powerpc = { version = "0.4", optional = true }
 rlwinmdec = { version = "1.1", optional = true }

 # mips
-rabbitizer = { version = "2.0.0-alpha.4", default-features = false, features = ["all_extensions"], optional = true }
+rabbitizer = { version = "2.0.0-alpha.7", default-features = false, features = ["all_extensions"], optional = true }

 # x86
 iced-x86 = { version = "1.21", default-features = false, features = ["decoder", "intel", "gas", "masm", "nasm", "exhaustive_enums", "no_std"], optional = true }

 # arm
-unarm = { version = "1.9", optional = true }
+unarm = { version = "2.1", optional = true }
 arm-attr = { version = "0.2", optional = true }

 # arm64
@@ -169,17 +169,17 @@ yaxpeax-arch = { version = "0.3", default-features = false, optional = true }
 yaxpeax-arm = { version = "0.3", default-features = false, optional = true }

 # build
-notify = { version = "8.1.0", optional = true }
-notify-debouncer-full = { version = "0.5.0", optional = true }
+notify = { version = "8.2.0", optional = true }
+notify-debouncer-full = { version = "0.6.0", optional = true }
 shell-escape = { version = "0.1", optional = true }
-tempfile = { version = "3.20", optional = true }
+tempfile = { version = "3.23", optional = true }
 time = { version = "0.3", optional = true }
 encoding_rs = { version = "0.8.35", optional = true }

 # demangler
-cpp_demangle = { version = "0.4", optional = true, default-features = false, features = ["alloc"] }
+cpp_demangle = { version = "0.5", optional = true, default-features = false, features = ["alloc"] }
 cwdemangle = { version = "1.0", optional = true }
-gnuv2_demangle = { version = "0.1.0", optional = true }
+gnuv2_demangle = { version = "0.4", optional = true }
 msvc-demangler = { version = "0.11", optional = true }

 [target.'cfg(windows)'.dependencies]
--- a/objdiff-core/config-schema.json
+++ b/objdiff-core/config-schema.json
@@ -82,6 +82,27 @@
      "name": "Space between args",
      "description": "Adds a space between arguments in the diff output."
    },
+    {
+      "id": "showSymbolSizes",
+      "type": "choice",
+      "default": "off",
+      "name": "Show symbol sizes",
+      "description": "Shows symbol sizes in the symbol view.",
+      "items": [
+        {
+          "value": "off",
+          "name": "Off"
+        },
+        {
+          "value": "hex",
+          "name": "Hex"
+        },
+        {
+          "value": "decimal",
+          "name": "Decimal"
+        }
+      ]
+    },
    {
      "id": "combineDataSections",
      "type": "boolean",
@@ -107,20 +128,43 @@
          "value": "auto",
          "name": "Auto"
        },
+        {
+          "value": "v4",
+          "name": "ARMv4"
+        },
        {
          "value": "v4t",
          "name": "ARMv4T (GBA)"
        },
+        {
+          "value": "v5t",
+          "name": "ARMv5T"
+        },
        {
          "value": "v5te",
          "name": "ARMv5TE (DS)"
        },
+        {
+          "value": "v5tej",
+          "name": "ARMv5TEJ"
+        },
+        {
+          "value": "v6",
+          "name": "ARMv6"
+        },
        {
          "value": "v6k",
          "name": "ARMv6K (3DS)"
        }
      ]
    },
+    {
+      "id": "arm.vfpV2",
+      "type": "boolean",
+      "default": true,
+      "name": "VFPv2 instructions",
+      "description": "Adds floating-point instructions from VFPv2."
+    },
    {
      "id": "arm.unifiedSyntax",
      "type": "boolean",
@@ -296,6 +340,7 @@
      "properties": [
        "functionRelocDiffs",
        "demangler",
+        "showSymbolSizes",
        "spaceBetweenArgs",
        "combineDataSections",
        "combineTextSections"
@@ -306,6 +351,7 @@
      "name": "ARM",
      "properties": [
        "arm.archVersion",
+        "arm.vfpV2",
        "arm.unifiedSyntax",
        "arm.avRegisters",
        "arm.r9Usage",
--- a/objdiff-core/src/arch/arm.rs
+++ b/objdiff-core/src/arch/arm.rs
@@ -1,16 +1,17 @@
-use alloc::{collections::BTreeMap, format, string::ToString, vec::Vec};
+use alloc::{borrow::Cow, collections::BTreeMap, vec::Vec};
+use core::fmt::Write;

 use anyhow::{Result, bail};
 use arm_attr::{BuildAttrs, enums::CpuArch, tag::Tag};
 use object::{Endian as _, Object as _, ObjectSection as _, ObjectSymbol as _, elf};
-use unarm::{args, arm, thumb};
+use unarm::FormatValue as _;

 use crate::{
    arch::{Arch, OPCODE_DATA, OPCODE_INVALID, RelocationOverride, RelocationOverrideTarget},
    diff::{ArmArchVersion, ArmR9Usage, DiffObjConfig, display::InstructionPart},
    obj::{
-        InstructionRef, Relocation, RelocationFlags, ResolvedInstructionRef, ResolvedRelocation,
-        Section, SectionKind, Symbol, SymbolFlag, SymbolFlagSet, SymbolKind,
+        InstructionRef, Relocation, RelocationFlags, ResolvedInstructionRef, Section, SectionKind,
+        Symbol, SymbolFlag, SymbolFlagSet, SymbolKind,
    },
 };

@@ -18,7 +19,7 @@ use crate::{
 pub struct ArchArm {
    /// Maps section index, to list of disasm modes (arm, thumb or data) sorted by address
    disasm_modes: BTreeMap<usize, Vec<DisasmMode>>,
-    detected_version: Option<unarm::ArmVersion>,
+    detected_version: Option<unarm::Version>,
    endianness: object::Endianness,
 }

@@ -36,7 +37,7 @@ impl ArchArm {
        }
    }

-    fn elf_detect_arm_version(file: &object::File) -> Result<Option<unarm::ArmVersion>> {
+    fn elf_detect_arm_version(file: &object::File) -> Result<Option<unarm::Version>> {
        // Check ARM attributes
        if let Some(arm_attrs) = file.sections().find(|s| {
            s.kind() == object::SectionKind::Elf(elf::SHT_ARM_ATTRIBUTES)
@@ -57,9 +58,12 @@ impl ArchArm {
                    if let Tag::CpuArch(cpu_arch) = tag { Some(cpu_arch) } else { None }
                });
                match cpu_arch {
-                    Some(CpuArch::V4T) => return Ok(Some(unarm::ArmVersion::V4T)),
-                    Some(CpuArch::V5TE) => return Ok(Some(unarm::ArmVersion::V5Te)),
-                    Some(CpuArch::V6K) => return Ok(Some(unarm::ArmVersion::V6K)),
+                    Some(CpuArch::V4) => return Ok(Some(unarm::Version::V4)),
+                    Some(CpuArch::V4T) => return Ok(Some(unarm::Version::V4T)),
+                    Some(CpuArch::V5TE) => return Ok(Some(unarm::Version::V5Te)),
+                    Some(CpuArch::V5TEJ) => return Ok(Some(unarm::Version::V5Tej)),
+                    Some(CpuArch::V6) => return Ok(Some(unarm::Version::V6)),
+                    Some(CpuArch::V6K) => return Ok(Some(unarm::Version::V6K)),
                    Some(arch) => bail!("ARM arch {} not supported", arch),
                    None => {}
                };
@@ -89,31 +93,33 @@ impl ArchArm {
            .collect()
    }

-    fn parse_flags(&self, diff_config: &DiffObjConfig) -> unarm::ParseFlags {
-        unarm::ParseFlags {
-            ual: diff_config.arm_unified_syntax,
-            version: match diff_config.arm_arch_version {
-                ArmArchVersion::Auto => self.detected_version.unwrap_or(unarm::ArmVersion::V5Te),
-                ArmArchVersion::V4t => unarm::ArmVersion::V4T,
-                ArmArchVersion::V5te => unarm::ArmVersion::V5Te,
-                ArmArchVersion::V6k => unarm::ArmVersion::V6K,
-            },
+    fn unarm_options(&self, diff_config: &DiffObjConfig) -> unarm::Options {
+        let mut extensions = unarm::Extensions::none();
+        if diff_config.arm_vfp_v2 {
+            extensions = extensions.with(unarm::Extension::VfpV2);
        }
-    }
-
-    fn display_options(&self, diff_config: &DiffObjConfig) -> unarm::DisplayOptions {
-        unarm::DisplayOptions {
-            reg_names: unarm::RegNames {
-                av_registers: diff_config.arm_av_registers,
-                r9_use: match diff_config.arm_r9_usage {
-                    ArmR9Usage::GeneralPurpose => unarm::R9Use::GeneralPurpose,
-                    ArmR9Usage::Sb => unarm::R9Use::Pid,
-                    ArmR9Usage::Tr => unarm::R9Use::Tls,
-                },
-                explicit_stack_limit: diff_config.arm_sl_usage,
-                frame_pointer: diff_config.arm_fp_usage,
-                ip: diff_config.arm_ip_usage,
+        unarm::Options {
+            version: match diff_config.arm_arch_version {
+                ArmArchVersion::Auto => self.detected_version.unwrap_or(unarm::Version::V5Te),
+                ArmArchVersion::V4 => unarm::Version::V4,
+                ArmArchVersion::V4t => unarm::Version::V4T,
+                ArmArchVersion::V5t => unarm::Version::V5T,
+                ArmArchVersion::V5te => unarm::Version::V5Te,
+                ArmArchVersion::V5tej => unarm::Version::V5Tej,
+                ArmArchVersion::V6 => unarm::Version::V6,
+                ArmArchVersion::V6k => unarm::Version::V6K,
            },
+            extensions,
+            av: diff_config.arm_av_registers,
+            r9_use: match diff_config.arm_r9_usage {
+                ArmR9Usage::GeneralPurpose => unarm::R9Use::R9,
+                ArmR9Usage::Sb => unarm::R9Use::Sb,
+                ArmR9Usage::Tr => unarm::R9Use::Tr,
+            },
+            sl: diff_config.arm_sl_usage,
+            fp: diff_config.arm_fp_usage,
+            ip: diff_config.arm_ip_usage,
+            ual: diff_config.arm_unified_syntax,
        }
    }

@@ -122,32 +128,7 @@ impl ArchArm {
        ins_ref: InstructionRef,
        code: &[u8],
        diff_config: &DiffObjConfig,
-    ) -> Result<(unarm::Ins, unarm::ParsedIns)> {
-        if ins_ref.opcode == thumb::Opcode::BlH as u16 && ins_ref.size == 4 {
-            // Special case: combined thumb BL instruction
-            let parse_flags = self.parse_flags(diff_config);
-            let first_ins = thumb::Ins {
-                code: match self.endianness {
-                    object::Endianness::Little => u16::from_le_bytes([code[0], code[1]]),
-                    object::Endianness::Big => u16::from_be_bytes([code[0], code[1]]),
-                } as u32,
-                op: thumb::Opcode::BlH,
-            };
-            let second_ins = thumb::Ins::new(
-                match self.endianness {
-                    object::Endianness::Little => u16::from_le_bytes([code[2], code[3]]),
-                    object::Endianness::Big => u16::from_be_bytes([code[2], code[3]]),
-                } as u32,
-                &parse_flags,
-            );
-            let first_parsed = first_ins.parse(&parse_flags);
-            let second_parsed = second_ins.parse(&parse_flags);
-            return Ok((
-                unarm::Ins::Thumb(first_ins),
-                first_parsed.combine_thumb_bl(&second_parsed),
-            ));
-        }
-
+    ) -> Result<unarm::Ins> {
        let code = match (self.endianness, ins_ref.size) {
            (object::Endianness::Little, 2) => u16::from_le_bytes([code[0], code[1]]) as u32,
            (object::Endianness::Little, 4) => {
@@ -159,21 +140,24 @@ impl ArchArm {
            }
            _ => bail!("Invalid instruction size {}", ins_ref.size),
        };
-        let (ins, parsed_ins) = if ins_ref.opcode == OPCODE_DATA {
-            let mut args = args::Arguments::default();
-            args[0] = args::Argument::UImm(code);
-            let mnemonic = if ins_ref.size == 4 { ".word" } else { ".hword" };
-            (unarm::Ins::Data, unarm::ParsedIns { mnemonic, args })
-        } else if ins_ref.opcode & (1 << 15) != 0 {
-            let ins = arm::Ins { code, op: arm::Opcode::from(ins_ref.opcode as u8) };
-            let parsed = ins.parse(&self.parse_flags(diff_config));
-            (unarm::Ins::Arm(ins), parsed)
+
+        let thumb = ins_ref.opcode & (1 << 15) == 0;
+        let discriminant = ins_ref.opcode & !(1 << 15);
+        let pc = ins_ref.address as u32;
+        let options = self.unarm_options(diff_config);
+
+        let ins = if ins_ref.opcode == OPCODE_DATA {
+            match ins_ref.size {
+                4 => unarm::Ins::Word(code),
+                2 => unarm::Ins::HalfWord(code as u16),
+                _ => bail!("Invalid data size {}", ins_ref.size),
+            }
+        } else if thumb {
+            unarm::parse_thumb_with_discriminant(code, discriminant, pc, &options)
        } else {
-            let ins = thumb::Ins { code, op: thumb::Opcode::from(ins_ref.opcode as u8) };
-            let parsed = ins.parse(&self.parse_flags(diff_config));
-            (unarm::Ins::Thumb(ins), parsed)
+            unarm::parse_arm_with_discriminant(code, discriminant, pc, &options)
        };
-        Ok((ins, parsed_ins))
+        Ok(ins)
    }
 }

@@ -213,10 +197,11 @@ impl Arch for ArchArm {
            .take_while(|x| x.address < end_addr);
        let mut next_mapping = mappings_iter.next();

-        let ins_count = code.len() / mode.instruction_size(start_addr);
+        let min_ins_size = if mode == unarm::ParseMode::Thumb { 2 } else { 4 };
+        let ins_count = code.len() / min_ins_size;
        let mut ops = Vec::<InstructionRef>::with_capacity(ins_count);

-        let parse_flags = self.parse_flags(diff_config);
+        let options = self.unarm_options(diff_config);

        let mut address = start_addr;
        while address < end_addr {
@@ -226,9 +211,8 @@ impl Arch for ArchArm {
                next_mapping = mappings_iter.next();
            }

-            let mut ins_size = mode.instruction_size(address);
            let data = &code[(address - start_addr) as usize..];
-            if data.len() < ins_size {
+            if data.len() < min_ins_size {
                // Push the remainder as data
                ops.push(InstructionRef {
                    address: address as u64,
@@ -238,82 +222,80 @@ impl Arch for ArchArm {
                });
                break;
            }
-            let code = match (self.endianness, ins_size) {
-                (object::Endianness::Little, 2) => u16::from_le_bytes([data[0], data[1]]) as u32,
-                (object::Endianness::Little, 4) => {
-                    u32::from_le_bytes([data[0], data[1], data[2], data[3]])
-                }
-                (object::Endianness::Big, 2) => u16::from_be_bytes([data[0], data[1]]) as u32,
-                (object::Endianness::Big, 4) => {
-                    u32::from_be_bytes([data[0], data[1], data[2], data[3]])
-                }
-                _ => {
-                    // Invalid instruction size
-                    ops.push(InstructionRef {
-                        address: address as u64,
-                        size: ins_size as u8,
-                        opcode: OPCODE_INVALID,
-                        branch_dest: None,
-                    });
-                    address += ins_size as u32;
-                    continue;
+
+            // Check how many bytes we can/should read
+            let num_code_bytes = if data.len() >= 4 {
+                if mode == unarm::ParseMode::Data && address & 3 != 0 {
+                    // 32-bit .word value should be aligned on a 4-byte boundary, otherwise use .hword
+                    2
+                } else {
+                    // Read 4 bytes even for Thumb, as the parser will determine if it's a 2 or 4 byte instruction
+                    4
                }
+            } else if mode != unarm::ParseMode::Arm {
+                2
+            } else {
+                // Invalid instruction size
+                ops.push(InstructionRef {
+                    address: address as u64,
+                    size: min_ins_size as u8,
+                    opcode: OPCODE_INVALID,
+                    branch_dest: None,
+                });
+                address += min_ins_size as u32;
+                continue;
            };

-            let (opcode, branch_dest) = match mode {
-                unarm::ParseMode::Arm => {
-                    let ins = arm::Ins::new(code, &parse_flags);
-                    let opcode = ins.op as u16 | (1 << 15);
-                    let branch_dest = match ins.op {
-                        arm::Opcode::B | arm::Opcode::Bl => {
-                            address.checked_add_signed(ins.field_branch_offset())
+            let code = match num_code_bytes {
+                4 => match self.endianness {
+                    object::Endianness::Little => {
+                        u32::from_le_bytes([data[0], data[1], data[2], data[3]])
+                    }
+                    object::Endianness::Big => {
+                        if mode != unarm::ParseMode::Thumb {
+                            u32::from_be_bytes([data[0], data[1], data[2], data[3]])
+                        } else {
+                            // For 4-byte Thumb instructions, read two 16-bit halfwords in big endian
+                            u32::from_be_bytes([data[2], data[3], data[0], data[1]])
                        }
-                        arm::Opcode::BlxI => address.checked_add_signed(ins.field_blx_offset()),
-                        _ => None,
-                    };
-                    (opcode, branch_dest)
+                    }
+                },
+                2 => match self.endianness {
+                    object::Endianness::Little => u16::from_le_bytes([data[0], data[1]]) as u32,
+                    object::Endianness::Big => u16::from_be_bytes([data[0], data[1]]) as u32,
+                },
+                _ => unreachable!(),
+            };
+
+            let (opcode, ins, ins_size) = match mode {
+                unarm::ParseMode::Arm => {
+                    let ins = unarm::parse_arm(code, address, &options);
+                    let opcode = ins.discriminant() | (1 << 15);
+                    (opcode, ins, 4)
                }
                unarm::ParseMode::Thumb => {
-                    let ins = thumb::Ins::new(code, &parse_flags);
-                    let opcode = ins.op as u16;
-                    let branch_dest = match ins.op {
-                        thumb::Opcode::B | thumb::Opcode::Bl => {
-                            address.checked_add_signed(ins.field_branch_offset_8())
-                        }
-                        thumb::Opcode::BlH if data.len() >= 4 => {
-                            // Combine BL instructions
-                            let second_ins = thumb::Ins::new(
-                                match self.endianness {
-                                    object::Endianness::Little => {
-                                        u16::from_le_bytes([data[2], data[3]]) as u32
-                                    }
-                                    object::Endianness::Big => {
-                                        u16::from_be_bytes([data[2], data[3]]) as u32
-                                    }
-                                },
-                                &parse_flags,
-                            );
-                            if let Some(low) = match second_ins.op {
-                                thumb::Opcode::Bl => Some(second_ins.field_low_branch_offset_11()),
-                                thumb::Opcode::BlxI => Some(second_ins.field_low_blx_offset_11()),
-                                _ => None,
-                            } {
-                                ins_size = 4;
-                                address.checked_add_signed(
-                                    (ins.field_high_branch_offset_11() + (low as i32)) << 9 >> 9,
-                                )
-                            } else {
-                                None
-                            }
-                        }
-                        thumb::Opcode::BLong => {
-                            address.checked_add_signed(ins.field_branch_offset_11())
-                        }
-                        _ => None,
-                    };
-                    (opcode, branch_dest)
+                    let (ins, size) = unarm::parse_thumb(code, address, &options);
+                    let opcode = ins.discriminant();
+                    (opcode, ins, size)
                }
-                unarm::ParseMode::Data => (OPCODE_DATA, None),
+                unarm::ParseMode::Data => (
+                    OPCODE_DATA,
+                    if num_code_bytes == 4 {
+                        unarm::Ins::Word(code)
+                    } else {
+                        unarm::Ins::HalfWord(code as u16)
+                    },
+                    num_code_bytes,
+                ),
+            };
+
+            let branch_dest = match ins {
+                unarm::Ins::B { target, .. }
+                | unarm::Ins::Bl { target, .. }
+                | unarm::Ins::Blx { target: unarm::BlxTarget::Direct(target), .. } => {
+                    Some(target.addr)
+                }
+                _ => None,
            };

            ops.push(InstructionRef {
@@ -322,7 +304,7 @@ impl Arch for ArchArm {
                opcode,
                branch_dest: branch_dest.map(|x| x as u64),
            });
-            address += ins_size as u32;
+            address += ins_size;
        }

        Ok(ops)
@@ -334,20 +316,17 @@ impl Arch for ArchArm {
        diff_config: &DiffObjConfig,
        cb: &mut dyn FnMut(InstructionPart) -> Result<()>,
    ) -> Result<()> {
-        let (ins, parsed_ins) = self.parse_ins_ref(resolved.ins_ref, resolved.code, diff_config)?;
-        cb(InstructionPart::opcode(parsed_ins.mnemonic, resolved.ins_ref.opcode))?;
-        if ins == unarm::Ins::Data && resolved.relocation.is_some() {
-            cb(InstructionPart::reloc())?;
-        } else {
-            push_args(
-                ins,
-                &parsed_ins,
-                resolved.relocation,
-                resolved.ins_ref.address as u32,
-                self.display_options(diff_config),
-                cb,
-            )?;
-        }
+        let ins = self.parse_ins_ref(resolved.ins_ref, resolved.code, diff_config)?;
+
+        let options = self.unarm_options(diff_config);
+        let mut string_fmt = unarm::StringFormatter::new(&options);
+        ins.write_opcode(&mut string_fmt)?;
+        let opcode = string_fmt.into_string();
+        cb(InstructionPart::opcode(opcode, resolved.ins_ref.opcode))?;
+
+        let mut args_formatter =
+            ArgsFormatter { options: &options, cb, resolved: &resolved, skip_leading_space: true };
+        ins.write_params(&mut args_formatter)?;
        Ok(())
    }

@@ -495,203 +474,133 @@ impl DisasmMode {
    }
 }

-fn push_args(
-    ins: unarm::Ins,
-    parsed_ins: &unarm::ParsedIns,
-    relocation: Option<ResolvedRelocation>,
-    cur_addr: u32,
-    display_options: unarm::DisplayOptions,
-    mut arg_cb: impl FnMut(InstructionPart) -> Result<()>,
-) -> Result<()> {
-    let reloc_arg = find_reloc_arg(parsed_ins, relocation);
-    let mut writeback = false;
-    let mut deref = false;
-    for (i, &arg) in parsed_ins.args_iter().enumerate() {
-        // Emit punctuation before separator
-        if deref {
-            match arg {
-                args::Argument::OffsetImm(args::OffsetImm { post_indexed: true, value: _ })
-                | args::Argument::OffsetReg(args::OffsetReg {
-                    add: _,
-                    post_indexed: true,
-                    reg: _,
-                })
-                | args::Argument::CoOption(_) => {
-                    deref = false;
-                    arg_cb(InstructionPart::basic("]"))?;
-                    if writeback {
-                        writeback = false;
-                        arg_cb(InstructionPart::opaque("!"))?;
-                    }
+pub struct ArgsFormatter<'a> {
+    options: &'a unarm::Options,
+    cb: &'a mut dyn FnMut(InstructionPart) -> Result<()>,
+    resolved: &'a ResolvedInstructionRef<'a>,
+    skip_leading_space: bool,
+}
+
+impl ArgsFormatter<'_> {
+    fn write(&mut self, part: InstructionPart) -> core::fmt::Result {
+        (self.cb)(part).map_err(|_| core::fmt::Error)
+    }
+
+    fn write_opaque<F>(&mut self, value: F) -> core::fmt::Result
+    where F: unarm::FormatValue {
+        let mut string_fmt = unarm::StringFormatter::new(self.options);
+        value.write(&mut string_fmt)?;
+        self.write(InstructionPart::opaque(string_fmt.into_string()))?;
+        Ok(())
+    }
+}
+
+impl Write for ArgsFormatter<'_> {
+    fn write_str(&mut self, s: &str) -> core::fmt::Result { self.write(InstructionPart::basic(s)) }
+}
+
+impl unarm::FormatIns for ArgsFormatter<'_> {
+    fn options(&self) -> &unarm::Options { self.options }
+
+    fn write_ins(&mut self, ins: &unarm::Ins) -> core::fmt::Result {
+        let mut string_fmt = unarm::StringFormatter::new(self.options);
+        ins.write_opcode(&mut string_fmt)?;
+        let opcode = string_fmt.into_string();
+        self.write(InstructionPart::Opcode(Cow::Owned(opcode), self.resolved.ins_ref.opcode))?;
+        ins.write_params(self)
+    }
+
+    fn write_space(&mut self) -> core::fmt::Result {
+        if self.skip_leading_space {
+            self.skip_leading_space = false;
+            Ok(())
+        } else {
+            self.write_str(" ")
+        }
+    }
+
+    fn write_separator(&mut self) -> core::fmt::Result { self.write(InstructionPart::separator()) }
+
+    fn write_uimm(&mut self, uimm: u32) -> core::fmt::Result {
+        if let Some(resolved) = self.resolved.relocation
+            && let RelocationFlags::Elf(elf::R_ARM_ABS32) = resolved.relocation.flags
+        {
+            return self.write(InstructionPart::reloc());
+        }
+        self.write(InstructionPart::unsigned(uimm))
+    }
+
+    fn write_simm(&mut self, simm: i32) -> core::fmt::Result {
+        self.write(InstructionPart::signed(simm))
+    }
+
+    fn write_branch_target(&mut self, branch_target: unarm::BranchTarget) -> core::fmt::Result {
+        if let Some(resolved) = self.resolved.relocation {
+            match resolved.relocation.flags {
+                RelocationFlags::Elf(elf::R_ARM_THM_XPC22)
+                | RelocationFlags::Elf(elf::R_ARM_THM_PC22)
+                | RelocationFlags::Elf(elf::R_ARM_PC24)
+                | RelocationFlags::Elf(elf::R_ARM_XPC25)
+                | RelocationFlags::Elf(elf::R_ARM_CALL) => {
+                    return self.write(InstructionPart::reloc());
                }
                _ => {}
            }
        }
-
-        if i > 0 {
-            arg_cb(InstructionPart::separator())?;
-        }
-
-        if reloc_arg == Some(i) {
-            arg_cb(InstructionPart::reloc())?;
-        } else {
-            match arg {
-                args::Argument::None => {}
-                args::Argument::Reg(reg) => {
-                    if reg.deref {
-                        deref = true;
-                        arg_cb(InstructionPart::basic("["))?;
-                    }
-                    arg_cb(InstructionPart::opaque(
-                        reg.reg.display(display_options.reg_names).to_string(),
-                    ))?;
-                    if reg.writeback {
-                        if reg.deref {
-                            writeback = true;
-                        } else {
-                            arg_cb(InstructionPart::opaque("!"))?;
-                        }
-                    }
-                }
-                args::Argument::RegList(reg_list) => {
-                    arg_cb(InstructionPart::basic("{"))?;
-                    let mut first = true;
-                    for i in 0..16 {
-                        if (reg_list.regs & (1 << i)) != 0 {
-                            if !first {
-                                arg_cb(InstructionPart::separator())?;
-                            }
-                            arg_cb(InstructionPart::opaque(
-                                args::Register::parse(i)
-                                    .display(display_options.reg_names)
-                                    .to_string(),
-                            ))?;
-                            first = false;
-                        }
-                    }
-                    arg_cb(InstructionPart::basic("}"))?;
-                    if reg_list.user_mode {
-                        arg_cb(InstructionPart::opaque("^"))?;
-                    }
-                }
-                args::Argument::UImm(value)
-                | args::Argument::CoOpcode(value)
-                | args::Argument::SatImm(value) => {
-                    arg_cb(InstructionPart::basic("#"))?;
-                    arg_cb(InstructionPart::unsigned(value))?;
-                }
-                args::Argument::SImm(value)
-                | args::Argument::OffsetImm(args::OffsetImm { post_indexed: _, value }) => {
-                    arg_cb(InstructionPart::basic("#"))?;
-                    arg_cb(InstructionPart::signed(value))?;
-                }
-                args::Argument::BranchDest(value) => {
-                    arg_cb(InstructionPart::branch_dest(cur_addr.wrapping_add_signed(value)))?;
-                }
-                args::Argument::CoOption(value) => {
-                    arg_cb(InstructionPart::basic("{"))?;
-                    arg_cb(InstructionPart::unsigned(value))?;
-                    arg_cb(InstructionPart::basic("}"))?;
-                }
-                args::Argument::CoprocNum(value) => {
-                    arg_cb(InstructionPart::opaque(format!("p{value}")))?;
-                }
-                args::Argument::ShiftImm(shift) => {
-                    arg_cb(InstructionPart::opaque(shift.op.to_string()))?;
-                    arg_cb(InstructionPart::basic(" #"))?;
-                    arg_cb(InstructionPart::unsigned(shift.imm))?;
-                }
-                args::Argument::ShiftReg(shift) => {
-                    arg_cb(InstructionPart::opaque(shift.op.to_string()))?;
-                    arg_cb(InstructionPart::basic(" "))?;
-                    arg_cb(InstructionPart::opaque(
-                        shift.reg.display(display_options.reg_names).to_string(),
-                    ))?;
-                }
-                args::Argument::OffsetReg(offset) => {
-                    if !offset.add {
-                        arg_cb(InstructionPart::basic("-"))?;
-                    }
-                    arg_cb(InstructionPart::opaque(
-                        offset.reg.display(display_options.reg_names).to_string(),
-                    ))?;
-                }
-                args::Argument::CpsrMode(mode) => {
-                    arg_cb(InstructionPart::basic("#"))?;
-                    arg_cb(InstructionPart::unsigned(mode.mode))?;
-                    if mode.writeback {
-                        arg_cb(InstructionPart::opaque("!"))?;
-                    }
-                }
-                args::Argument::CoReg(_)
-                | args::Argument::StatusReg(_)
-                | args::Argument::StatusMask(_)
-                | args::Argument::Shift(_)
-                | args::Argument::CpsrFlags(_)
-                | args::Argument::Endian(_) => {
-                    arg_cb(InstructionPart::opaque(
-                        arg.display(display_options, None).to_string(),
-                    ))?;
-                }
-            }
-        }
-    }
-    if deref {
-        arg_cb(InstructionPart::basic("]"))?;
-        if writeback {
-            arg_cb(InstructionPart::opaque("!"))?;
-        }
+        self.write(InstructionPart::branch_dest(branch_target.addr))
    }

-    let branch_dest = get_pc_relative_load_address(ins, cur_addr);
-    if let Some(branch_dest) = branch_dest {
-        arg_cb(InstructionPart::basic(" (->"))?;
-        arg_cb(InstructionPart::branch_dest(branch_dest))?;
-        arg_cb(InstructionPart::basic(")"))?;
+    fn write_reg(&mut self, reg: unarm::Reg) -> core::fmt::Result { self.write_opaque(reg) }
+
+    fn write_status_reg(&mut self, status_reg: unarm::StatusReg) -> core::fmt::Result {
+        self.write_opaque(status_reg)
    }

-    Ok(())
-}
-
-fn find_reloc_arg(
-    parsed_ins: &unarm::ParsedIns,
-    relocation: Option<ResolvedRelocation>,
-) -> Option<usize> {
-    if let Some(resolved) = relocation {
-        match resolved.relocation.flags {
-            // Calls
-            RelocationFlags::Elf(elf::R_ARM_THM_XPC22)
-            | RelocationFlags::Elf(elf::R_ARM_THM_PC22)
-            | RelocationFlags::Elf(elf::R_ARM_PC24)
-            | RelocationFlags::Elf(elf::R_ARM_XPC25)
-            | RelocationFlags::Elf(elf::R_ARM_CALL) => {
-                parsed_ins.args.iter().rposition(|a| matches!(a, args::Argument::BranchDest(_)))
-            }
-            // Data
-            RelocationFlags::Elf(elf::R_ARM_ABS32) => {
-                parsed_ins.args.iter().rposition(|a| matches!(a, args::Argument::UImm(_)))
-            }
-            _ => None,
-        }
-    } else {
-        None
+    fn write_status_fields(&mut self, status_fields: unarm::StatusFields) -> core::fmt::Result {
+        self.write_opaque(status_fields)
    }
-}

-fn get_pc_relative_load_address(ins: unarm::Ins, address: u32) -> Option<u32> {
-    match ins {
-        unarm::Ins::Arm(ins)
-            if ins.op == arm::Opcode::Ldr
-                && ins.modifier_addr_ldr_str() == arm::AddrLdrStr::Imm
-                && ins.field_rn_deref().reg == args::Register::Pc =>
+    fn write_shift_op(&mut self, shift_op: unarm::ShiftOp) -> core::fmt::Result {
+        self.write_opaque(shift_op)
+    }
+
+    fn write_coproc(&mut self, coproc: unarm::Coproc) -> core::fmt::Result {
+        self.write_opaque(coproc)
+    }
+
+    fn write_co_reg(&mut self, co_reg: unarm::CoReg) -> core::fmt::Result {
+        self.write_opaque(co_reg)
+    }
+
+    fn write_aif_flags(&mut self, aif_flags: unarm::AifFlags) -> core::fmt::Result {
+        self.write_opaque(aif_flags)
+    }
+
+    fn write_endianness(&mut self, endianness: unarm::Endianness) -> core::fmt::Result {
+        self.write_opaque(endianness)
+    }
+
+    fn write_sreg(&mut self, sreg: unarm::Sreg) -> core::fmt::Result { self.write_opaque(sreg) }
+
+    fn write_dreg(&mut self, dreg: unarm::Dreg) -> core::fmt::Result { self.write_opaque(dreg) }
+
+    fn write_fpscr(&mut self, fpscr: unarm::Fpscr) -> core::fmt::Result { self.write_opaque(fpscr) }
+
+    fn write_addr_ldr_str(&mut self, addr_ldr_str: unarm::AddrLdrStr) -> core::fmt::Result {
+        addr_ldr_str.write(self)?;
+        if let unarm::AddrLdrStr::Pre {
+            rn: unarm::Reg::Pc,
+            offset: unarm::LdrStrOffset::Imm(offset),
+            ..
+        } = addr_ldr_str
        {
-            let offset = ins.field_offset_12().value;
-            Some(address.wrapping_add_signed(offset + 8))
+            let thumb = self.resolved.ins_ref.opcode & (1 << 15) == 0;
+            let pc_offset = if thumb { 4 } else { 8 };
+            let pc = (self.resolved.ins_ref.address as u32 & !3) + pc_offset;
+            self.write(InstructionPart::basic(" (->"))?;
+            self.write(InstructionPart::branch_dest(pc.wrapping_add(offset as u32)))?;
+            self.write(InstructionPart::basic(")"))?;
        }
-        unarm::Ins::Thumb(ins) if ins.op == thumb::Opcode::LdrPc => {
-            let offset = ins.field_rel_immed_8().value;
-            Some((address & !3).wrapping_add_signed(offset + 4))
-        }
-        _ => None,
+        Ok(())
    }
 }
--- a/objdiff-core/src/arch/mips.rs
+++ b/objdiff-core/src/arch/mips.rs
@@ -293,6 +293,7 @@ impl Arch for ArchMips {
                        }
                        elf::R_MIPS_PC16 => 0, // PC-relative relocation
                        R_MIPS15_S3 => ((code & 0x001FFFC0) >> 3) as i64,
+                        elf::R_MIPS_GPREL32 => (code as i32 as i64) + self.ri_gp_value as i64,
                        flags => bail!("Unsupported MIPS implicit relocation {flags:?}"),
                    };
                    Ok(Some(RelocationOverride { target: RelocationOverrideTarget::Keep, addend }))
@@ -318,6 +319,7 @@ impl Arch for ArchMips {
                elf::R_MIPS_GOT16 => Some("R_MIPS_GOT16"),
                elf::R_MIPS_PC16 => Some("R_MIPS_PC16"),
                elf::R_MIPS_CALL16 => Some("R_MIPS_CALL16"),
+                elf::R_MIPS_GPREL32 => Some("R_MIPS_GPREL32"),
                R_MIPS15_S3 => Some("R_MIPS15_S3"),
                _ => None,
            },
--- a/objdiff-core/src/diff/data.rs
+++ b/objdiff-core/src/diff/data.rs
@@ -37,12 +37,13 @@ pub fn diff_bss_symbol(

 pub fn symbol_name_matches(left_name: &str, right_name: &str) -> bool {
    // Match Metrowerks symbol$1234 against symbol$2345
-    if let Some((prefix, suffix)) = left_name.split_once('$') {
+    // and GCC symbol.1234 against symbol.2345
+    if let Some((prefix, suffix)) = left_name.split_once(['$', '.']) {
        if !suffix.chars().all(char::is_numeric) {
            return false;
        }
        right_name
-            .split_once('$')
+            .split_once(['$', '.'])
            .is_some_and(|(p, s)| p == prefix && s.chars().all(char::is_numeric))
    } else {
        left_name == right_name
--- a/objdiff-core/src/diff/demangler.rs
+++ b/objdiff-core/src/diff/demangler.rs
@@ -34,14 +34,12 @@ impl Demangler {

    fn demangle_itanium(name: &str) -> Option<String> {
        let name = name.trim_start_matches('.');
-        cpp_demangle::Symbol::new(name)
-            .ok()
-            .and_then(|s| s.demangle(&cpp_demangle::DemangleOptions::default()).ok())
+        cpp_demangle::Symbol::new(name).ok().and_then(|s| s.demangle().ok())
    }

    fn demangle_gnu_legacy(name: &str) -> Option<String> {
        let name = name.trim_start_matches('.');
-        gnuv2_demangle::demangle(name, &gnuv2_demangle::DemangleConfig::new_no_cfilt_mimics()).ok()
+        gnuv2_demangle::demangle(name, &gnuv2_demangle::DemangleConfig::new()).ok()
    }
 }

--- a/objdiff-core/src/obj/mdebug.rs
+++ b/objdiff-core/src/obj/mdebug.rs
@@ -0,0 +1,401 @@
+use alloc::vec::Vec;
+
+use anyhow::{Context, Result, bail, ensure};
+use object::{Endianness, Object, ObjectSection};
+
+use super::{Section, SectionKind};
+
+const HDRR_SIZE: usize = 0x60;
+const FDR_SIZE: usize = 0x48;
+const PDR_SIZE: usize = 0x34;
+const SYMR_SIZE: usize = 0x0c;
+
+const ST_PROC: u8 = 6;
+const ST_STATICPROC: u8 = 14;
+const ST_END: u8 = 8;
+
+pub(super) fn parse_line_info_mdebug(
+    obj_file: &object::File,
+    sections: &mut [Section],
+) -> Result<()> {
+    let Some(section) = obj_file.section_by_name(".mdebug") else {
+        return Ok(());
+    };
+
+    let data = section.data().context("failed to read .mdebug contents")?;
+    if data.len() < HDRR_SIZE {
+        return Ok(());
+    }
+
+    let section_file_offset = section.file_range().map(|(offset, _)| offset as usize);
+
+    let endianness = obj_file.endianness();
+    let header = Header::parse(data, endianness)?;
+
+    let symbols_data = slice_at(
+        data,
+        header.cb_sym_offset,
+        header.isym_max.checked_mul(SYMR_SIZE as u32).context("symbol table size overflow")?,
+        section_file_offset,
+    )?;
+    let symbols = parse_symbols(symbols_data, endianness)?;
+
+    let fdr_data = slice_at(
+        data,
+        header.cb_fd_offset,
+        header
+            .ifd_max
+            .checked_mul(FDR_SIZE as u32)
+            .context("file descriptor table size overflow")?,
+        section_file_offset,
+    )?;
+
+    for fdr_index in 0..header.ifd_max as usize {
+        let fdr_offset = fdr_index * FDR_SIZE;
+        let fdr = FileDescriptor::parse(&fdr_data[fdr_offset..fdr_offset + FDR_SIZE], endianness)?;
+        if fdr.cpd == 0 || fdr.csym == 0 {
+            continue;
+        }
+
+        let sym_base = fdr.isym_base as usize;
+        let sym_end = sym_base + fdr.csym as usize;
+        if sym_end > symbols.len() {
+            continue;
+        }
+
+        let Some(line_file_offset) = header.cb_line_offset.checked_add(fdr.cb_line_offset) else {
+            continue;
+        };
+        let Some(line_file_base) =
+            resolve_offset(line_file_offset, data.len(), section_file_offset)
+        else {
+            continue;
+        };
+        let Some(line_file_end) = line_file_base.checked_add(fdr.cb_line as usize) else {
+            continue;
+        };
+        if line_file_end > data.len() {
+            continue;
+        }
+
+        for local_proc_index in 0..fdr.cpd as usize {
+            let pdr_index = fdr.ipd_first as usize + local_proc_index;
+            let pdr_offset = header
+                .cb_pd_offset
+                .checked_add((pdr_index as u32) * PDR_SIZE as u32)
+                .context("procedure descriptor offset overflow")?;
+            let pdr_data = match slice_at(data, pdr_offset, PDR_SIZE as u32, section_file_offset) {
+                Ok(data) => data,
+                Err(_) => continue,
+            };
+            let pdr = ProcDescriptor::parse(pdr_data, endianness)?;
+            if pdr.isym as usize >= fdr.csym as usize {
+                continue;
+            }
+            let global_sym_index = sym_base + pdr.isym as usize;
+            let Some(start_symbol) = symbols.get(global_sym_index) else {
+                continue;
+            };
+            if start_symbol.st != ST_PROC && start_symbol.st != ST_STATICPROC {
+                continue;
+            }
+
+            let local_index = pdr.isym as u32;
+            let mut end_address = None;
+            for sym in &symbols[global_sym_index..sym_end] {
+                if sym.st == ST_END && sym.index == local_index {
+                    end_address = Some(sym.value);
+                    break;
+                }
+            }
+            let Some(end_address) = end_address else {
+                continue;
+            };
+            let Some(size) = end_address.checked_sub(start_symbol.value) else {
+                continue;
+            };
+            if size == 0 || size % 4 != 0 {
+                continue;
+            }
+            let word_count = (size / 4) as usize;
+            if word_count == 0 {
+                continue;
+            }
+
+            let Some(mut cursor) = line_file_base.checked_add(pdr.cb_line_offset as usize) else {
+                continue;
+            };
+            if cursor >= line_file_end {
+                continue;
+            }
+
+            let mut line_number = pdr.ln_low as i32;
+            let mut lines = Vec::with_capacity(word_count);
+            while lines.len() < word_count && cursor < line_file_end {
+                let b0 = data[cursor];
+                cursor += 1;
+                let count = (b0 & 0x0f) as usize + 1;
+                let delta = decode_delta(endianness, b0 >> 4, data, &mut cursor, line_file_end)?;
+                line_number = line_number.wrapping_add(delta as i32);
+                for _ in 0..count {
+                    if lines.len() == word_count {
+                        break;
+                    }
+                    lines.push(line_number);
+                }
+            }
+
+            if lines.len() != word_count {
+                continue;
+            }
+
+            assign_lines(sections, fdr.adr as u64 + pdr.addr as u64, &lines);
+        }
+    }
+
+    Ok(())
+}
+
+fn assign_lines(sections: &mut [Section], base_address: u64, lines: &[i32]) {
+    let mut address = base_address;
+    for &line in lines {
+        if line >= 0
+            && let Some(section) = find_code_section(sections, address)
+        {
+            section.line_info.insert(address, line as u32);
+        }
+        address = address.wrapping_add(4);
+    }
+}
+
+fn find_code_section(sections: &mut [Section], address: u64) -> Option<&mut Section> {
+    sections.iter_mut().find(|section| {
+        section.kind == SectionKind::Code
+            && address >= section.address
+            && address < section.address + section.size
+    })
+}
+
+fn decode_delta(
+    endianness: Endianness,
+    nibble: u8,
+    data: &[u8],
+    cursor: &mut usize,
+    end: usize,
+) -> Result<i32> {
+    if nibble == 8 {
+        ensure!(*cursor + 2 <= end, "extended delta out of range");
+        let bytes: [u8; 2] = data[*cursor..*cursor + 2].try_into().unwrap();
+        *cursor += 2;
+        Ok(match endianness {
+            Endianness::Big => i16::from_be_bytes(bytes) as i32,
+            Endianness::Little => i16::from_le_bytes(bytes) as i32,
+        })
+    } else {
+        let mut value = (nibble & 0x0f) as i32;
+        if value & 0x8 != 0 {
+            value -= 0x10;
+        }
+        Ok(value)
+    }
+}
+
+fn slice_at(
+    data: &[u8],
+    offset: u32,
+    size: u32,
+    section_file_offset: Option<usize>,
+) -> Result<&[u8]> {
+    let size = size as usize;
+    if size == 0 {
+        ensure!(
+            resolve_offset(offset, data.len(), section_file_offset).is_some(),
+            "offset outside of .mdebug section"
+        );
+        return Ok(&data[0..0]);
+    }
+    let Some(offset) = resolve_offset(offset, data.len(), section_file_offset) else {
+        bail!("offset outside of .mdebug section");
+    };
+    let end = offset.checked_add(size).context("range overflow")?;
+    ensure!(end <= data.len(), "range exceeds .mdebug size");
+    Ok(&data[offset..end])
+}
+
+fn resolve_offset(
+    offset: u32,
+    data_len: usize,
+    section_file_offset: Option<usize>,
+) -> Option<usize> {
+    let offset = offset as usize;
+    if offset <= data_len {
+        Some(offset)
+    } else if let Some(file_offset) = section_file_offset {
+        offset.checked_sub(file_offset).filter(|rel| *rel <= data_len)
+    } else {
+        None
+    }
+}
+
+#[derive(Clone, Copy)]
+struct Header {
+    cb_line_offset: u32,
+    cb_pd_offset: u32,
+    cb_sym_offset: u32,
+    cb_fd_offset: u32,
+    isym_max: u32,
+    ifd_max: u32,
+}
+
+impl Header {
+    fn parse(data: &[u8], endianness: Endianness) -> Result<Self> {
+        ensure!(HDRR_SIZE <= data.len(), ".mdebug header truncated");
+        let mut cursor = 0;
+        let magic = read_u16(data, &mut cursor, endianness)?;
+        let _vstamp = read_u16(data, &mut cursor, endianness)?;
+        ensure!(magic == 0x7009, "unexpected .mdebug magic: {magic:#x}");
+        let _iline_max = read_u32(data, &mut cursor, endianness)?;
+        let _cb_line = read_u32(data, &mut cursor, endianness)?;
+        let cb_line_offset = read_u32(data, &mut cursor, endianness)?;
+        let _idn_max = read_u32(data, &mut cursor, endianness)?;
+        let _cb_dn_offset = read_u32(data, &mut cursor, endianness)?;
+        let _ipd_max = read_u32(data, &mut cursor, endianness)?;
+        let cb_pd_offset = read_u32(data, &mut cursor, endianness)?;
+        let isym_max = read_u32(data, &mut cursor, endianness)?;
+        let cb_sym_offset = read_u32(data, &mut cursor, endianness)?;
+        let _iopt_max = read_u32(data, &mut cursor, endianness)?;
+        let _cb_opt_offset = read_u32(data, &mut cursor, endianness)?;
+        let _iaux_max = read_u32(data, &mut cursor, endianness)?;
+        let _cb_aux_offset = read_u32(data, &mut cursor, endianness)?;
+        let _iss_max = read_u32(data, &mut cursor, endianness)?;
+        let _cb_ss_offset = read_u32(data, &mut cursor, endianness)?;
+        let _iss_ext_max = read_u32(data, &mut cursor, endianness)?;
+        let _cb_ss_ext_offset = read_u32(data, &mut cursor, endianness)?;
+        let ifd_max = read_u32(data, &mut cursor, endianness)?;
+        let cb_fd_offset = read_u32(data, &mut cursor, endianness)?;
+        let _crfd = read_u32(data, &mut cursor, endianness)?;
+        let _cb_rfd_offset = read_u32(data, &mut cursor, endianness)?;
+        let _iext_max = read_u32(data, &mut cursor, endianness)?;
+        let _cb_ext_offset = read_u32(data, &mut cursor, endianness)?;
+
+        Ok(Header { cb_line_offset, cb_pd_offset, cb_sym_offset, cb_fd_offset, isym_max, ifd_max })
+    }
+}
+
+#[derive(Clone, Copy)]
+struct FileDescriptor {
+    adr: u32,
+    isym_base: u32,
+    csym: u32,
+    ipd_first: u16,
+    cpd: u16,
+    cb_line_offset: u32,
+    cb_line: u32,
+}
+
+impl FileDescriptor {
+    fn parse(data: &[u8], endianness: Endianness) -> Result<Self> {
+        ensure!(data.len() >= FDR_SIZE, "FDR truncated");
+        let mut cursor = 0;
+        let adr = read_u32(data, &mut cursor, endianness)?;
+        let _rss = read_u32(data, &mut cursor, endianness)?;
+        let _iss_base = read_u32(data, &mut cursor, endianness)?;
+        let _cb_ss = read_u32(data, &mut cursor, endianness)?;
+        let isym_base = read_u32(data, &mut cursor, endianness)?;
+        let csym = read_u32(data, &mut cursor, endianness)?;
+        let _iline_base = read_u32(data, &mut cursor, endianness)?;
+        let _cline = read_u32(data, &mut cursor, endianness)?;
+        let _iopt_base = read_u32(data, &mut cursor, endianness)?;
+        let _copt = read_u32(data, &mut cursor, endianness)?;
+        let ipd_first = read_u16(data, &mut cursor, endianness)?;
+        let cpd = read_u16(data, &mut cursor, endianness)?;
+        let _iaux_base = read_u32(data, &mut cursor, endianness)?;
+        let _caux = read_u32(data, &mut cursor, endianness)?;
+        let _rfd_base = read_u32(data, &mut cursor, endianness)?;
+        let _crfd = read_u32(data, &mut cursor, endianness)?;
+        let _bits = read_u32(data, &mut cursor, endianness)?;
+        let cb_line_offset = read_u32(data, &mut cursor, endianness)?;
+        let cb_line = read_u32(data, &mut cursor, endianness)?;
+
+        Ok(FileDescriptor { adr, isym_base, csym, ipd_first, cpd, cb_line_offset, cb_line })
+    }
+}
+
+#[derive(Clone, Copy)]
+struct ProcDescriptor {
+    addr: u32,
+    isym: u32,
+    ln_low: i32,
+    cb_line_offset: u32,
+}
+
+impl ProcDescriptor {
+    fn parse(data: &[u8], endianness: Endianness) -> Result<Self> {
+        ensure!(data.len() >= PDR_SIZE, "PDR truncated");
+        let mut cursor = 0;
+        let addr = read_u32(data, &mut cursor, endianness)?;
+        let isym = read_u32(data, &mut cursor, endianness)?;
+        let _iline = read_u32(data, &mut cursor, endianness)?;
+        let _regmask = read_u32(data, &mut cursor, endianness)?;
+        let _regoffset = read_u32(data, &mut cursor, endianness)?;
+        let _iopt = read_u32(data, &mut cursor, endianness)?;
+        let _fregmask = read_u32(data, &mut cursor, endianness)?;
+        let _fregoffset = read_u32(data, &mut cursor, endianness)?;
+        let _frameoffset = read_u32(data, &mut cursor, endianness)?;
+        let _framereg = read_u16(data, &mut cursor, endianness)?;
+        let _pcreg = read_u16(data, &mut cursor, endianness)?;
+        let ln_low = read_i32(data, &mut cursor, endianness)?;
+        let _ln_high = read_i32(data, &mut cursor, endianness)?;
+        let cb_line_offset = read_u32(data, &mut cursor, endianness)?;
+
+        Ok(ProcDescriptor { addr, isym, ln_low, cb_line_offset })
+    }
+}
+
+#[derive(Clone, Copy)]
+struct SymbolEntry {
+    value: u32,
+    st: u8,
+    index: u32,
+}
+
+fn parse_symbols(data: &[u8], endianness: Endianness) -> Result<Vec<SymbolEntry>> {
+    ensure!(data.len().is_multiple_of(SYMR_SIZE), "symbol table misaligned");
+    let mut symbols = Vec::with_capacity(data.len() / SYMR_SIZE);
+    let mut cursor = 0;
+    while cursor + SYMR_SIZE <= data.len() {
+        let _iss = read_u32(data, &mut cursor, endianness)?;
+        let value = read_u32(data, &mut cursor, endianness)?;
+        let bits = read_u32(data, &mut cursor, endianness)?;
+        let (st, index) = match endianness {
+            Endianness::Big => (((bits >> 26) & 0x3f) as u8, bits & 0x000f_ffff),
+            Endianness::Little => (((bits & 0x3f) as u8), (bits >> 12) & 0x000f_ffff),
+        };
+        symbols.push(SymbolEntry { value, st, index });
+    }
+    Ok(symbols)
+}
+
+fn read_u16(data: &[u8], cursor: &mut usize, endianness: Endianness) -> Result<u16> {
+    ensure!(*cursor + 2 <= data.len(), "unexpected EOF while reading u16");
+    let bytes: [u8; 2] = data[*cursor..*cursor + 2].try_into().unwrap();
+    *cursor += 2;
+    Ok(match endianness {
+        Endianness::Big => u16::from_be_bytes(bytes),
+        Endianness::Little => u16::from_le_bytes(bytes),
+    })
+}
+
+fn read_u32(data: &[u8], cursor: &mut usize, endianness: Endianness) -> Result<u32> {
+    ensure!(*cursor + 4 <= data.len(), "unexpected EOF while reading u32");
+    let bytes: [u8; 4] = data[*cursor..*cursor + 4].try_into().unwrap();
+    *cursor += 4;
+    Ok(match endianness {
+        Endianness::Big => u32::from_be_bytes(bytes),
+        Endianness::Little => u32::from_le_bytes(bytes),
+    })
+}
+
+fn read_i32(data: &[u8], cursor: &mut usize, endianness: Endianness) -> Result<i32> {
+    Ok(read_u32(data, cursor, endianness)? as i32)
+}
--- a/objdiff-core/src/obj/mod.rs
+++ b/objdiff-core/src/obj/mod.rs
@@ -1,5 +1,6 @@
 #[cfg(feature = "dwarf")]
 mod dwarf2;
+mod mdebug;
 pub mod read;
 pub mod split_meta;

--- a/objdiff-core/src/obj/read.rs
+++ b/objdiff-core/src/obj/read.rs
@@ -654,6 +654,10 @@ fn parse_line_info(
        log::warn!("Failed to parse COFF line info: {e}");
    }

+    if let Err(e) = super::mdebug::parse_line_info_mdebug(obj_file, sections) {
+        log::warn!("Failed to parse MIPS mdebug line info: {e}");
+    }
+
    Ok(())
 }

--- a/objdiff-core/tests/arch_mips.rs
+++ b/objdiff-core/tests/arch_mips.rs
@@ -62,3 +62,21 @@ fn filter_non_matching() {
    .unwrap();
    insta::assert_debug_snapshot!(obj.symbols);
 }
+
+#[test]
+#[cfg(feature = "mips")]
+fn ido_mdebug_line_numbers() {
+    let diff_config = diff::DiffObjConfig::default();
+    let obj = obj::read::parse(
+        include_object!("data/mips/ido_lines_example.o"),
+        &diff_config,
+        diff::DiffSide::Base,
+    )
+    .unwrap();
+
+    let text_section = obj.sections.iter().find(|s| s.name == ".text").unwrap();
+    assert_eq!(text_section.line_info.get(&0), Some(&6));
+    assert_eq!(text_section.line_info.get(&12), Some(&7));
+    assert_eq!(text_section.line_info.get(&56), Some(&9));
+    assert_eq!(text_section.line_info.len(), 66);
+}
--- a/objdiff-core/tests/data/mips/ido_lines_example.o
+++ b/objdiff-core/tests/data/mips/ido_lines_example.o
--- a/objdiff-core/tests/snapshots/arch_arm__combine_text_sections-2.snap
+++ b/objdiff-core/tests/snapshots/arch_arm__combine_text_sections-2.snap
@@ -2,6 +2,6 @@
 source: objdiff-core/tests/arch_arm.rs
 expression: output
 ---
-[(Line(90), Dim, 5), (Address(0), Dim, 5), (Spacing(4), Normal, 0), (Opcode("ldr", 32799), Normal, 10), (Argument(Opaque("r12")), Normal, 0), (Basic(", "), Normal, 0), (Basic("["), Normal, 0), (Argument(Opaque("pc")), Normal, 0), (Basic(", "), Normal, 0), (Basic("#"), Normal, 0), (Argument(Signed(0)), Normal, 0), (Basic("]"), Normal, 0), (Basic(" (->"), Normal, 0), (BranchDest(8), Normal, 0), (Basic(")"), Normal, 0), (Eol, Normal, 0)]
-[(Line(90), Dim, 5), (Address(4), Dim, 5), (Spacing(4), Normal, 0), (Opcode("bx", 32779), Normal, 10), (Argument(Opaque("r12")), Normal, 0), (Eol, Normal, 0)]
+[(Line(90), Dim, 5), (Address(0), Dim, 5), (Spacing(4), Normal, 0), (Opcode("ldr", 32792), Normal, 10), (Argument(Opaque("r12")), Normal, 0), (Basic(", "), Normal, 0), (Basic("["), Normal, 0), (Argument(Opaque("pc")), Normal, 0), (Basic(", "), Normal, 0), (Basic("#"), Normal, 0), (Argument(Signed(0)), Normal, 0), (Basic("]"), Normal, 0), (Basic(" (->"), Normal, 0), (BranchDest(8), Normal, 0), (Basic(")"), Normal, 0), (Eol, Normal, 0)]
+[(Line(90), Dim, 5), (Address(4), Dim, 5), (Spacing(4), Normal, 0), (Opcode("bx", 32777), Normal, 10), (Argument(Opaque("r12")), Normal, 0), (Eol, Normal, 0)]
 [(Line(90), Dim, 5), (Address(8), Dim, 5), (Spacing(4), Normal, 0), (Opcode(".word", 65534), Normal, 10), (Symbol(Symbol { name: "esEnemyDraw", demangled_name: None, address: 0, size: 0, kind: Unknown, section: None, flags: FlagSet(Global), align: None, virtual_address: None }), Bright, 0), (Eol, Normal, 0)]
--- a/objdiff-core/tests/snapshots/arch_arm__combine_text_sections.snap
+++ b/objdiff-core/tests/snapshots/arch_arm__combine_text_sections.snap
@@ -8,7 +8,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 76,
                size: 4,
-                opcode: 32799,
+                opcode: 32792,
                branch_dest: None,
            },
        ),
@@ -22,7 +22,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 80,
                size: 4,
-                opcode: 32779,
+                opcode: 32777,
                branch_dest: None,
            },
        ),
--- a/objdiff-core/tests/snapshots/arch_arm__read_arm-2.snap
+++ b/objdiff-core/tests/snapshots/arch_arm__read_arm-2.snap
@@ -8,7 +8,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 40,
                size: 4,
-                opcode: 32895,
+                opcode: 32883,
                branch_dest: None,
            },
        ),
@@ -22,7 +22,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 44,
                size: 4,
-                opcode: 32818,
+                opcode: 32811,
                branch_dest: None,
            },
        ),
@@ -36,7 +36,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 48,
                size: 4,
-                opcode: 32818,
+                opcode: 32811,
                branch_dest: None,
            },
        ),
@@ -50,7 +50,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 52,
                size: 4,
-                opcode: 32774,
+                opcode: 32775,
                branch_dest: None,
            },
        ),
@@ -64,7 +64,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 56,
                size: 4,
-                opcode: 32799,
+                opcode: 32792,
                branch_dest: None,
            },
        ),
@@ -78,7 +78,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 60,
                size: 4,
-                opcode: 32786,
+                opcode: 32784,
                branch_dest: None,
            },
        ),
@@ -92,7 +92,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 64,
                size: 4,
-                opcode: 32770,
+                opcode: 32769,
                branch_dest: None,
            },
        ),
@@ -106,7 +106,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 68,
                size: 4,
-                opcode: 32773,
+                opcode: 32772,
                branch_dest: Some(
                    240,
                ),
@@ -127,7 +127,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 72,
                size: 4,
-                opcode: 32773,
+                opcode: 32772,
                branch_dest: Some(
                    240,
                ),
@@ -148,7 +148,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 76,
                size: 4,
-                opcode: 32773,
+                opcode: 32772,
                branch_dest: Some(
                    240,
                ),
@@ -169,7 +169,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 80,
                size: 4,
-                opcode: 32773,
+                opcode: 32772,
                branch_dest: Some(
                    240,
                ),
@@ -190,7 +190,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 84,
                size: 4,
-                opcode: 32773,
+                opcode: 32772,
                branch_dest: Some(
                    232,
                ),
@@ -211,7 +211,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 88,
                size: 4,
-                opcode: 32773,
+                opcode: 32772,
                branch_dest: Some(
                    164,
                ),
@@ -232,7 +232,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 92,
                size: 4,
-                opcode: 32773,
+                opcode: 32772,
                branch_dest: Some(
                    240,
                ),
@@ -253,7 +253,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 96,
                size: 4,
-                opcode: 32773,
+                opcode: 32772,
                branch_dest: Some(
                    180,
                ),
@@ -274,7 +274,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 100,
                size: 4,
-                opcode: 32773,
+                opcode: 32772,
                branch_dest: Some(
                    116,
                ),
@@ -295,7 +295,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 104,
                size: 4,
-                opcode: 32773,
+                opcode: 32772,
                branch_dest: Some(
                    192,
                ),
@@ -316,7 +316,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 108,
                size: 4,
-                opcode: 32773,
+                opcode: 32772,
                branch_dest: Some(
                    204,
                ),
@@ -337,7 +337,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 112,
                size: 4,
-                opcode: 32773,
+                opcode: 32772,
                branch_dest: Some(
                    204,
                ),
@@ -358,7 +358,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 116,
                size: 4,
-                opcode: 32799,
+                opcode: 32792,
                branch_dest: None,
            },
        ),
@@ -379,7 +379,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 120,
                size: 4,
-                opcode: 32799,
+                opcode: 32792,
                branch_dest: None,
            },
        ),
@@ -393,7 +393,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 124,
                size: 4,
-                opcode: 32774,
+                opcode: 32775,
                branch_dest: None,
            },
        ),
@@ -407,7 +407,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 128,
                size: 4,
-                opcode: 32800,
+                opcode: 32793,
                branch_dest: None,
            },
        ),
@@ -421,7 +421,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 132,
                size: 4,
-                opcode: 32786,
+                opcode: 32784,
                branch_dest: None,
            },
        ),
@@ -435,7 +435,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 136,
                size: 4,
-                opcode: 32773,
+                opcode: 32772,
                branch_dest: Some(
                    148,
                ),
@@ -456,7 +456,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 140,
                size: 4,
-                opcode: 32774,
+                opcode: 32775,
                branch_dest: Some(
                    464,
                ),
@@ -477,7 +477,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 144,
                size: 4,
-                opcode: 32774,
+                opcode: 32775,
                branch_dest: None,
            },
        ),
@@ -491,7 +491,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 148,
                size: 4,
-                opcode: 32799,
+                opcode: 32792,
                branch_dest: None,
            },
        ),
@@ -512,7 +512,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 152,
                size: 4,
-                opcode: 32799,
+                opcode: 32792,
                branch_dest: None,
            },
        ),
@@ -526,7 +526,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 156,
                size: 4,
-                opcode: 32777,
+                opcode: 32776,
                branch_dest: None,
            },
        ),
@@ -540,7 +540,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 160,
                size: 4,
-                opcode: 32773,
+                opcode: 32772,
                branch_dest: Some(
                    240,
                ),
@@ -561,7 +561,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 164,
                size: 4,
-                opcode: 32818,
+                opcode: 32811,
                branch_dest: None,
            },
        ),
@@ -582,7 +582,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 168,
                size: 4,
-                opcode: 32818,
+                opcode: 32811,
                branch_dest: None,
            },
        ),
@@ -596,7 +596,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 172,
                size: 4,
-                opcode: 32774,
+                opcode: 32775,
                branch_dest: None,
            },
        ),
@@ -610,7 +610,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 176,
                size: 4,
-                opcode: 32773,
+                opcode: 32772,
                branch_dest: Some(
                    240,
                ),
@@ -631,7 +631,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 180,
                size: 4,
-                opcode: 32818,
+                opcode: 32811,
                branch_dest: None,
            },
        ),
@@ -652,7 +652,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 184,
                size: 4,
-                opcode: 32774,
+                opcode: 32775,
                branch_dest: None,
            },
        ),
@@ -666,7 +666,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 188,
                size: 4,
-                opcode: 32773,
+                opcode: 32772,
                branch_dest: Some(
                    240,
                ),
@@ -687,7 +687,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 192,
                size: 4,
-                opcode: 32818,
+                opcode: 32811,
                branch_dest: None,
            },
        ),
@@ -708,7 +708,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 196,
                size: 4,
-                opcode: 32774,
+                opcode: 32775,
                branch_dest: None,
            },
        ),
@@ -722,7 +722,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 200,
                size: 4,
-                opcode: 32773,
+                opcode: 32772,
                branch_dest: Some(
                    240,
                ),
@@ -743,7 +743,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 204,
                size: 4,
-                opcode: 32799,
+                opcode: 32792,
                branch_dest: None,
            },
        ),
@@ -765,7 +765,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 208,
                size: 4,
-                opcode: 32818,
+                opcode: 32811,
                branch_dest: None,
            },
        ),
@@ -779,7 +779,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 212,
                size: 4,
-                opcode: 32799,
+                opcode: 32792,
                branch_dest: None,
            },
        ),
@@ -793,7 +793,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 216,
                size: 4,
-                opcode: 32818,
+                opcode: 32811,
                branch_dest: None,
            },
        ),
@@ -807,7 +807,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 220,
                size: 4,
-                opcode: 32899,
+                opcode: 32885,
                branch_dest: None,
            },
        ),
@@ -821,7 +821,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 224,
                size: 4,
-                opcode: 32774,
+                opcode: 32775,
                branch_dest: None,
            },
        ),
@@ -835,7 +835,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 228,
                size: 4,
-                opcode: 32773,
+                opcode: 32772,
                branch_dest: Some(
                    240,
                ),
@@ -856,7 +856,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 232,
                size: 4,
-                opcode: 32818,
+                opcode: 32811,
                branch_dest: None,
            },
        ),
@@ -877,7 +877,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 236,
                size: 4,
-                opcode: 32774,
+                opcode: 32775,
                branch_dest: None,
            },
        ),
@@ -891,7 +891,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 240,
                size: 4,
-                opcode: 32799,
+                opcode: 32792,
                branch_dest: None,
            },
        ),
@@ -921,7 +921,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 244,
                size: 4,
-                opcode: 32829,
+                opcode: 32819,
                branch_dest: None,
            },
        ),
@@ -935,7 +935,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 248,
                size: 4,
-                opcode: 32786,
+                opcode: 32784,
                branch_dest: None,
            },
        ),
@@ -949,7 +949,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 252,
                size: 4,
-                opcode: 32773,
+                opcode: 32772,
                branch_dest: Some(
                    276,
                ),
@@ -970,7 +970,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 256,
                size: 4,
-                opcode: 32818,
+                opcode: 32811,
                branch_dest: None,
            },
        ),
@@ -984,7 +984,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 260,
                size: 4,
-                opcode: 32774,
+                opcode: 32775,
                branch_dest: None,
            },
        ),
@@ -998,7 +998,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 264,
                size: 4,
-                opcode: 32799,
+                opcode: 32792,
                branch_dest: None,
            },
        ),
@@ -1012,7 +1012,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 268,
                size: 4,
-                opcode: 32799,
+                opcode: 32792,
                branch_dest: None,
            },
        ),
@@ -1026,7 +1026,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 272,
                size: 4,
-                opcode: 32778,
+                opcode: 32776,
                branch_dest: None,
            },
        ),
@@ -1040,7 +1040,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 276,
                size: 4,
-                opcode: 32799,
+                opcode: 32792,
                branch_dest: None,
            },
        ),
@@ -1061,7 +1061,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 280,
                size: 4,
-                opcode: 32786,
+                opcode: 32784,
                branch_dest: None,
            },
        ),
@@ -1075,7 +1075,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 284,
                size: 4,
-                opcode: 32773,
+                opcode: 32772,
                branch_dest: Some(
                    328,
                ),
@@ -1096,7 +1096,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 288,
                size: 4,
-                opcode: 32773,
+                opcode: 32772,
                branch_dest: Some(
                    336,
                ),
@@ -1117,7 +1117,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 292,
                size: 4,
-                opcode: 32786,
+                opcode: 32784,
                branch_dest: None,
            },
        ),
@@ -1131,7 +1131,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 296,
                size: 4,
-                opcode: 32773,
+                opcode: 32772,
                branch_dest: Some(
                    348,
                ),
@@ -1152,7 +1152,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 300,
                size: 4,
-                opcode: 32829,
+                opcode: 32819,
                branch_dest: None,
            },
        ),
@@ -1166,7 +1166,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 304,
                size: 4,
-                opcode: 32786,
+                opcode: 32784,
                branch_dest: None,
            },
        ),
@@ -1180,7 +1180,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 308,
                size: 4,
-                opcode: 32773,
+                opcode: 32772,
                branch_dest: Some(
                    348,
                ),
@@ -1201,7 +1201,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 312,
                size: 4,
-                opcode: 32786,
+                opcode: 32784,
                branch_dest: None,
            },
        ),
@@ -1215,7 +1215,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 316,
                size: 4,
-                opcode: 32786,
+                opcode: 32784,
                branch_dest: None,
            },
        ),
@@ -1229,7 +1229,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 320,
                size: 4,
-                opcode: 32773,
+                opcode: 32772,
                branch_dest: Some(
                    380,
                ),
@@ -1250,7 +1250,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 324,
                size: 4,
-                opcode: 32773,
+                opcode: 32772,
                branch_dest: Some(
                    348,
                ),
@@ -1271,7 +1271,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 328,
                size: 4,
-                opcode: 32786,
+                opcode: 32784,
                branch_dest: None,
            },
        ),
@@ -1292,7 +1292,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 332,
                size: 4,
-                opcode: 32773,
+                opcode: 32772,
                branch_dest: Some(
                    348,
                ),
@@ -1313,7 +1313,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 336,
                size: 4,
-                opcode: 32818,
+                opcode: 32811,
                branch_dest: None,
            },
        ),
@@ -1334,7 +1334,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 340,
                size: 4,
-                opcode: 32774,
+                opcode: 32775,
                branch_dest: None,
            },
        ),
@@ -1348,7 +1348,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 344,
                size: 4,
-                opcode: 32773,
+                opcode: 32772,
                branch_dest: Some(
                    380,
                ),
@@ -1369,7 +1369,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 348,
                size: 4,
-                opcode: 32818,
+                opcode: 32811,
                branch_dest: None,
            },
        ),
@@ -1393,7 +1393,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 352,
                size: 4,
-                opcode: 32774,
+                opcode: 32775,
                branch_dest: None,
            },
        ),
@@ -1407,7 +1407,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 356,
                size: 4,
-                opcode: 32786,
+                opcode: 32784,
                branch_dest: None,
            },
        ),
@@ -1421,7 +1421,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 360,
                size: 4,
-                opcode: 32786,
+                opcode: 32784,
                branch_dest: None,
            },
        ),
@@ -1435,7 +1435,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 364,
                size: 4,
-                opcode: 32773,
+                opcode: 32772,
                branch_dest: Some(
                    380,
                ),
@@ -1456,7 +1456,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 368,
                size: 4,
-                opcode: 32774,
+                opcode: 32775,
                branch_dest: None,
            },
        ),
@@ -1470,7 +1470,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 372,
                size: 4,
-                opcode: 32818,
+                opcode: 32811,
                branch_dest: None,
            },
        ),
@@ -1484,7 +1484,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 376,
                size: 4,
-                opcode: 32899,
+                opcode: 32885,
                branch_dest: None,
            },
        ),
@@ -1498,7 +1498,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 380,
                size: 4,
-                opcode: 32829,
+                opcode: 32819,
                branch_dest: None,
            },
        ),
@@ -1521,7 +1521,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 384,
                size: 4,
-                opcode: 32770,
+                opcode: 32769,
                branch_dest: None,
            },
        ),
@@ -1535,7 +1535,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 388,
                size: 4,
-                opcode: 32770,
+                opcode: 32769,
                branch_dest: None,
            },
        ),
@@ -1549,7 +1549,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 392,
                size: 4,
-                opcode: 32898,
+                opcode: 32884,
                branch_dest: None,
            },
        ),
@@ -1563,7 +1563,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 396,
                size: 4,
-                opcode: 32786,
+                opcode: 32784,
                branch_dest: None,
            },
        ),
@@ -1577,7 +1577,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 400,
                size: 4,
-                opcode: 32773,
+                opcode: 32772,
                branch_dest: Some(
                    424,
                ),
@@ -1598,7 +1598,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 404,
                size: 4,
-                opcode: 32818,
+                opcode: 32811,
                branch_dest: None,
            },
        ),
@@ -1619,7 +1619,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 408,
                size: 4,
-                opcode: 32774,
+                opcode: 32775,
                branch_dest: None,
            },
        ),
@@ -1633,7 +1633,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 412,
                size: 4,
-                opcode: 32770,
+                opcode: 32769,
                branch_dest: None,
            },
        ),
@@ -1647,7 +1647,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 416,
                size: 4,
-                opcode: 32786,
+                opcode: 32784,
                branch_dest: None,
            },
        ),
@@ -1661,7 +1661,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 420,
                size: 4,
-                opcode: 32773,
+                opcode: 32772,
                branch_dest: Some(
                    404,
                ),
@@ -1682,7 +1682,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 424,
                size: 4,
-                opcode: 32799,
+                opcode: 32792,
                branch_dest: None,
            },
        ),
@@ -1703,7 +1703,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 428,
                size: 4,
-                opcode: 32799,
+                opcode: 32792,
                branch_dest: None,
            },
        ),
@@ -1717,7 +1717,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 432,
                size: 4,
-                opcode: 32800,
+                opcode: 32793,
                branch_dest: None,
            },
        ),
@@ -1731,7 +1731,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 436,
                size: 4,
-                opcode: 32786,
+                opcode: 32784,
                branch_dest: None,
            },
        ),
@@ -1745,7 +1745,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 440,
                size: 4,
-                opcode: 32773,
+                opcode: 32772,
                branch_dest: Some(
                    448,
                ),
@@ -1766,7 +1766,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 444,
                size: 4,
-                opcode: 32774,
+                opcode: 32775,
                branch_dest: None,
            },
        ),
@@ -1780,7 +1780,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 448,
                size: 4,
-                opcode: 32818,
+                opcode: 32811,
                branch_dest: None,
            },
        ),
@@ -1801,7 +1801,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 452,
                size: 4,
-                opcode: 32899,
+                opcode: 32885,
                branch_dest: None,
            },
        ),
@@ -1815,7 +1815,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 456,
                size: 4,
-                opcode: 32793,
+                opcode: 32791,
                branch_dest: None,
            },
        ),
--- a/objdiff-core/tests/snapshots/arch_arm__read_arm-3.snap
+++ b/objdiff-core/tests/snapshots/arch_arm__read_arm-3.snap
@@ -2,111 +2,111 @@
 source: objdiff-core/tests/arch_arm.rs
 expression: output
 ---
-[(Address(0), Dim, 5), (Spacing(4), Normal, 0), (Opcode("stmdb", 32895), Normal, 10), (Argument(Opaque("sp")), Normal, 0), (Argument(Opaque("!")), Normal, 0), (Basic(", "), Normal, 0), (Basic("{"), Normal, 0), (Argument(Opaque("r4")), Normal, 0), (Basic(", "), Normal, 0), (Argument(Opaque("r5")), Normal, 0), (Basic(", "), Normal, 0), (Argument(Opaque("r6")), Normal, 0), (Basic(", "), Normal, 0), (Argument(Opaque("lr")), Normal, 0), (Basic("}"), Normal, 0), (Eol, Normal, 0)]
-[(Address(4), Dim, 5), (Spacing(4), Normal, 0), (Opcode("mov", 32818), Normal, 10), (Argument(Opaque("r5")), Normal, 0), (Basic(", "), Normal, 0), (Argument(Opaque("r0")), Normal, 0), (Eol, Normal, 0)]
-[(Address(8), Dim, 5), (Spacing(4), Normal, 0), (Opcode("mov", 32818), Normal, 10), (Argument(Opaque("r4")), Normal, 0), (Basic(", "), Normal, 0), (Argument(Opaque("r1")), Normal, 0), (Eol, Normal, 0)]
-[(Address(12), Dim, 5), (Spacing(4), Normal, 0), (Opcode("bl", 32774), Normal, 10), (Symbol(Symbol { name: "_ZN13LinkStateBase12OnStateLeaveEi", demangled_name: Some("LinkStateBase::OnStateLeave(int)"), address: 0, size: 0, kind: Unknown, section: None, flags: FlagSet(Global | Weak), align: None, virtual_address: None }), Bright, 0), (Addend(-8), Bright, 0), (Eol, Normal, 0)]
-[(Address(16), Dim, 5), (Spacing(4), Normal, 0), (Opcode("ldr", 32799), Normal, 10), (Argument(Opaque("r0")), Normal, 0), (Basic(", "), Normal, 0), (Basic("["), Normal, 0), (Argument(Opaque("r5")), Normal, 0), (Basic(", "), Normal, 0), (Basic("#"), Normal, 0), (Argument(Signed(20)), Normal, 0), (Basic("]"), Normal, 0), (Eol, Normal, 0)]
-[(Address(20), Dim, 5), (Spacing(4), Normal, 0), (Opcode("cmp", 32786), Normal, 10), (Argument(Opaque("r0")), Normal, 0), (Basic(", "), Normal, 0), (Basic("#"), Normal, 0), (Argument(Unsigned(10)), Normal, 0), (Eol, Normal, 0)]
-[(Address(24), Dim, 5), (Spacing(4), Normal, 0), (Opcode("addls", 32770), Normal, 10), (Argument(Opaque("pc")), Normal, 0), (Basic(", "), Normal, 0), (Argument(Opaque("pc")), Normal, 0), (Basic(", "), Normal, 0), (Argument(Opaque("r0")), Normal, 0), (Basic(", "), Normal, 0), (Argument(Opaque("lsl")), Normal, 0), (Basic(" #"), Normal, 0), (Argument(Unsigned(2)), Normal, 0), (Eol, Normal, 0)]
-[(Address(28), Dim, 5), (Spacing(4), Normal, 0), (Opcode("b", 32773), Normal, 10), (BranchDest(200), Normal, 0), (Basic(" ~>"), Rotating(0), 0), (Eol, Normal, 0)]
-[(Address(32), Dim, 5), (Spacing(4), Normal, 0), (Opcode("b", 32773), Normal, 10), (BranchDest(200), Normal, 0), (Basic(" ~>"), Rotating(0), 0), (Eol, Normal, 0)]
-[(Address(36), Dim, 5), (Spacing(4), Normal, 0), (Opcode("b", 32773), Normal, 10), (BranchDest(200), Normal, 0), (Basic(" ~>"), Rotating(0), 0), (Eol, Normal, 0)]
-[(Address(40), Dim, 5), (Spacing(4), Normal, 0), (Opcode("b", 32773), Normal, 10), (BranchDest(200), Normal, 0), (Basic(" ~>"), Rotating(0), 0), (Eol, Normal, 0)]
-[(Address(44), Dim, 5), (Spacing(4), Normal, 0), (Opcode("b", 32773), Normal, 10), (BranchDest(192), Normal, 0), (Basic(" ~>"), Rotating(1), 0), (Eol, Normal, 0)]
-[(Address(48), Dim, 5), (Spacing(4), Normal, 0), (Opcode("b", 32773), Normal, 10), (BranchDest(124), Normal, 0), (Basic(" ~>"), Rotating(2), 0), (Eol, Normal, 0)]
-[(Address(52), Dim, 5), (Spacing(4), Normal, 0), (Opcode("b", 32773), Normal, 10), (BranchDest(200), Normal, 0), (Basic(" ~>"), Rotating(0), 0), (Eol, Normal, 0)]
-[(Address(56), Dim, 5), (Spacing(4), Normal, 0), (Opcode("b", 32773), Normal, 10), (BranchDest(140), Normal, 0), (Basic(" ~>"), Rotating(3), 0), (Eol, Normal, 0)]
-[(Address(60), Dim, 5), (Spacing(4), Normal, 0), (Opcode("b", 32773), Normal, 10), (BranchDest(76), Normal, 0), (Basic(" ~>"), Rotating(4), 0), (Eol, Normal, 0)]
-[(Address(64), Dim, 5), (Spacing(4), Normal, 0), (Opcode("b", 32773), Normal, 10), (BranchDest(152), Normal, 0), (Basic(" ~>"), Rotating(5), 0), (Eol, Normal, 0)]
-[(Address(68), Dim, 5), (Spacing(4), Normal, 0), (Opcode("b", 32773), Normal, 10), (BranchDest(164), Normal, 0), (Basic(" ~>"), Rotating(6), 0), (Eol, Normal, 0)]
-[(Address(72), Dim, 5), (Spacing(4), Normal, 0), (Opcode("b", 32773), Normal, 10), (BranchDest(164), Normal, 0), (Basic(" ~>"), Rotating(6), 0), (Eol, Normal, 0)]
-[(Address(76), Dim, 5), (Basic(" ~> "), Rotating(4), 0), (Opcode("ldr", 32799), Normal, 10), (Argument(Opaque("r0")), Normal, 0), (Basic(", "), Normal, 0), (Basic("["), Normal, 0), (Argument(Opaque("pc")), Normal, 0), (Basic(", "), Normal, 0), (Basic("#"), Normal, 0), (Argument(Signed(336)), Normal, 0), (Basic("]"), Normal, 0), (Basic(" (->"), Normal, 0), (BranchDest(420), Normal, 0), (Basic(")"), Normal, 0), (Eol, Normal, 0)]
-[(Address(80), Dim, 5), (Spacing(4), Normal, 0), (Opcode("ldr", 32799), Normal, 10), (Argument(Opaque("r0")), Normal, 0), (Basic(", "), Normal, 0), (Basic("["), Normal, 0), (Argument(Opaque("r0")), Normal, 0), (Basic(", "), Normal, 0), (Basic("#"), Normal, 0), (Argument(Signed(0)), Normal, 0), (Basic("]"), Normal, 0), (Eol, Normal, 0)]
-[(Address(84), Dim, 5), (Spacing(4), Normal, 0), (Opcode("bl", 32774), Normal, 10), (Symbol(Symbol { name: "_ZN18UnkStruct_027e103c19func_ov000_020cf01cEv", demangled_name: Some("UnkStruct_027e103c::func_ov000_020cf01c()"), address: 0, size: 0, kind: Unknown, section: None, flags: FlagSet(Global | Weak), align: None, virtual_address: None }), Bright, 0), (Addend(-8), Bright, 0), (Eol, Normal, 0)]
-[(Address(88), Dim, 5), (Spacing(4), Normal, 0), (Opcode("ldrb", 32800), Normal, 10), (Argument(Opaque("r0")), Normal, 0), (Basic(", "), Normal, 0), (Basic("["), Normal, 0), (Argument(Opaque("r0")), Normal, 0), (Basic(", "), Normal, 0), (Basic("#"), Normal, 0), (Argument(Signed(224)), Normal, 0), (Basic("]"), Normal, 0), (Eol, Normal, 0)]
-[(Address(92), Dim, 5), (Spacing(4), Normal, 0), (Opcode("cmp", 32786), Normal, 10), (Argument(Opaque("r0")), Normal, 0), (Basic(", "), Normal, 0), (Basic("#"), Normal, 0), (Argument(Unsigned(0)), Normal, 0), (Eol, Normal, 0)]
-[(Address(96), Dim, 5), (Spacing(4), Normal, 0), (Opcode("bne", 32773), Normal, 10), (BranchDest(108), Normal, 0), (Basic(" ~>"), Rotating(7), 0), (Eol, Normal, 0)]
-[(Address(100), Dim, 5), (Spacing(4), Normal, 0), (Opcode("bl", 32774), Normal, 10), (BranchDest(424), Normal, 0), (Basic(" ~>"), Rotating(8), 0), (Eol, Normal, 0)]
-[(Address(104), Dim, 5), (Spacing(4), Normal, 0), (Opcode("bl", 32774), Normal, 10), (Symbol(Symbol { name: "_ZN12EquipBombchu19func_ov014_0213ec64Ev", demangled_name: Some("EquipBombchu::func_ov014_0213ec64()"), address: 0, size: 0, kind: Unknown, section: None, flags: FlagSet(Global | Weak), align: None, virtual_address: None }), Bright, 0), (Addend(-8), Bright, 0), (Eol, Normal, 0)]
-[(Address(108), Dim, 5), (Basic(" ~> "), Rotating(7), 0), (Opcode("ldr", 32799), Normal, 10), (Argument(Opaque("r0")), Normal, 0), (Basic(", "), Normal, 0), (Basic("["), Normal, 0), (Argument(Opaque("pc")), Normal, 0), (Basic(", "), Normal, 0), (Basic("#"), Normal, 0), (Argument(Signed(308)), Normal, 0), (Basic("]"), Normal, 0), (Basic(" (->"), Normal, 0), (BranchDest(424), Normal, 0), (Basic(")"), Normal, 0), (Eol, Normal, 0)]
-[(Address(112), Dim, 5), (Spacing(4), Normal, 0), (Opcode("ldr", 32799), Normal, 10), (Argument(Opaque("r0")), Normal, 0), (Basic(", "), Normal, 0), (Basic("["), Normal, 0), (Argument(Opaque("r0")), Normal, 0), (Basic(", "), Normal, 0), (Basic("#"), Normal, 0), (Argument(Signed(0)), Normal, 0), (Basic("]"), Normal, 0), (Eol, Normal, 0)]
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+[(Address(316), Dim, 5), (Spacing(4), Normal, 0), (Opcode("cmp", 32784), Normal, 10), (Argument(Opaque("r4")), Normal, 0), (Basic(", "), Normal, 0), (Basic("#"), Normal, 0), (Argument(Unsigned(4)), Normal, 0), (Eol, Normal, 0)]
+[(Address(320), Dim, 5), (Spacing(4), Normal, 0), (Opcode("cmpne", 32784), Normal, 10), (Argument(Opaque("r4")), Normal, 0), (Basic(", "), Normal, 0), (Basic("#"), Normal, 0), (Argument(Unsigned(2)), Normal, 0), (Eol, Normal, 0)]
+[(Address(324), Dim, 5), (Spacing(4), Normal, 0), (Opcode("beq", 32772), Normal, 10), (BranchDest(340), Normal, 0), (Basic(" ~>"), Rotating(13), 0), (Eol, Normal, 0)]
+[(Address(328), Dim, 5), (Spacing(4), Normal, 0), (Opcode("bl", 32775), Normal, 10), (Symbol(Symbol { name: "_ZN13LinkStateItem16GetLinkStateMoveEv", demangled_name: Some("LinkStateItem::GetLinkStateMove()"), address: 488, size: 16, kind: Function, section: Some(0), flags: FlagSet(Global), align: None, virtual_address: None }), Bright, 0), (Addend(-8), Bright, 0), (Eol, Normal, 0)]
+[(Address(332), Dim, 5), (Spacing(4), Normal, 0), (Opcode("mov", 32811), Normal, 10), (Argument(Opaque("r1")), Normal, 0), (Basic(", "), Normal, 0), (Basic("#"), Normal, 0), (Argument(Unsigned(1)), Normal, 0), (Eol, Normal, 0)]
+[(Address(336), Dim, 5), (Spacing(4), Normal, 0), (Opcode("strb", 32885), Normal, 10), (Argument(Opaque("r1")), Normal, 0), (Basic(", "), Normal, 0), (Basic("["), Normal, 0), (Argument(Opaque("r0")), Normal, 0), (Basic(", "), Normal, 0), (Basic("#"), Normal, 0), (Argument(Signed(20)), Normal, 0), (Basic("]"), Normal, 0), (Eol, Normal, 0)]
+[(Address(340), Dim, 5), (Basic(" ~> "), Rotating(13), 0), (Opcode("mvn", 32819), Normal, 10), (Argument(Opaque("r0")), Normal, 0), (Basic(", "), Normal, 0), (Basic("#"), Normal, 0), (Argument(Unsigned(0)), Normal, 0), (Eol, Normal, 0)]
+[(Address(344), Dim, 5), (Spacing(4), Normal, 0), (Opcode("add", 32769), Normal, 10), (Argument(Opaque("r6")), Normal, 0), (Basic(", "), Normal, 0), (Argument(Opaque("r5")), Normal, 0), (Basic(", "), Normal, 0), (Basic("#"), Normal, 0), (Argument(Unsigned(80)), Normal, 0), (Eol, Normal, 0)]
+[(Address(348), Dim, 5), (Spacing(4), Normal, 0), (Opcode("add", 32769), Normal, 10), (Argument(Opaque("r4")), Normal, 0), (Basic(", "), Normal, 0), (Argument(Opaque("r5")), Normal, 0), (Basic(", "), Normal, 0), (Basic("#"), Normal, 0), (Argument(Unsigned(88)), Normal, 0), (Eol, Normal, 0)]
+[(Address(352), Dim, 5), (Spacing(4), Normal, 0), (Opcode("str", 32884), Normal, 10), (Argument(Opaque("r0")), Normal, 0), (Basic(", "), Normal, 0), (Basic("["), Normal, 0), (Argument(Opaque("r5")), Normal, 0), (Basic(", "), Normal, 0), (Basic("#"), Normal, 0), (Argument(Signed(24)), Normal, 0), (Basic("]"), Normal, 0), (Eol, Normal, 0)]
+[(Address(356), Dim, 5), (Spacing(4), Normal, 0), (Opcode("cmp", 32784), Normal, 10), (Argument(Opaque("r6")), Normal, 0), (Basic(", "), Normal, 0), (Argument(Opaque("r4")), Normal, 0), (Eol, Normal, 0)]
+[(Address(360), Dim, 5), (Spacing(4), Normal, 0), (Opcode("beq", 32772), Normal, 10), (BranchDest(384), Normal, 0), (Basic(" ~>"), Rotating(14), 0), (Eol, Normal, 0)]
+[(Address(364), Dim, 5), (Basic(" ~> "), Rotating(15), 0), (Opcode("mov", 32811), Normal, 10), (Argument(Opaque("r0")), Normal, 0), (Basic(", "), Normal, 0), (Argument(Opaque("r6")), Normal, 0), (Eol, Normal, 0)]
+[(Address(368), Dim, 5), (Spacing(4), Normal, 0), (Opcode("bl", 32775), Normal, 10), (Symbol(Symbol { name: "_Z19func_ov000_020b7e6cPi", demangled_name: Some("func_ov000_020b7e6c(int*)"), address: 0, size: 0, kind: Unknown, section: None, flags: FlagSet(Global | Weak), align: None, virtual_address: None }), Bright, 0), (Addend(-8), Bright, 0), (Eol, Normal, 0)]
+[(Address(372), Dim, 5), (Spacing(4), Normal, 0), (Opcode("add", 32769), Normal, 10), (Argument(Opaque("r6")), Normal, 0), (Basic(", "), Normal, 0), (Argument(Opaque("r6")), Normal, 0), (Basic(", "), Normal, 0), (Basic("#"), Normal, 0), (Argument(Unsigned(4)), Normal, 0), (Eol, Normal, 0)]
+[(Address(376), Dim, 5), (Spacing(4), Normal, 0), (Opcode("cmp", 32784), Normal, 10), (Argument(Opaque("r6")), Normal, 0), (Basic(", "), Normal, 0), (Argument(Opaque("r4")), Normal, 0), (Eol, Normal, 0)]
+[(Address(380), Dim, 5), (Spacing(4), Normal, 0), (Opcode("bne", 32772), Normal, 10), (BranchDest(364), Normal, 0), (Basic(" ~>"), Rotating(15), 0), (Eol, Normal, 0)]
+[(Address(384), Dim, 5), (Basic(" ~> "), Rotating(14), 0), (Opcode("ldr", 32792), Normal, 10), (Argument(Opaque("r0")), Normal, 0), (Basic(", "), Normal, 0), (Basic("["), Normal, 0), (Argument(Opaque("pc")), Normal, 0), (Basic(", "), Normal, 0), (Basic("#"), Normal, 0), (Argument(Signed(36)), Normal, 0), (Basic("]"), Normal, 0), (Basic(" (->"), Normal, 0), (BranchDest(428), Normal, 0), (Basic(")"), Normal, 0), (Eol, Normal, 0)]
+[(Address(388), Dim, 5), (Spacing(4), Normal, 0), (Opcode("ldr", 32792), Normal, 10), (Argument(Opaque("r0")), Normal, 0), (Basic(", "), Normal, 0), (Basic("["), Normal, 0), (Argument(Opaque("r0")), Normal, 0), (Basic(", "), Normal, 0), (Basic("#"), Normal, 0), (Argument(Signed(0)), Normal, 0), (Basic("]"), Normal, 0), (Eol, Normal, 0)]
+[(Address(392), Dim, 5), (Spacing(4), Normal, 0), (Opcode("ldrb", 32793), Normal, 10), (Argument(Opaque("r1")), Normal, 0), (Basic(", "), Normal, 0), (Basic("["), Normal, 0), (Argument(Opaque("r0")), Normal, 0), (Basic(", "), Normal, 0), (Basic("#"), Normal, 0), (Argument(Signed(128)), Normal, 0), (Basic("]"), Normal, 0), (Eol, Normal, 0)]
+[(Address(396), Dim, 5), (Spacing(4), Normal, 0), (Opcode("cmp", 32784), Normal, 10), (Argument(Opaque("r1")), Normal, 0), (Basic(", "), Normal, 0), (Basic("#"), Normal, 0), (Argument(Unsigned(0)), Normal, 0), (Eol, Normal, 0)]
+[(Address(400), Dim, 5), (Spacing(4), Normal, 0), (Opcode("beq", 32772), Normal, 10), (BranchDest(408), Normal, 0), (Basic(" ~>"), Rotating(16), 0), (Eol, Normal, 0)]
+[(Address(404), Dim, 5), (Spacing(4), Normal, 0), (Opcode("bl", 32775), Normal, 10), (Symbol(Symbol { name: "_ZN13PlayerControl13StopFollowingEv", demangled_name: Some("PlayerControl::StopFollowing()"), address: 0, size: 0, kind: Unknown, section: None, flags: FlagSet(Global | Weak), align: None, virtual_address: None }), Bright, 0), (Addend(-8), Bright, 0), (Eol, Normal, 0)]
+[(Address(408), Dim, 5), (Basic(" ~> "), Rotating(16), 0), (Opcode("mov", 32811), Normal, 10), (Argument(Opaque("r0")), Normal, 0), (Basic(", "), Normal, 0), (Basic("#"), Normal, 0), (Argument(Unsigned(0)), Normal, 0), (Eol, Normal, 0)]
+[(Address(412), Dim, 5), (Spacing(4), Normal, 0), (Opcode("strb", 32885), Normal, 10), (Argument(Opaque("r0")), Normal, 0), (Basic(", "), Normal, 0), (Basic("["), Normal, 0), (Argument(Opaque("r5")), Normal, 0), (Basic(", "), Normal, 0), (Basic("#"), Normal, 0), (Argument(Signed(38)), Normal, 0), (Basic("]"), Normal, 0), (Eol, Normal, 0)]
+[(Address(416), Dim, 5), (Spacing(4), Normal, 0), (Opcode("ldmia", 32791), Normal, 10), (Argument(Opaque("sp")), Normal, 0), (Basic("!"), Normal, 0), (Basic(", "), Normal, 0), (Basic("{"), Normal, 0), (Argument(Opaque("r4")), Normal, 0), (Basic(", "), Normal, 0), (Argument(Opaque("r5")), Normal, 0), (Basic(", "), Normal, 0), (Argument(Opaque("r6")), Normal, 0), (Basic(", "), Normal, 0), (Argument(Opaque("pc")), Normal, 0), (Basic("}"), Normal, 0), (Eol, Normal, 0)]
 [(Address(420), Dim, 5), (Spacing(4), Normal, 0), (Opcode(".word", 65534), Normal, 10), (Symbol(Symbol { name: "data_027e103c", demangled_name: None, address: 0, size: 0, kind: Unknown, section: None, flags: FlagSet(Global | Weak), align: None, virtual_address: None }), Bright, 0), (Eol, Normal, 0)]
 [(Address(424), Dim, 5), (Basic(" ~> "), Rotating(8), 0), (Opcode(".word", 65534), Normal, 10), (Symbol(Symbol { name: "data_027e1098", demangled_name: None, address: 0, size: 0, kind: Unknown, section: None, flags: FlagSet(Global | Weak), align: None, virtual_address: None }), Bright, 0), (Eol, Normal, 0)]
 [(Address(428), Dim, 5), (Spacing(4), Normal, 0), (Opcode(".word", 65534), Normal, 10), (Symbol(Symbol { name: "gPlayerControl", demangled_name: None, address: 0, size: 0, kind: Unknown, section: None, flags: FlagSet(Global | Weak), align: None, virtual_address: None }), Bright, 0), (Eol, Normal, 0)]
--- a/objdiff-core/tests/snapshots/arch_arm__read_thumb-2.snap
+++ b/objdiff-core/tests/snapshots/arch_arm__read_thumb-2.snap
@@ -8,7 +8,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 0,
                size: 2,
-                opcode: 56,
+                opcode: 59,
                branch_dest: None,
            },
        ),
@@ -22,7 +22,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 2,
                size: 2,
-                opcode: 74,
+                opcode: 126,
                branch_dest: None,
            },
        ),
@@ -36,7 +36,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 4,
                size: 2,
-                opcode: 47,
+                opcode: 43,
                branch_dest: None,
            },
        ),
@@ -50,7 +50,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 6,
                size: 2,
-                opcode: 47,
+                opcode: 43,
                branch_dest: None,
            },
        ),
@@ -64,7 +64,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 8,
                size: 2,
-                opcode: 47,
+                opcode: 43,
                branch_dest: None,
            },
        ),
@@ -78,7 +78,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 10,
                size: 2,
-                opcode: 47,
+                opcode: 43,
                branch_dest: None,
            },
        ),
@@ -92,7 +92,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 12,
                size: 2,
-                opcode: 66,
+                opcode: 116,
                branch_dest: None,
            },
        ),
@@ -106,7 +106,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 14,
                size: 4,
-                opcode: 19,
+                opcode: 7,
                branch_dest: None,
            },
        ),
@@ -120,7 +120,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 18,
                size: 2,
-                opcode: 25,
+                opcode: 16,
                branch_dest: None,
            },
        ),
@@ -134,7 +134,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 20,
                size: 2,
-                opcode: 15,
+                opcode: 4,
                branch_dest: Some(
                    212,
                ),
@@ -155,7 +155,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 22,
                size: 2,
-                opcode: 38,
+                opcode: 32,
                branch_dest: None,
            },
        ),
@@ -169,7 +169,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 24,
                size: 2,
-                opcode: 25,
+                opcode: 16,
                branch_dest: None,
            },
        ),
@@ -183,7 +183,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 26,
                size: 2,
-                opcode: 15,
+                opcode: 4,
                branch_dest: Some(
                    48,
                ),
@@ -204,7 +204,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 28,
                size: 2,
-                opcode: 34,
+                opcode: 24,
                branch_dest: None,
            },
        ),
@@ -218,7 +218,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 30,
                size: 2,
-                opcode: 26,
+                opcode: 16,
                branch_dest: None,
            },
        ),
@@ -232,7 +232,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 32,
                size: 2,
-                opcode: 15,
+                opcode: 4,
                branch_dest: Some(
                    94,
                ),
@@ -253,7 +253,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 34,
                size: 2,
-                opcode: 35,
+                opcode: 24,
                branch_dest: None,
            },
        ),
@@ -267,7 +267,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 36,
                size: 2,
-                opcode: 47,
+                opcode: 43,
                branch_dest: None,
            },
        ),
@@ -281,7 +281,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 38,
                size: 2,
-                opcode: 47,
+                opcode: 43,
                branch_dest: None,
            },
        ),
@@ -295,7 +295,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 40,
                size: 4,
-                opcode: 19,
+                opcode: 7,
                branch_dest: None,
            },
        ),
@@ -309,7 +309,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 44,
                size: 2,
-                opcode: 7,
+                opcode: 1,
                branch_dest: None,
            },
        ),
@@ -323,7 +323,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 46,
                size: 2,
-                opcode: 55,
+                opcode: 58,
                branch_dest: None,
            },
        ),
@@ -337,7 +337,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 48,
                size: 2,
-                opcode: 47,
+                opcode: 43,
                branch_dest: None,
            },
        ),
@@ -358,7 +358,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 50,
                size: 2,
-                opcode: 47,
+                opcode: 43,
                branch_dest: None,
            },
        ),
@@ -372,7 +372,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 52,
                size: 4,
-                opcode: 19,
+                opcode: 7,
                branch_dest: None,
            },
        ),
@@ -386,7 +386,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 56,
                size: 2,
-                opcode: 25,
+                opcode: 16,
                branch_dest: None,
            },
        ),
@@ -400,7 +400,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 58,
                size: 2,
-                opcode: 15,
+                opcode: 4,
                branch_dest: Some(
                    212,
                ),
@@ -421,7 +421,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 60,
                size: 2,
-                opcode: 34,
+                opcode: 24,
                branch_dest: None,
            },
        ),
@@ -435,7 +435,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 62,
                size: 2,
-                opcode: 33,
+                opcode: 24,
                branch_dest: None,
            },
        ),
@@ -449,7 +449,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 64,
                size: 2,
-                opcode: 36,
+                opcode: 25,
                branch_dest: None,
            },
        ),
@@ -463,7 +463,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 66,
                size: 2,
-                opcode: 42,
+                opcode: 36,
                branch_dest: None,
            },
        ),
@@ -477,7 +477,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 68,
                size: 2,
-                opcode: 44,
+                opcode: 37,
                branch_dest: None,
            },
        ),
@@ -491,7 +491,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 70,
                size: 2,
-                opcode: 15,
+                opcode: 4,
                branch_dest: Some(
                    212,
                ),
@@ -512,7 +512,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 72,
                size: 2,
-                opcode: 46,
+                opcode: 43,
                branch_dest: None,
            },
        ),
@@ -526,7 +526,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 74,
                size: 2,
-                opcode: 17,
+                opcode: 5,
                branch_dest: None,
            },
        ),
@@ -540,7 +540,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 76,
                size: 2,
-                opcode: 46,
+                opcode: 43,
                branch_dest: None,
            },
        ),
@@ -568,7 +568,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 80,
                size: 2,
-                opcode: 67,
+                opcode: 117,
                branch_dest: None,
            },
        ),
@@ -582,7 +582,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 82,
                size: 2,
-                opcode: 36,
+                opcode: 25,
                branch_dest: None,
            },
        ),
@@ -596,7 +596,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 84,
                size: 2,
-                opcode: 46,
+                opcode: 43,
                branch_dest: None,
            },
        ),
@@ -610,7 +610,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 86,
                size: 2,
-                opcode: 7,
+                opcode: 1,
                branch_dest: None,
            },
        ),
@@ -638,7 +638,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 90,
                size: 2,
-                opcode: 67,
+                opcode: 117,
                branch_dest: None,
            },
        ),
@@ -652,7 +652,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 92,
                size: 2,
-                opcode: 55,
+                opcode: 58,
                branch_dest: None,
            },
        ),
@@ -666,7 +666,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 94,
                size: 2,
-                opcode: 34,
+                opcode: 24,
                branch_dest: None,
            },
        ),
@@ -687,7 +687,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 96,
                size: 2,
-                opcode: 34,
+                opcode: 24,
                branch_dest: None,
            },
        ),
@@ -701,7 +701,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 98,
                size: 2,
-                opcode: 4,
+                opcode: 1,
                branch_dest: None,
            },
        ),
@@ -715,7 +715,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 100,
                size: 4,
-                opcode: 19,
+                opcode: 7,
                branch_dest: None,
            },
        ),
@@ -729,7 +729,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 104,
                size: 2,
-                opcode: 66,
+                opcode: 116,
                branch_dest: None,
            },
        ),
@@ -743,7 +743,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 106,
                size: 2,
-                opcode: 47,
+                opcode: 43,
                branch_dest: None,
            },
        ),
@@ -757,7 +757,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 108,
                size: 4,
-                opcode: 19,
+                opcode: 7,
                branch_dest: None,
            },
        ),
@@ -771,7 +771,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 112,
                size: 2,
-                opcode: 47,
+                opcode: 43,
                branch_dest: None,
            },
        ),
@@ -785,7 +785,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 114,
                size: 2,
-                opcode: 6,
+                opcode: 1,
                branch_dest: None,
            },
        ),
@@ -799,7 +799,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 116,
                size: 2,
-                opcode: 66,
+                opcode: 116,
                branch_dest: None,
            },
        ),
@@ -813,7 +813,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 118,
                size: 2,
-                opcode: 35,
+                opcode: 24,
                branch_dest: None,
            },
        ),
@@ -827,7 +827,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 120,
                size: 2,
-                opcode: 47,
+                opcode: 43,
                branch_dest: None,
            },
        ),
@@ -841,7 +841,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 122,
                size: 2,
-                opcode: 47,
+                opcode: 43,
                branch_dest: None,
            },
        ),
@@ -855,7 +855,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 124,
                size: 2,
-                opcode: 47,
+                opcode: 43,
                branch_dest: None,
            },
        ),
@@ -869,7 +869,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 126,
                size: 4,
-                opcode: 19,
+                opcode: 7,
                branch_dest: None,
            },
        ),
@@ -883,7 +883,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 130,
                size: 2,
-                opcode: 25,
+                opcode: 16,
                branch_dest: None,
            },
        ),
@@ -897,7 +897,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 132,
                size: 2,
-                opcode: 15,
+                opcode: 4,
                branch_dest: Some(
                    168,
                ),
@@ -918,7 +918,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 134,
                size: 2,
-                opcode: 47,
+                opcode: 43,
                branch_dest: None,
            },
        ),
@@ -932,7 +932,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 136,
                size: 4,
-                opcode: 19,
+                opcode: 7,
                branch_dest: None,
            },
        ),
@@ -946,7 +946,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 140,
                size: 2,
-                opcode: 47,
+                opcode: 43,
                branch_dest: None,
            },
        ),
@@ -960,7 +960,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 142,
                size: 2,
-                opcode: 25,
+                opcode: 16,
                branch_dest: None,
            },
        ),
@@ -974,7 +974,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 144,
                size: 2,
-                opcode: 15,
+                opcode: 4,
                branch_dest: Some(
                    168,
                ),
@@ -995,7 +995,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 146,
                size: 2,
-                opcode: 34,
+                opcode: 24,
                branch_dest: None,
            },
        ),
@@ -1009,7 +1009,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 148,
                size: 2,
-                opcode: 33,
+                opcode: 24,
                branch_dest: None,
            },
        ),
@@ -1023,7 +1023,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 150,
                size: 2,
-                opcode: 36,
+                opcode: 25,
                branch_dest: None,
            },
        ),
@@ -1037,7 +1037,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 152,
                size: 2,
-                opcode: 42,
+                opcode: 36,
                branch_dest: None,
            },
        ),
@@ -1051,7 +1051,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 154,
                size: 2,
-                opcode: 44,
+                opcode: 37,
                branch_dest: None,
            },
        ),
@@ -1065,7 +1065,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 156,
                size: 2,
-                opcode: 15,
+                opcode: 4,
                branch_dest: Some(
                    168,
                ),
@@ -1086,7 +1086,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 158,
                size: 2,
-                opcode: 46,
+                opcode: 43,
                branch_dest: None,
            },
        ),
@@ -1100,7 +1100,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 160,
                size: 2,
-                opcode: 17,
+                opcode: 5,
                branch_dest: None,
            },
        ),
@@ -1114,7 +1114,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 162,
                size: 2,
-                opcode: 46,
+                opcode: 43,
                branch_dest: None,
            },
        ),
@@ -1142,7 +1142,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 166,
                size: 2,
-                opcode: 67,
+                opcode: 117,
                branch_dest: None,
            },
        ),
@@ -1156,7 +1156,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 168,
                size: 2,
-                opcode: 25,
+                opcode: 16,
                branch_dest: None,
            },
        ),
@@ -1179,7 +1179,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 170,
                size: 2,
-                opcode: 15,
+                opcode: 4,
                branch_dest: Some(
                    200,
                ),
@@ -1200,7 +1200,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 172,
                size: 2,
-                opcode: 35,
+                opcode: 24,
                branch_dest: None,
            },
        ),
@@ -1214,7 +1214,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 174,
                size: 2,
-                opcode: 25,
+                opcode: 16,
                branch_dest: None,
            },
        ),
@@ -1228,7 +1228,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 176,
                size: 2,
-                opcode: 15,
+                opcode: 4,
                branch_dest: Some(
                    200,
                ),
@@ -1249,7 +1249,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 178,
                size: 2,
-                opcode: 34,
+                opcode: 24,
                branch_dest: None,
            },
        ),
@@ -1263,7 +1263,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 180,
                size: 2,
-                opcode: 37,
+                opcode: 25,
                branch_dest: None,
            },
        ),
@@ -1277,7 +1277,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 182,
                size: 2,
-                opcode: 42,
+                opcode: 36,
                branch_dest: None,
            },
        ),
@@ -1291,7 +1291,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 184,
                size: 2,
-                opcode: 44,
+                opcode: 37,
                branch_dest: None,
            },
        ),
@@ -1305,7 +1305,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 186,
                size: 2,
-                opcode: 15,
+                opcode: 4,
                branch_dest: Some(
                    200,
                ),
@@ -1326,7 +1326,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 188,
                size: 2,
-                opcode: 32,
+                opcode: 24,
                branch_dest: None,
            },
        ),
@@ -1340,7 +1340,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 190,
                size: 2,
-                opcode: 34,
+                opcode: 24,
                branch_dest: None,
            },
        ),
@@ -1354,7 +1354,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 192,
                size: 2,
-                opcode: 46,
+                opcode: 43,
                branch_dest: None,
            },
        ),
@@ -1368,7 +1368,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 194,
                size: 2,
-                opcode: 46,
+                opcode: 43,
                branch_dest: None,
            },
        ),
@@ -1382,7 +1382,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 196,
                size: 4,
-                opcode: 19,
+                opcode: 7,
                branch_dest: None,
            },
        ),
@@ -1396,7 +1396,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 200,
                size: 2,
-                opcode: 34,
+                opcode: 24,
                branch_dest: None,
            },
        ),
@@ -1419,7 +1419,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 202,
                size: 2,
-                opcode: 35,
+                opcode: 24,
                branch_dest: None,
            },
        ),
@@ -1433,7 +1433,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 204,
                size: 2,
-                opcode: 34,
+                opcode: 24,
                branch_dest: None,
            },
        ),
@@ -1447,7 +1447,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 206,
                size: 2,
-                opcode: 4,
+                opcode: 1,
                branch_dest: None,
            },
        ),
@@ -1461,7 +1461,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 208,
                size: 4,
-                opcode: 19,
+                opcode: 7,
                branch_dest: None,
            },
        ),
@@ -1475,7 +1475,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 212,
                size: 2,
-                opcode: 7,
+                opcode: 1,
                branch_dest: None,
            },
        ),
@@ -1498,7 +1498,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 214,
                size: 2,
-                opcode: 55,
+                opcode: 58,
                branch_dest: None,
            },
        ),
--- a/objdiff-core/tests/snapshots/arch_arm__read_thumb-3.snap
+++ b/objdiff-core/tests/snapshots/arch_arm__read_thumb-3.snap
@@ -2,109 +2,109 @@
 source: objdiff-core/tests/arch_arm.rs
 expression: output
 ---
-[(Line(37), Dim, 5), (Address(0), Dim, 5), (Spacing(4), Normal, 0), (Opcode("push", 56), Normal, 10), (Basic("{"), Normal, 0), (Argument(Opaque("r3")), Normal, 0), (Basic(", "), Normal, 0), (Argument(Opaque("r4")), Normal, 0), (Basic(", "), Normal, 0), (Argument(Opaque("r5")), Normal, 0), (Basic(", "), Normal, 0), (Argument(Opaque("r6")), Normal, 0), (Basic(", "), Normal, 0), (Argument(Opaque("r7")), Normal, 0), (Basic(", "), Normal, 0), (Argument(Opaque("lr")), Normal, 0), (Basic("}"), Normal, 0), (Eol, Normal, 0)]
-[(Line(37), Dim, 5), (Address(2), Dim, 5), (Spacing(4), Normal, 0), (Opcode("sub", 74), Normal, 10), (Argument(Opaque("sp")), Normal, 0), (Basic(", "), Normal, 0), (Argument(Opaque("sp")), Normal, 0), (Basic(", "), Normal, 0), (Basic("#"), Normal, 0), (Argument(Signed(16)), Normal, 0), (Eol, Normal, 0)]
-[(Line(37), Dim, 5), (Address(4), Dim, 5), (Spacing(4), Normal, 0), (Opcode("mov", 47), Normal, 10), (Argument(Opaque("r5")), Normal, 0), (Basic(", "), Normal, 0), (Argument(Opaque("r0")), Normal, 0), (Eol, Normal, 0)]
-[(Line(39), Dim, 5), (Address(6), Dim, 5), (Spacing(4), Normal, 0), (Opcode("mov", 47), Normal, 10), (Argument(Opaque("r0")), Normal, 0), (Basic(", "), Normal, 0), (Argument(Opaque("r3")), Normal, 0), (Eol, Normal, 0)]
-[(Line(39), Dim, 5), (Address(8), Dim, 5), (Spacing(4), Normal, 0), (Opcode("mov", 47), Normal, 10), (Argument(Opaque("r4")), Normal, 0), (Basic(", "), Normal, 0), (Argument(Opaque("r1")), Normal, 0), (Eol, Normal, 0)]
-[(Line(39), Dim, 5), (Address(10), Dim, 5), (Spacing(4), Normal, 0), (Opcode("mov", 47), Normal, 10), (Argument(Opaque("r6")), Normal, 0), (Basic(", "), Normal, 0), (Argument(Opaque("r2")), Normal, 0), (Eol, Normal, 0)]
-[(Line(39), Dim, 5), (Address(12), Dim, 5), (Spacing(4), Normal, 0), (Opcode("str", 66), Normal, 10), (Argument(Opaque("r3")), Normal, 0), (Basic(", "), Normal, 0), (Basic("["), Normal, 0), (Argument(Opaque("sp")), Normal, 0), (Basic(", "), Normal, 0), (Basic("#"), Normal, 0), (Argument(Signed(4)), Normal, 0), (Basic("]"), Normal, 0), (Eol, Normal, 0)]
-[(Line(39), Dim, 5), (Address(14), Dim, 5), (Spacing(4), Normal, 0), (Opcode("bl", 19), Normal, 10), (Symbol(Symbol { name: "PokeSet_IsRemovedAll", demangled_name: None, address: 0, size: 0, kind: Unknown, section: None, flags: FlagSet(Global), align: None, virtual_address: None }), Bright, 0), (Addend(-4), Bright, 0), (Eol, Normal, 0)]
-[(Line(39), Dim, 5), (Address(18), Dim, 5), (Spacing(4), Normal, 0), (Opcode("cmp", 25), Normal, 10), (Argument(Opaque("r0")), Normal, 0), (Basic(", "), Normal, 0), (Basic("#"), Normal, 0), (Argument(Unsigned(0)), Normal, 0), (Eol, Normal, 0)]
-[(Line(39), Dim, 5), (Address(20), Dim, 5), (Spacing(4), Normal, 0), (Opcode("bne", 15), Normal, 10), (BranchDest(212), Normal, 0), (Basic(" ~>"), Rotating(0), 0), (Eol, Normal, 0)]
-[(Line(44), Dim, 5), (Address(22), Dim, 5), (Spacing(4), Normal, 0), (Opcode("ldrh", 38), Normal, 10), (Argument(Opaque("r1")), Normal, 0), (Basic(", "), Normal, 0), (Basic("["), Normal, 0), (Argument(Opaque("r4")), Normal, 0), (Basic(", "), Normal, 0), (Basic("#"), Normal, 0), (Argument(Signed(0)), Normal, 0), (Basic("]"), Normal, 0), (Eol, Normal, 0)]
-[(Line(44), Dim, 5), (Address(24), Dim, 5), (Spacing(4), Normal, 0), (Opcode("cmp", 25), Normal, 10), (Argument(Opaque("r1")), Normal, 0), (Basic(", "), Normal, 0), (Basic("#"), Normal, 0), (Argument(Unsigned(164)), Normal, 0), (Eol, Normal, 0)]
-[(Line(44), Dim, 5), (Address(26), Dim, 5), (Spacing(4), Normal, 0), (Opcode("beq", 15), Normal, 10), (BranchDest(48), Normal, 0), (Basic(" ~>"), Rotating(1), 0), (Eol, Normal, 0)]
-[(Line(44), Dim, 5), (Address(28), Dim, 5), (Spacing(4), Normal, 0), (Opcode("ldr", 34), Normal, 10), (Argument(Opaque("r0")), Normal, 0), (Basic(", "), Normal, 0), (Basic("["), Normal, 0), (Argument(Opaque("pc")), Normal, 0), (Basic(", "), Normal, 0), (Basic("#"), Normal, 0), (Argument(Signed(184)), Normal, 0), (Basic("]"), Normal, 0), (Basic(" (->"), Normal, 0), (BranchDest(216), Normal, 0), (Basic(")"), Normal, 0), (Eol, Normal, 0)]
-[(Line(44), Dim, 5), (Address(30), Dim, 5), (Spacing(4), Normal, 0), (Opcode("cmp", 26), Normal, 10), (Argument(Opaque("r1")), Normal, 0), (Basic(", "), Normal, 0), (Argument(Opaque("r0")), Normal, 0), (Eol, Normal, 0)]
-[(Line(44), Dim, 5), (Address(32), Dim, 5), (Spacing(4), Normal, 0), (Opcode("bne", 15), Normal, 10), (BranchDest(94), Normal, 0), (Basic(" ~>"), Rotating(2), 0), (Eol, Normal, 0)]
-[(Line(47), Dim, 5), (Address(34), Dim, 5), (Spacing(4), Normal, 0), (Opcode("ldr", 35), Normal, 10), (Argument(Opaque("r2")), Normal, 0), (Basic(", "), Normal, 0), (Basic("["), Normal, 0), (Argument(Opaque("sp")), Normal, 0), (Basic(", "), Normal, 0), (Basic("#"), Normal, 0), (Argument(Signed(4)), Normal, 0), (Basic("]"), Normal, 0), (Eol, Normal, 0)]
-[(Line(47), Dim, 5), (Address(36), Dim, 5), (Spacing(4), Normal, 0), (Opcode("mov", 47), Normal, 10), (Argument(Opaque("r0")), Normal, 0), (Basic(", "), Normal, 0), (Argument(Opaque("r5")), Normal, 0), (Eol, Normal, 0)]
-[(Line(47), Dim, 5), (Address(38), Dim, 5), (Spacing(4), Normal, 0), (Opcode("mov", 47), Normal, 10), (Argument(Opaque("r1")), Normal, 0), (Basic(", "), Normal, 0), (Argument(Opaque("r6")), Normal, 0), (Eol, Normal, 0)]
-[(Line(47), Dim, 5), (Address(40), Dim, 5), (Spacing(4), Normal, 0), (Opcode("bl", 19), Normal, 10), (Symbol(Symbol { name: "ServerDisplay_SkillSwap", demangled_name: None, address: 0, size: 0, kind: Unknown, section: None, flags: FlagSet(Global), align: None, virtual_address: None }), Bright, 0), (Addend(-4), Bright, 0), (Eol, Normal, 0)]
-[(Line(86), Dim, 5), (Address(44), Dim, 5), (Spacing(4), Normal, 0), (Opcode("add", 7), Normal, 10), (Argument(Opaque("sp")), Normal, 0), (Basic(", "), Normal, 0), (Basic("#"), Normal, 0), (Argument(Signed(16)), Normal, 0), (Eol, Normal, 0)]
-[(Line(86), Dim, 5), (Address(46), Dim, 5), (Spacing(4), Normal, 0), (Opcode("pop", 55), Normal, 10), (Basic("{"), Normal, 0), (Argument(Opaque("r3")), Normal, 0), (Basic(", "), Normal, 0), (Argument(Opaque("r4")), Normal, 0), (Basic(", "), Normal, 0), (Argument(Opaque("r5")), Normal, 0), (Basic(", "), Normal, 0), (Argument(Opaque("r6")), Normal, 0), (Basic(", "), Normal, 0), (Argument(Opaque("r7")), Normal, 0), (Basic(", "), Normal, 0), (Argument(Opaque("pc")), Normal, 0), (Basic("}"), Normal, 0), (Eol, Normal, 0)]
-[(Line(50), Dim, 5), (Address(48), Dim, 5), (Basic(" ~> "), Rotating(1), 0), (Opcode("mov", 47), Normal, 10), (Argument(Opaque("r0")), Normal, 0), (Basic(", "), Normal, 0), (Argument(Opaque("r5")), Normal, 0), (Eol, Normal, 0)]
-[(Line(50), Dim, 5), (Address(50), Dim, 5), (Spacing(4), Normal, 0), (Opcode("mov", 47), Normal, 10), (Argument(Opaque("r1")), Normal, 0), (Basic(", "), Normal, 0), (Argument(Opaque("r6")), Normal, 0), (Eol, Normal, 0)]
-[(Line(50), Dim, 5), (Address(52), Dim, 5), (Spacing(4), Normal, 0), (Opcode("bl", 19), Normal, 10), (Symbol(Symbol { name: "ServerEvent_CreateSubstitute", demangled_name: None, address: 0, size: 0, kind: Unknown, section: None, flags: FlagSet(Global), align: None, virtual_address: None }), Bright, 0), (Addend(-4), Bright, 0), (Eol, Normal, 0)]
-[(Line(50), Dim, 5), (Address(56), Dim, 5), (Spacing(4), Normal, 0), (Opcode("cmp", 25), Normal, 10), (Argument(Opaque("r0")), Normal, 0), (Basic(", "), Normal, 0), (Basic("#"), Normal, 0), (Argument(Unsigned(0)), Normal, 0), (Eol, Normal, 0)]
-[(Line(50), Dim, 5), (Address(58), Dim, 5), (Spacing(4), Normal, 0), (Opcode("beq", 15), Normal, 10), (BranchDest(212), Normal, 0), (Basic(" ~>"), Rotating(0), 0), (Eol, Normal, 0)]
-[(Line(52), Dim, 5), (Address(60), Dim, 5), (Spacing(4), Normal, 0), (Opcode("ldr", 34), Normal, 10), (Argument(Opaque("r0")), Normal, 0), (Basic(", "), Normal, 0), (Basic("["), Normal, 0), (Argument(Opaque("pc")), Normal, 0), (Basic(", "), Normal, 0), (Basic("#"), Normal, 0), (Argument(Signed(156)), Normal, 0), (Basic("]"), Normal, 0), (Basic(" (->"), Normal, 0), (BranchDest(220), Normal, 0), (Basic(")"), Normal, 0), (Eol, Normal, 0)]
-[(Line(52), Dim, 5), (Address(62), Dim, 5), (Spacing(4), Normal, 0), (Opcode("ldr", 33), Normal, 10), (Argument(Opaque("r0")), Normal, 0), (Basic(", "), Normal, 0), (Basic("["), Normal, 0), (Argument(Opaque("r5")), Normal, 0), (Basic(", "), Normal, 0), (Argument(Opaque("r0")), Normal, 0), (Basic("]"), Normal, 0), (Eol, Normal, 0)]
-[(Line(52), Dim, 5), (Address(64), Dim, 5), (Spacing(4), Normal, 0), (Opcode("ldrb", 36), Normal, 10), (Argument(Opaque("r2")), Normal, 0), (Basic(", "), Normal, 0), (Basic("["), Normal, 0), (Argument(Opaque("r0")), Normal, 0), (Basic(", "), Normal, 0), (Basic("#"), Normal, 0), (Argument(Signed(5)), Normal, 0), (Basic("]"), Normal, 0), (Eol, Normal, 0)]
-[(Line(52), Dim, 5), (Address(66), Dim, 5), (Spacing(4), Normal, 0), (Opcode("lsl", 42), Normal, 10), (Argument(Opaque("r1")), Normal, 0), (Basic(", "), Normal, 0), (Argument(Opaque("r2")), Normal, 0), (Basic(", "), Normal, 0), (Basic("#"), Normal, 0), (Argument(Unsigned(31)), Normal, 0), (Eol, Normal, 0)]
-[(Line(52), Dim, 5), (Address(68), Dim, 5), (Spacing(4), Normal, 0), (Opcode("lsr", 44), Normal, 10), (Argument(Opaque("r1")), Normal, 0), (Basic(", "), Normal, 0), (Argument(Opaque("r1")), Normal, 0), (Basic(", "), Normal, 0), (Basic("#"), Normal, 0), (Argument(Unsigned(31)), Normal, 0), (Eol, Normal, 0)]
-[(Line(52), Dim, 5), (Address(70), Dim, 5), (Spacing(4), Normal, 0), (Opcode("bne", 15), Normal, 10), (BranchDest(212), Normal, 0), (Basic(" ~>"), Rotating(0), 0), (Eol, Normal, 0)]
-[(Line(52), Dim, 5), (Address(72), Dim, 5), (Spacing(4), Normal, 0), (Opcode("mov", 46), Normal, 10), (Argument(Opaque("r1")), Normal, 0), (Basic(", "), Normal, 0), (Basic("#"), Normal, 0), (Argument(Unsigned(1)), Normal, 0), (Eol, Normal, 0)]
-[(Line(52), Dim, 5), (Address(74), Dim, 5), (Spacing(4), Normal, 0), (Opcode("bic", 17), Normal, 10), (Argument(Opaque("r2")), Normal, 0), (Basic(", "), Normal, 0), (Argument(Opaque("r1")), Normal, 0), (Eol, Normal, 0)]
-[(Line(52), Dim, 5), (Address(76), Dim, 5), (Spacing(4), Normal, 0), (Opcode("mov", 46), Normal, 10), (Argument(Opaque("r1")), Normal, 0), (Basic(", "), Normal, 0), (Basic("#"), Normal, 0), (Argument(Unsigned(1)), Normal, 0), (Eol, Normal, 0)]
+[(Line(37), Dim, 5), (Address(0), Dim, 5), (Spacing(4), Normal, 0), (Opcode("push", 59), Normal, 10), (Basic("{"), Normal, 0), (Argument(Opaque("r3")), Normal, 0), (Basic(", "), Normal, 0), (Argument(Opaque("r4")), Normal, 0), (Basic(", "), Normal, 0), (Argument(Opaque("r5")), Normal, 0), (Basic(", "), Normal, 0), (Argument(Opaque("r6")), Normal, 0), (Basic(", "), Normal, 0), (Argument(Opaque("r7")), Normal, 0), (Basic(", "), Normal, 0), (Argument(Opaque("lr")), Normal, 0), (Basic("}"), Normal, 0), (Eol, Normal, 0)]
+[(Line(37), Dim, 5), (Address(2), Dim, 5), (Spacing(4), Normal, 0), (Opcode("sub", 126), Normal, 10), (Argument(Opaque("sp")), Normal, 0), (Basic(", "), Normal, 0), (Basic("#"), Normal, 0), (Argument(Unsigned(16)), Normal, 0), (Eol, Normal, 0)]
+[(Line(37), Dim, 5), (Address(4), Dim, 5), (Spacing(4), Normal, 0), (Opcode("mov", 43), Normal, 10), (Argument(Opaque("r5")), Normal, 0), (Basic(", "), Normal, 0), (Argument(Opaque("r0")), Normal, 0), (Eol, Normal, 0)]
+[(Line(39), Dim, 5), (Address(6), Dim, 5), (Spacing(4), Normal, 0), (Opcode("mov", 43), Normal, 10), (Argument(Opaque("r0")), Normal, 0), (Basic(", "), Normal, 0), (Argument(Opaque("r3")), Normal, 0), (Eol, Normal, 0)]
+[(Line(39), Dim, 5), (Address(8), Dim, 5), (Spacing(4), Normal, 0), (Opcode("mov", 43), Normal, 10), (Argument(Opaque("r4")), Normal, 0), (Basic(", "), Normal, 0), (Argument(Opaque("r1")), Normal, 0), (Eol, Normal, 0)]
+[(Line(39), Dim, 5), (Address(10), Dim, 5), (Spacing(4), Normal, 0), (Opcode("mov", 43), Normal, 10), (Argument(Opaque("r6")), Normal, 0), (Basic(", "), Normal, 0), (Argument(Opaque("r2")), Normal, 0), (Eol, Normal, 0)]
+[(Line(39), Dim, 5), (Address(12), Dim, 5), (Spacing(4), Normal, 0), (Opcode("str", 116), Normal, 10), (Argument(Opaque("r3")), Normal, 0), (Basic(", "), Normal, 0), (Basic("["), Normal, 0), (Argument(Opaque("sp")), Normal, 0), (Basic(", "), Normal, 0), (Basic("#"), Normal, 0), (Argument(Signed(4)), Normal, 0), (Basic("]"), Normal, 0), (Eol, Normal, 0)]
+[(Line(39), Dim, 5), (Address(14), Dim, 5), (Spacing(4), Normal, 0), (Opcode("bl", 7), Normal, 10), (Symbol(Symbol { name: "PokeSet_IsRemovedAll", demangled_name: None, address: 0, size: 0, kind: Unknown, section: None, flags: FlagSet(Global), align: None, virtual_address: None }), Bright, 0), (Addend(-4), Bright, 0), (Eol, Normal, 0)]
+[(Line(39), Dim, 5), (Address(18), Dim, 5), (Spacing(4), Normal, 0), (Opcode("cmp", 16), Normal, 10), (Argument(Opaque("r0")), Normal, 0), (Basic(", "), Normal, 0), (Basic("#"), Normal, 0), (Argument(Unsigned(0)), Normal, 0), (Eol, Normal, 0)]
+[(Line(39), Dim, 5), (Address(20), Dim, 5), (Spacing(4), Normal, 0), (Opcode("bne", 4), Normal, 10), (BranchDest(212), Normal, 0), (Basic(" ~>"), Rotating(0), 0), (Eol, Normal, 0)]
+[(Line(44), Dim, 5), (Address(22), Dim, 5), (Spacing(4), Normal, 0), (Opcode("ldrh", 32), Normal, 10), (Argument(Opaque("r1")), Normal, 0), (Basic(", "), Normal, 0), (Basic("["), Normal, 0), (Argument(Opaque("r4")), Normal, 0), (Basic(", "), Normal, 0), (Basic("#"), Normal, 0), (Argument(Signed(0)), Normal, 0), (Basic("]"), Normal, 0), (Eol, Normal, 0)]
+[(Line(44), Dim, 5), (Address(24), Dim, 5), (Spacing(4), Normal, 0), (Opcode("cmp", 16), Normal, 10), (Argument(Opaque("r1")), Normal, 0), (Basic(", "), Normal, 0), (Basic("#"), Normal, 0), (Argument(Unsigned(164)), Normal, 0), (Eol, Normal, 0)]
+[(Line(44), Dim, 5), (Address(26), Dim, 5), (Spacing(4), Normal, 0), (Opcode("beq", 4), Normal, 10), (BranchDest(48), Normal, 0), (Basic(" ~>"), Rotating(1), 0), (Eol, Normal, 0)]
+[(Line(44), Dim, 5), (Address(28), Dim, 5), (Spacing(4), Normal, 0), (Opcode("ldr", 24), Normal, 10), (Argument(Opaque("r0")), Normal, 0), (Basic(", "), Normal, 0), (Basic("["), Normal, 0), (Argument(Opaque("pc")), Normal, 0), (Basic(", "), Normal, 0), (Basic("#"), Normal, 0), (Argument(Signed(184)), Normal, 0), (Basic("]"), Normal, 0), (Basic(" (->"), Normal, 0), (BranchDest(216), Normal, 0), (Basic(")"), Normal, 0), (Eol, Normal, 0)]
+[(Line(44), Dim, 5), (Address(30), Dim, 5), (Spacing(4), Normal, 0), (Opcode("cmp", 16), Normal, 10), (Argument(Opaque("r1")), Normal, 0), (Basic(", "), Normal, 0), (Argument(Opaque("r0")), Normal, 0), (Eol, Normal, 0)]
+[(Line(44), Dim, 5), (Address(32), Dim, 5), (Spacing(4), Normal, 0), (Opcode("bne", 4), Normal, 10), (BranchDest(94), Normal, 0), (Basic(" ~>"), Rotating(2), 0), (Eol, Normal, 0)]
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+[(Line(75), Dim, 5), (Address(184), Dim, 5), (Spacing(4), Normal, 0), (Opcode("lsr", 37), Normal, 10), (Argument(Opaque("r0")), Normal, 0), (Basic(", "), Normal, 0), (Basic("#"), Normal, 0), (Argument(Unsigned(31)), Normal, 0), (Eol, Normal, 0)]
+[(Line(75), Dim, 5), (Address(186), Dim, 5), (Spacing(4), Normal, 0), (Opcode("bne", 4), Normal, 10), (BranchDest(200), Normal, 0), (Basic(" ~>"), Rotating(4), 0), (Eol, Normal, 0)]
+[(Line(77), Dim, 5), (Address(188), Dim, 5), (Spacing(4), Normal, 0), (Opcode("ldr", 24), Normal, 10), (Argument(Opaque("r0")), Normal, 0), (Basic(", "), Normal, 0), (Basic("["), Normal, 0), (Argument(Opaque("r5")), Normal, 0), (Basic(", "), Normal, 0), (Basic("#"), Normal, 0), (Argument(Signed(12)), Normal, 0), (Basic("]"), Normal, 0), (Eol, Normal, 0)]
+[(Line(77), Dim, 5), (Address(190), Dim, 5), (Spacing(4), Normal, 0), (Opcode("ldr", 24), Normal, 10), (Argument(Opaque("r3")), Normal, 0), (Basic(", "), Normal, 0), (Basic("["), Normal, 0), (Argument(Opaque("pc")), Normal, 0), (Basic(", "), Normal, 0), (Basic("#"), Normal, 0), (Argument(Signed(44)), Normal, 0), (Basic("]"), Normal, 0), (Basic(" (->"), Normal, 0), (BranchDest(236), Normal, 0), (Basic(")"), Normal, 0), (Eol, Normal, 0)]
+[(Line(77), Dim, 5), (Address(192), Dim, 5), (Spacing(4), Normal, 0), (Opcode("mov", 43), Normal, 10), (Argument(Opaque("r1")), Normal, 0), (Basic(", "), Normal, 0), (Basic("#"), Normal, 0), (Argument(Unsigned(90)), Normal, 0), (Eol, Normal, 0)]
+[(Line(77), Dim, 5), (Address(194), Dim, 5), (Spacing(4), Normal, 0), (Opcode("mov", 43), Normal, 10), (Argument(Opaque("r2")), Normal, 0), (Basic(", "), Normal, 0), (Basic("#"), Normal, 0), (Argument(Unsigned(71)), Normal, 0), (Eol, Normal, 0)]
+[(Line(77), Dim, 5), (Address(196), Dim, 5), (Spacing(4), Normal, 0), (Opcode("bl", 7), Normal, 10), (Symbol(Symbol { name: "SCQUE_PUT_MsgImpl", demangled_name: None, address: 0, size: 0, kind: Unknown, section: None, flags: FlagSet(Global), align: None, virtual_address: None }), Bright, 0), (Addend(-4), Bright, 0), (Eol, Normal, 0)]
+[(Line(81), Dim, 5), (Address(200), Dim, 5), (Basic(" ~> "), Rotating(4), 0), (Opcode("ldr", 24), Normal, 10), (Argument(Opaque("r0")), Normal, 0), (Basic(", "), Normal, 0), (Basic("["), Normal, 0), (Argument(Opaque("pc")), Normal, 0), (Basic(", "), Normal, 0), (Basic("#"), Normal, 0), (Argument(Signed(20)), Normal, 0), (Basic("]"), Normal, 0), (Basic(" (->"), Normal, 0), (BranchDest(224), Normal, 0), (Basic(")"), Normal, 0), (Eol, Normal, 0)]
+[(Line(81), Dim, 5), (Address(202), Dim, 5), (Spacing(4), Normal, 0), (Opcode("ldr", 24), Normal, 10), (Argument(Opaque("r1")), Normal, 0), (Basic(", "), Normal, 0), (Basic("["), Normal, 0), (Argument(Opaque("sp")), Normal, 0), (Basic(", "), Normal, 0), (Basic("#"), Normal, 0), (Argument(Signed(8)), Normal, 0), (Basic("]"), Normal, 0), (Eol, Normal, 0)]
+[(Line(81), Dim, 5), (Address(204), Dim, 5), (Spacing(4), Normal, 0), (Opcode("ldr", 24), Normal, 10), (Argument(Opaque("r2")), Normal, 0), (Basic(", "), Normal, 0), (Basic("["), Normal, 0), (Argument(Opaque("pc")), Normal, 0), (Basic(", "), Normal, 0), (Basic("#"), Normal, 0), (Argument(Signed(32)), Normal, 0), (Basic("]"), Normal, 0), (Basic(" (->"), Normal, 0), (BranchDest(240), Normal, 0), (Basic(")"), Normal, 0), (Eol, Normal, 0)]
+[(Line(81), Dim, 5), (Address(206), Dim, 5), (Spacing(4), Normal, 0), (Opcode("add", 1), Normal, 10), (Argument(Opaque("r0")), Normal, 0), (Basic(", "), Normal, 0), (Argument(Opaque("r5")), Normal, 0), (Basic(", "), Normal, 0), (Argument(Opaque("r0")), Normal, 0), (Eol, Normal, 0)]
+[(Line(81), Dim, 5), (Address(208), Dim, 5), (Spacing(4), Normal, 0), (Opcode("bl", 7), Normal, 10), (Symbol(Symbol { name: "HEManager_PopState", demangled_name: None, address: 0, size: 0, kind: Unknown, section: None, flags: FlagSet(Global), align: None, virtual_address: None }), Bright, 0), (Addend(-4), Bright, 0), (Eol, Normal, 0)]
+[(Line(86), Dim, 5), (Address(212), Dim, 5), (Basic(" ~> "), Rotating(0), 0), (Opcode("add", 1), Normal, 10), (Argument(Opaque("sp")), Normal, 0), (Basic(", "), Normal, 0), (Basic("#"), Normal, 0), (Argument(Unsigned(16)), Normal, 0), (Eol, Normal, 0)]
+[(Line(86), Dim, 5), (Address(214), Dim, 5), (Spacing(4), Normal, 0), (Opcode("pop", 58), Normal, 10), (Basic("{"), Normal, 0), (Argument(Opaque("r3")), Normal, 0), (Basic(", "), Normal, 0), (Argument(Opaque("r4")), Normal, 0), (Basic(", "), Normal, 0), (Argument(Opaque("r5")), Normal, 0), (Basic(", "), Normal, 0), (Argument(Opaque("r6")), Normal, 0), (Basic(", "), Normal, 0), (Argument(Opaque("r7")), Normal, 0), (Basic(", "), Normal, 0), (Argument(Opaque("pc")), Normal, 0), (Basic("}"), Normal, 0), (Eol, Normal, 0)]
+[(Line(86), Dim, 5), (Address(216), Dim, 5), (Spacing(4), Normal, 0), (Opcode(".word", 65534), Normal, 10), (Argument(Unsigned(285)), Normal, 0), (Eol, Normal, 0)]
+[(Line(86), Dim, 5), (Address(220), Dim, 5), (Spacing(4), Normal, 0), (Opcode(".word", 65534), Normal, 10), (Argument(Unsigned(1192)), Normal, 0), (Eol, Normal, 0)]
+[(Line(86), Dim, 5), (Address(224), Dim, 5), (Spacing(4), Normal, 0), (Opcode(".word", 65534), Normal, 10), (Argument(Unsigned(7544)), Normal, 0), (Eol, Normal, 0)]
+[(Line(86), Dim, 5), (Address(228), Dim, 5), (Spacing(4), Normal, 0), (Opcode(".word", 65534), Normal, 10), (Argument(Unsigned(9103)), Normal, 0), (Eol, Normal, 0)]
+[(Line(86), Dim, 5), (Address(232), Dim, 5), (Spacing(4), Normal, 0), (Opcode(".word", 65534), Normal, 10), (Argument(Unsigned(1930)), Normal, 0), (Eol, Normal, 0)]
+[(Line(86), Dim, 5), (Address(236), Dim, 5), (Spacing(4), Normal, 0), (Opcode(".word", 65534), Normal, 10), (Argument(Unsigned(4294901760)), Normal, 0), (Eol, Normal, 0)]
+[(Line(86), Dim, 5), (Address(240), Dim, 5), (Spacing(4), Normal, 0), (Opcode(".word", 65534), Normal, 10), (Argument(Unsigned(9129)), Normal, 0), (Eol, Normal, 0)]
--- a/objdiff-core/tests/snapshots/arch_arm__trim_trailing_hword-2.snap
+++ b/objdiff-core/tests/snapshots/arch_arm__trim_trailing_hword-2.snap
@@ -2,6 +2,6 @@
 source: objdiff-core/tests/arch_arm.rs
 expression: output
 ---
-[(Address(0), Dim, 5), (Spacing(4), Normal, 0), (Opcode("str", 64), Normal, 10), (Argument(Opaque("r1")), Normal, 0), (Basic(", "), Normal, 0), (Basic("["), Normal, 0), (Argument(Opaque("r0")), Normal, 0), (Basic(", "), Normal, 0), (Basic("#"), Normal, 0), (Argument(Signed(36)), Normal, 0), (Basic("]"), Normal, 0), (Eol, Normal, 0)]
-[(Address(2), Dim, 5), (Spacing(4), Normal, 0), (Opcode("str", 64), Normal, 10), (Argument(Opaque("r2")), Normal, 0), (Basic(", "), Normal, 0), (Basic("["), Normal, 0), (Argument(Opaque("r0")), Normal, 0), (Basic(", "), Normal, 0), (Basic("#"), Normal, 0), (Argument(Signed(40)), Normal, 0), (Basic("]"), Normal, 0), (Eol, Normal, 0)]
-[(Address(4), Dim, 5), (Spacing(4), Normal, 0), (Opcode("bx", 23), Normal, 10), (Argument(Opaque("lr")), Normal, 0), (Eol, Normal, 0)]
+[(Address(0), Dim, 5), (Spacing(4), Normal, 0), (Opcode("str", 116), Normal, 10), (Argument(Opaque("r1")), Normal, 0), (Basic(", "), Normal, 0), (Basic("["), Normal, 0), (Argument(Opaque("r0")), Normal, 0), (Basic(", "), Normal, 0), (Basic("#"), Normal, 0), (Argument(Signed(36)), Normal, 0), (Basic("]"), Normal, 0), (Eol, Normal, 0)]
+[(Address(2), Dim, 5), (Spacing(4), Normal, 0), (Opcode("str", 116), Normal, 10), (Argument(Opaque("r2")), Normal, 0), (Basic(", "), Normal, 0), (Basic("["), Normal, 0), (Argument(Opaque("r0")), Normal, 0), (Basic(", "), Normal, 0), (Basic("#"), Normal, 0), (Argument(Signed(40)), Normal, 0), (Basic("]"), Normal, 0), (Eol, Normal, 0)]
+[(Address(4), Dim, 5), (Spacing(4), Normal, 0), (Opcode("bx", 9), Normal, 10), (Argument(Opaque("lr")), Normal, 0), (Eol, Normal, 0)]
--- a/objdiff-core/tests/snapshots/arch_arm__trim_trailing_hword.snap
+++ b/objdiff-core/tests/snapshots/arch_arm__trim_trailing_hword.snap
@@ -8,7 +8,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 0,
                size: 2,
-                opcode: 64,
+                opcode: 116,
                branch_dest: None,
            },
        ),
@@ -22,7 +22,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 2,
                size: 2,
-                opcode: 64,
+                opcode: 116,
                branch_dest: None,
            },
        ),
@@ -36,7 +36,7 @@ expression: diff.instruction_rows
            InstructionRef {
                address: 4,
                size: 2,
-                opcode: 23,
+                opcode: 9,
                branch_dest: None,
            },
        ),
--- a/objdiff-core/tests/snapshots/arch_ppc__read_extab.snap
+++ b/objdiff-core/tests/snapshots/arch_ppc__read_extab.snap
@@ -69,19 +69,19 @@ Object {
                                action_param: 0,
                                has_end_bit: true,
                                bytes: [
+                                    130,
+                                    0,
                                    0,
                                    8,
                                    0,
                                    0,
-                                    0,
-                                    0,
                                ],
                            },
                        ],
                        relocations: [
                            Relocation {
-                                offset: 20,
-                                address: 0,
+                                offset: 18,
+                                address: 524288,
                            },
                        ],
                    },
--- a/objdiff-gui/Cargo.toml
+++ b/objdiff-gui/Cargo.toml
@@ -30,9 +30,9 @@ cfg-if = "1.0"
 const_format = "0.2"
 cwdemangle = "1.0"
 dirs = "6.0"
-egui = "0.32"
-egui_extras = "0.32"
-egui-notify = "0.20"
+egui = "0.33"
+egui_extras = "0.33"
+egui-notify = "0.21"
 filetime = "0.2"
 float-ord = "0.3"
 font-kit = "0.14"
@@ -40,21 +40,21 @@ globset = { version = "0.4", features = ["serde1"] }
 log = "0.4"
 objdiff-core = { path = "../objdiff-core", features = ["all"] }
 open = "5.3"
-png = "0.17"
+png = "0.18"
 pollster = "0.4"
-regex = "1.11"
+regex = "1.12"
 rfd = { version = "0.15" } #, default-features = false, features = ['xdg-portal']
 rlwinmdec = "1.1"
-ron = "0.10"
+ron = "0.12"
 serde = { version = "1.0", features = ["derive"] }
 time = { version = "0.3", features = ["formatting", "local-offset"] }
-typed-path = "0.11"
+typed-path = "0.12"
 winit = { version = "0.30", features = ["default"] }
 tracing-subscriber = { version = "0.3", features = ["env-filter"] }

 # Keep version in sync with egui
 [dependencies.eframe]
-version = "0.32"
+version = "0.33"
 features = [
    "default_fonts",
    "glow",
@@ -66,7 +66,7 @@ default-features = false

 # Keep version in sync with eframe
 [dependencies.wgpu]
-version = "25.0"
+version = "27.0"
 features = [
    "dx12",
    "metal",
--- a/objdiff-gui/src/app_config.rs
+++ b/objdiff-gui/src/app_config.rs
@@ -6,7 +6,7 @@ use objdiff_core::{
    config::ScratchConfig,
    diff::{
        ArmArchVersion, ArmR9Usage, DiffObjConfig, FunctionRelocDiffs, MipsAbi, MipsInstrCategory,
-        X86Formatter,
+        ShowSymbolSizes, X86Formatter,
    },
 };
 use typed_path::{Utf8PlatformPathBuf, Utf8UnixPathBuf};
@@ -227,6 +227,7 @@ pub struct DiffObjConfigV1 {
    pub relax_reloc_diffs: bool,
    #[serde(default = "bool_true")]
    pub space_between_args: bool,
+    pub show_symbol_sizes: ShowSymbolSizes,
    pub combine_data_sections: bool,
    // x86
    pub x86_formatter: X86Formatter,
@@ -248,6 +249,7 @@ impl Default for DiffObjConfigV1 {
        Self {
            relax_reloc_diffs: false,
            space_between_args: true,
+            show_symbol_sizes: Default::default(),
            combine_data_sections: false,
            x86_formatter: Default::default(),
            mips_abi: Default::default(),
@@ -272,6 +274,7 @@ impl DiffObjConfigV1 {
                FunctionRelocDiffs::default()
            },
            space_between_args: self.space_between_args,
+            show_symbol_sizes: self.show_symbol_sizes,
            combine_data_sections: self.combine_data_sections,
            x86_formatter: self.x86_formatter,
            mips_abi: self.mips_abi,
--- a/objdiff-gui/src/main.rs
+++ b/objdiff-gui/src/main.rs
@@ -14,6 +14,7 @@ mod views;
 use std::{
    ffi::OsStr,
    fmt::Display,
+    io::Cursor,
    path::PathBuf,
    process::ExitCode,
    rc::Rc,
@@ -21,7 +22,7 @@ use std::{
    sync::{Arc, Mutex},
 };

-use anyhow::{Result, ensure};
+use anyhow::{Context, Result, ensure};
 use argp::{FromArgValue, FromArgs};
 use cfg_if::cfg_if;
 use objdiff_core::config::path::check_path_buf;
@@ -90,9 +91,9 @@ struct TopLevel {
 }

 fn load_icon() -> Result<egui::IconData> {
-    let decoder = png::Decoder::new(include_bytes!("../assets/icon_64.png").as_ref());
+    let decoder = png::Decoder::new(Cursor::new(include_bytes!("../assets/icon_64.png").as_ref()));
    let mut reader = decoder.read_info()?;
-    let mut buf = vec![0; reader.output_buffer_size()];
+    let mut buf = vec![0; reader.output_buffer_size().context("Buffer too large")?];
    let info = reader.next_frame(&mut buf)?;
    ensure!(info.bit_depth == png::BitDepth::Eight);
    ensure!(info.color_type == png::ColorType::Rgba);
--- a/objdiff-gui/src/views/diff.rs
+++ b/objdiff-gui/src/views/diff.rs
@@ -1,12 +1,18 @@
+use std::cmp::Ordering;
+
 use egui::{Id, Layout, RichText, ScrollArea, TextEdit, Ui, Widget, text::LayoutJob};
 use objdiff_core::{
    build::BuildStatus,
    diff::{
        DiffObjConfig, ObjectDiff, SymbolDiff,
        data::BYTES_PER_ROW,
-        display::{ContextItem, HoverItem, HoverItemColor, SymbolFilter, SymbolNavigationKind},
+        display::{
+            ContextItem, DiffText, HoverItem, HoverItemColor, SymbolFilter, SymbolNavigationKind,
+            display_row,
+        },
    },
-    obj::{Object, Symbol},
+    obj::{InstructionArgValue, Object, Symbol},
+    util::ReallySigned,
 };
 use time::format_description;

@@ -64,6 +70,51 @@ impl<'a> DiffColumnContext<'a> {
    pub fn id(&self) -> Option<&str> { self.symbol.map(|(symbol, _, _)| symbol.name.as_str()) }
 }

+/// Obtains the assembly text for a given symbol diff, suitable for copying to clipboard.
+fn get_asm_text(
+    obj: &Object,
+    symbol_diff: &SymbolDiff,
+    symbol_idx: usize,
+    diff_config: &DiffObjConfig,
+) -> String {
+    let mut asm_text = String::new();
+
+    for ins_row in &symbol_diff.instruction_rows {
+        let mut line = String::new();
+        let result = display_row(obj, symbol_idx, ins_row, diff_config, |segment| {
+            let text = match segment.text {
+                DiffText::Basic(text) => text.to_string(),
+                DiffText::Line(num) => format!("{num} "),
+                DiffText::Address(addr) => format!("{addr:x}:"),
+                DiffText::Opcode(mnemonic, _op) => format!("{mnemonic} "),
+                DiffText::Argument(arg) => match arg {
+                    InstructionArgValue::Signed(v) => format!("{:#x}", ReallySigned(v)),
+                    InstructionArgValue::Unsigned(v) => format!("{v:#x}"),
+                    InstructionArgValue::Opaque(v) => v.into_owned(),
+                },
+                DiffText::BranchDest(addr) => format!("{addr:x}"),
+                DiffText::Symbol(sym) => sym.demangled_name.as_ref().unwrap_or(&sym.name).clone(),
+                DiffText::Addend(addend) => match addend.cmp(&0i64) {
+                    Ordering::Greater => format!("+{addend:#x}"),
+                    Ordering::Less => format!("-{:#x}", -addend),
+                    _ => String::new(),
+                },
+                DiffText::Spacing(n) => " ".repeat(n.into()),
+                DiffText::Eol => "\n".to_string(),
+            };
+            line.push_str(&text);
+            Ok(())
+        });
+
+        if result.is_ok() {
+            asm_text.push_str(line.trim_end());
+            asm_text.push('\n');
+        }
+    }
+
+    asm_text
+}
+
 #[must_use]
 pub fn diff_view_ui(
    ui: &mut Ui,
@@ -162,6 +213,17 @@ pub fn diff_view_ui(
                            ret = Some(DiffViewAction::CreateScratch(symbol.name.clone()));
                        }
                    }
+
+                    if state.current_view == View::FunctionDiff
+                        && let Some((_, symbol_diff, symbol_idx)) = left_ctx.symbol
+                        && let Some((obj, _)) = left_ctx.obj
+                        && ui
+                            .button("📋 Copy")
+                            .on_hover_text_at_pointer("Copy all rows to clipboard")
+                            .clicked()
+                    {
+                        ui.ctx().copy_text(get_asm_text(obj, symbol_diff, symbol_idx, diff_config));
+                    }
                });
            }

@@ -208,16 +270,20 @@ pub fn diff_view_ui(

            // Third row
            if left_ctx.has_symbol() && right_ctx.has_symbol() {
-                if (state.current_view == View::FunctionDiff
-                    && ui
-                        .button("Change target")
-                        .on_hover_text_at_pointer("Choose a different symbol to use as the target")
-                        .clicked()
-                    || hotkeys::consume_change_target_shortcut(ui.ctx()))
-                    && let Some(symbol_ref) = state.symbol_state.right_symbol.as_ref()
-                {
-                    ret = Some(DiffViewAction::SelectingLeft(symbol_ref.clone()));
-                }
+                ui.horizontal(|ui| {
+                    if (state.current_view == View::FunctionDiff
+                        && ui
+                            .button("Change target")
+                            .on_hover_text_at_pointer(
+                                "Choose a different symbol to use as the target",
+                            )
+                            .clicked()
+                        || hotkeys::consume_change_target_shortcut(ui.ctx()))
+                        && let Some(symbol_ref) = state.symbol_state.right_symbol.as_ref()
+                    {
+                        ret = Some(DiffViewAction::SelectingLeft(symbol_ref.clone()));
+                    }
+                });
            } else if left_ctx.status.success && !left_ctx.has_symbol() {
                ui.horizontal(|ui| {
                    let mut search = state.search.clone();
@@ -291,6 +357,15 @@ pub fn diff_view_ui(
                {
                    ret = Some(DiffViewAction::OpenSourcePath);
                }
+                if let Some((_, symbol_diff, symbol_idx)) = right_ctx.symbol
+                    && let Some((obj, _)) = right_ctx.obj
+                    && ui
+                        .button("📋 Copy")
+                        .on_hover_text_at_pointer("Copy all rows to clipboard")
+                        .clicked()
+                {
+                    ui.ctx().copy_text(get_asm_text(obj, symbol_diff, symbol_idx, diff_config));
+                }
            });

            // Second row
@@ -665,6 +740,7 @@ fn diff_col_ui(
                appearance,
                column,
                open_sections,
+                diff_config,
            ) {
                match (column, action) {
                    (
@@ -703,6 +779,7 @@ fn diff_col_ui(
                appearance,
                column,
                open_sections,
+                diff_config,
            ) {
                ret = Some(result);
            }
--- a/objdiff-gui/src/views/frame_history.rs
+++ b/objdiff-gui/src/views/frame_history.rs
@@ -104,7 +104,7 @@ impl FrameHistory {
            ));
            let cpu_usage = to_screen.inverse().transform_pos(pointer_pos).y;
            let text = format!("{:.1} ms", 1e3 * cpu_usage);
-            shapes.push(ui.fonts(|f| {
+            shapes.push(ui.fonts_mut(|f| {
                Shape::text(
                    f,
                    pos2(rect.left(), y),
--- a/objdiff-gui/src/views/function_diff.rs
+++ b/objdiff-gui/src/views/function_diff.rs
@@ -217,7 +217,7 @@ fn asm_row_ui(
    if ins_diff.kind != InstructionDiffKind::None {
        ui.painter().rect_filled(ui.available_rect_before_wrap(), 0.0, ui.visuals().faint_bg_color);
    }
-    let space_width = ui.fonts(|f| f.glyph_width(&appearance.code_font, ' '));
+    let space_width = ui.fonts_mut(|f| f.glyph_width(&appearance.code_font, ' '));
    display_row(obj, symbol_idx, ins_diff, diff_config, |segment| {
        if let Some(action) =
            diff_text_ui(ui, segment, appearance, ins_view_state, column, space_width, &response_cb)
--- a/objdiff-gui/src/views/symbol_diff.rs
+++ b/objdiff-gui/src/views/symbol_diff.rs
@@ -6,7 +6,7 @@ use egui::{
 };
 use objdiff_core::{
    diff::{
-        ObjectDiff, SymbolDiff,
+        DiffObjConfig, ObjectDiff, ShowSymbolSizes, SymbolDiff,
        display::{
            HighlightKind, SectionDisplay, SymbolFilter, SymbolNavigationKind, display_sections,
            symbol_context, symbol_hover,
@@ -525,6 +525,7 @@ fn symbol_ui(
    state: &SymbolViewState,
    appearance: &Appearance,
    column: usize,
+    diff_config: &DiffObjConfig,
 ) -> Option<DiffViewAction> {
    let mut ret = None;
    let mut job = LayoutJob::default();
@@ -572,6 +573,21 @@ fn symbol_ui(
        write_text(") ", appearance.text_color, &mut job, appearance.code_font.clone());
    }
    write_text(name, appearance.highlight_color, &mut job, appearance.code_font.clone());
+    if diff_config.show_symbol_sizes == ShowSymbolSizes::Decimal {
+        write_text(
+            &format!(" (size={})", symbol.size),
+            appearance.deemphasized_text_color,
+            &mut job,
+            appearance.code_font.clone(),
+        );
+    } else if diff_config.show_symbol_sizes == ShowSymbolSizes::Hex {
+        write_text(
+            &format!(" (size={:x})", symbol.size),
+            appearance.deemphasized_text_color,
+            &mut job,
+            appearance.code_font.clone(),
+        );
+    }
    let response = egui::Button::selectable(selected, job)
        .ui(ui)
        .on_hover_ui_at_pointer(|ui| symbol_hover_ui(ui, ctx, symbol_idx, appearance));
@@ -646,6 +662,7 @@ pub fn symbol_list_ui(
    appearance: &Appearance,
    column: usize,
    open_sections: Option<bool>,
+    diff_config: &DiffObjConfig,
 ) -> Option<DiffViewAction> {
    let mut ret = None;
    ScrollArea::both().auto_shrink([false, false]).show(ui, |ui| {
@@ -770,6 +787,7 @@ pub fn symbol_list_ui(
                                state,
                                appearance,
                                column,
+                                diff_config,
                            ) {
                                ret = Some(result);
                            }
--- a/objdiff-wasm/Cargo.toml
+++ b/objdiff-wasm/Cargo.toml
@@ -22,8 +22,8 @@ std = ["objdiff-core/std"]

 [dependencies]
 log = { version = "0.4", default-features = false }
-regex = { version = "1.11", default-features = false, features = ["unicode-case"] }
-wit-bindgen = { version = "0.44", default-features = false, features = ["macros"] }
+regex = { version = "1.12", default-features = false, features = ["unicode-case"] }
+wit-bindgen = { version = "0.48", default-features = false, features = ["macros"] }
 xxhash-rust = { version = "0.8", default-features = false, features = ["xxh3"] }

 [dependencies.objdiff-core]
--- a/objdiff-wasm/package-lock.json
+++ b/objdiff-wasm/package-lock.json
@@ -1,12 +1,12 @@
 {
  "name": "objdiff-wasm",
-  "version": "3.3.0",
+  "version": "3.4.2",
  "lockfileVersion": 3,
  "requires": true,
  "packages": {
    "": {
      "name": "objdiff-wasm",
-      "version": "3.3.0",
+      "version": "3.4.2",
      "license": "MIT OR Apache-2.0",
      "devDependencies": {
        "@biomejs/biome": "^1.9.3",
@@ -852,6 +852,7 @@
      "integrity": "sha512-Y3b4Y7lGIvNPywspP38deHkp/EEkTXrJEHeX1K5yz8U/94PkWvPlDebjjiSvmI6TT+9iVzsq22qDlBEdDuJZhA==",
      "dev": true,
      "license": "MIT",
+      "peer": true,
      "dependencies": {
        "@rspack/core": "1.2.3",
        "@rspack/lite-tapable": "~1.0.1",
@@ -1083,6 +1084,7 @@
      "integrity": "sha512-JQ5TuMi45Owi4/BIMAJBoSQoOJu12oOk/gADqlcUL9JEdHB8vyjUSsxqeNXnmXHjYKMi2WcYtezGEEhqUI/E2g==",
      "dev": true,
      "license": "Apache-2.0",
+      "peer": true,
      "dependencies": {
        "tslib": "^2.8.0"
      }
@@ -2139,6 +2141,7 @@
      "integrity": "sha512-M7BAV6Rlcy5u+m6oPhAPFgJTzAioX/6B0DxyvDlo9l8+T3nLKbrczg2WLUyzd45L8RqfUMyGPzekbMvX2Ldkwg==",
      "dev": true,
      "license": "MIT",
+      "peer": true,
      "engines": {
        "node": ">=12"
      },
@@ -2166,6 +2169,7 @@
      "integrity": "sha512-84MVSjMEHP+FQRPy3pX9sTVV/INIex71s9TL2Gm5FG/WG1SqXeKyZ0k7/blY/4FdOzI12CBy1vGc4og/eus0fw==",
      "dev": true,
      "license": "Apache-2.0",
+      "peer": true,
      "bin": {
        "tsc": "bin/tsc",
        "tsserver": "bin/tsserver"
--- a/objdiff-wasm/package.json
+++ b/objdiff-wasm/package.json
@@ -1,6 +1,6 @@
 {
  "name": "objdiff-wasm",
-  "version": "3.3.0",
+  "version": "3.4.2",
  "description": "A local diffing tool for decompilation projects.",
  "author": {
    "name": "Luke Street",
--- a/objdiff-wasm/src/api.rs
+++ b/objdiff-wasm/src/api.rs
@@ -469,16 +469,17 @@ impl From<obj::SymbolFlagSet> for SymbolFlags {
    fn from(flags: obj::SymbolFlagSet) -> SymbolFlags {
        let mut out = SymbolFlags::empty();
        for flag in flags {
-            out |= match flag {
-                obj::SymbolFlag::Global => SymbolFlags::GLOBAL,
-                obj::SymbolFlag::Local => SymbolFlags::LOCAL,
-                obj::SymbolFlag::Weak => SymbolFlags::WEAK,
-                obj::SymbolFlag::Common => SymbolFlags::COMMON,
-                obj::SymbolFlag::Hidden => SymbolFlags::HIDDEN,
-                obj::SymbolFlag::HasExtra => SymbolFlags::HAS_EXTRA,
-                obj::SymbolFlag::SizeInferred => SymbolFlags::SIZE_INFERRED,
-                obj::SymbolFlag::Ignored => SymbolFlags::IGNORED,
-            };
+            out = out
+                | match flag {
+                    obj::SymbolFlag::Global => SymbolFlags::GLOBAL,
+                    obj::SymbolFlag::Local => SymbolFlags::LOCAL,
+                    obj::SymbolFlag::Weak => SymbolFlags::WEAK,
+                    obj::SymbolFlag::Common => SymbolFlags::COMMON,
+                    obj::SymbolFlag::Hidden => SymbolFlags::HIDDEN,
+                    obj::SymbolFlag::HasExtra => SymbolFlags::HAS_EXTRA,
+                    obj::SymbolFlag::SizeInferred => SymbolFlags::SIZE_INFERRED,
+                    obj::SymbolFlag::Ignored => SymbolFlags::IGNORED,
+                };
        }
        out
    }
Author	SHA1	Message	Date
Luke Street	2a24eb5aec	Version 3.4.2	2025-11-21 22:15:20 -07:00
Aetias	f7c291bd55	arm: Fix .word reading 4 bytes when less than 4 remain (#285 )	2025-11-20 15:38:55 -07:00
Luke Street	03a578c1bb	Update test snapshots for new cwextab	2025-11-18 22:29:42 -07:00
Luke Street	d09ef8e207	Version v3.4.1	2025-11-18 22:22:43 -07:00
Luke Street	63552a58ae	Move copy button to first header row	2025-11-18 22:22:02 -07:00
Luke Street	827f4a42bd	Upgrade all dependencies (incl. egui)	2025-11-18 22:21:46 -07:00
Franco M	b2dcecc5d8	Copy button (#271 ) * Update diff.rs * Fixes * More fixes * More fixes... * Cargo fmt * fmt * Trim extra * cargo +nightly fmt * Update 'Copy ASM' button text to include emoji	2025-11-18 22:00:20 -07:00
Dávid Balatoni	67b237eab6	Adjust symbol name matching logic for GCC (#278 ) * Adjust symbol name matching logic for GCC * Turn $ and . into a list * Fix borrow issue	2025-11-18 21:55:55 -07:00
Aetias	66da80ff69	arm: Fix .word not on 4-byte boundary (#282 )	2025-11-18 21:55:40 -07:00
Luke Street	0a85f540f2	Version v3.4.0	2025-11-12 12:22:01 -07:00
Anghelo Carvajal	d79b5b1233	Update gnuv2_demangle to 0.4 (#280 )	2025-11-09 11:53:02 -07:00
Anghelo Carvajal	8f5519cb6a	Update gnuv2_demangle to version 0.3 (#275 )	2025-10-12 21:19:07 -06:00
Aetias	19ec08be9a	Update unarm to 2.0 (#274 ) * Migrate to unarm 2.0 * Update unarm to proper 2.0 release * Deduplicate formatters for opaque instruction parts in ARM * Add option to enable VFPv2 for ARM * Update unarm to 2.0.1 * Fix read order for big-endian Thumb code * Skip leading space in ARM instruction params * Update ARM tests * arm.rs: Use `alloc::borrow::Cow`	2025-10-12 21:13:29 -06:00
Luke Street	2ad0898efa	Version v3.3.1	2025-10-08 21:47:36 -06:00
Ethan Lafrenais	03f2bcb8b1	R_MIPS_GPREL32 Support (#270 ) * R_MIPS_GPREL32 Support * cargo fmt * Add name for R_MIPS_GPREL32 relocation	2025-10-08 20:34:35 -06:00
BR-	781071761a	show symbol size in symbol list (#268 ) * show symbol size in symbol list * configs for show symbol size * move symbol size config to config-schema	2025-10-08 20:32:07 -06:00
Luke Street	572afa8551	Support IDO .mdebug for line numbers (#264 ) * Support IDO .mdebug for line numbers Resolves #179 * Fix wasm build && cargo clippy --fix * Resolve review comment	2025-09-25 10:00:40 -06:00