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isa: remove `mfspr`'s `mftdu` and `mttdu` mnemonics since there are not recognized by the metrowerks assembler

This commit is contained in:
InusualZ 2022-05-31 19:54:51 -04:00
parent 86e081fdb2
commit 3c0656ee3c
2 changed files with 0 additions and 30 deletions
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22
disasm/src/generated.rs
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@ -5708,17 +5708,6 @@ impl Ins {
ins: self, ins: self,
}; };
} }
if (((((self.code >> 11u8) & 0x3ff) & 0b11111_00000u32) >> 5u32)
| ((((self.code >> 11u8) & 0x3ff) & 0b00000_11111u32) << 5u32))
as u32
== 571
{
return SimplifiedIns {
mnemonic: "mftdu",
args: vec![Argument::GPR(GPR(((self.code >> 21u8) & 0x1f) as _))],
ins: self,
};
}
} }
Opcode::Mtspr => { Opcode::Mtspr => {
if (((((self.code >> 11u8) & 0x3ff) & 0b11111_00000u32) >> 5u32) if (((((self.code >> 11u8) & 0x3ff) & 0b11111_00000u32) >> 5u32)
@ -5776,17 +5765,6 @@ impl Ins {
ins: self, ins: self,
}; };
} }
if (((((self.code >> 11u8) & 0x3ff) & 0b11111_00000u32) >> 5u32)
| ((((self.code >> 11u8) & 0x3ff) & 0b00000_11111u32) << 5u32))
as u32
== 571
{
return SimplifiedIns {
mnemonic: "mttdu",
args: vec![Argument::GPR(GPR(((self.code >> 21u8) & 0x1f) as _))],
ins: self,
};
}
} }
Opcode::Or => { Opcode::Or => {
if ((self.code >> 21u8) & 0x1f) == ((self.code >> 11u8) & 0x1f) { if ((self.code >> 21u8) & 0x1f) == ((self.code >> 11u8) & 0x1f) {

8
isa.yaml
View File

@ -2103,10 +2103,6 @@ mnemonics:
opcode: mtspr opcode: mtspr
args: [ rS ] args: [ rS ]
condition: spr == 397 condition: spr == 397
- name: mttdu
opcode: mtspr
args: [ rS ]
condition: spr == 571
# Move from special-purpose register # Move from special-purpose register
- name: mfxer - name: mfxer
@ -2129,10 +2125,6 @@ mnemonics:
opcode: mfspr opcode: mfspr
args: [ rD ] args: [ rD ]
condition: spr == 397 condition: spr == 397
- name: mftdu
opcode: mfspr
args: [ rD ]
condition: spr == 571
# Branch Conditional # Branch Conditional
# bc branch always # bc branch always