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isa: fix `mfcr` argument

This commit is contained in:
InusualZ 2022-05-31 19:17:42 -04:00
parent 65b0966a97
commit 7167807402
3 changed files with 5 additions and 5 deletions
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4
disasm/src/generated.rs
View File

@ -1823,7 +1823,7 @@ impl Ins {
Field::crfS(CRField(((self.code >> 18u8) & 0x7) as _)),
],
Opcode::Mcrxr => vec![Field::crfD(CRField(((self.code >> 23u8) & 0x7) as _))],
Opcode::Mfcr => vec![Field::crfD(CRField(((self.code >> 23u8) & 0x7) as _))],
Opcode::Mfcr => vec![Field::rD(GPR(((self.code >> 21u8) & 0x1f) as _))],
Opcode::Mffs => vec![Field::frD(FPR(((self.code >> 21u8) & 0x1f) as _))],
Opcode::Mfmsr => vec![Field::rD(GPR(((self.code >> 21u8) & 0x1f) as _))],
Opcode::Mfspr => vec![
@ -2562,7 +2562,7 @@ impl Ins {
Field::crfD(CRField(((self.code >> 23u8) & 0x7) as _)),
Field::xer,
],
Opcode::Mfcr => vec![Field::crfD(CRField(((self.code >> 23u8) & 0x7) as _))],
Opcode::Mfcr => vec![Field::rD(GPR(((self.code >> 21u8) & 0x1f) as _))],
Opcode::Mffs => vec![Field::frD(FPR(((self.code >> 21u8) & 0x1f) as _))],
Opcode::Mfmsr => vec![Field::rD(GPR(((self.code >> 21u8) & 0x1f) as _))],
Opcode::Mfspr => vec![Field::rD(GPR(((self.code >> 21u8) & 0x1f) as _))],

2
disasm/tests/test_disasm.rs
View File

@ -483,7 +483,7 @@ fn test_ins_lwzx() {
#[test]
fn test_ins_mfcr() {
assert_asm!(0x7C000026, "mfcr cr0");
assert_asm!(0x7C000026, "mfcr r0");
}
#[test]

4
isa.yaml
View File

@ -1063,8 +1063,8 @@ opcodes:
desc: Move from Condition Register
bitmask: 0xfc1fffff
pattern: 0x7c000026
args: [ crfD ]
defs: [ crfD ]
args: [ rD ]
defs: [ rD ]
- name: mffs
desc: Move from FPSCR