encounter
/
ppc750cl
mirror of https://github.com/encounter/ppc750cl.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

isa: fix `rlwinm`'s mnemonic `slwi` using `ME` instead of `SH` as arg

This commit is contained in:
InusualZ 2022-05-31 19:44:21 -04:00
parent a9ae0cb8a1
commit 86e081fdb2
3 changed files with 5 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
disasm/src/generated.rs
View File

@ -5843,7 +5843,7 @@ impl Ins {
args: vec![ args: vec![
Argument::GPR(GPR(((self.code >> 16u8) & 0x1f) as _)), Argument::GPR(GPR(((self.code >> 16u8) & 0x1f) as _)),
Argument::GPR(GPR(((self.code >> 21u8) & 0x1f) as _)), Argument::GPR(GPR(((self.code >> 21u8) & 0x1f) as _)),
Argument::OpaqueU(OpaqueU(((self.code >> 1u8) & 0x1f) as _)), Argument::OpaqueU(OpaqueU(((self.code >> 11u8) & 0x1f) as _)),
], ],
ins: self, ins: self,
}; };

3
disasm/tests/test_disasm.rs
View File

@ -784,6 +784,9 @@ fn test_ins_rlwimi() {
fn test_ins_rlwinm() { fn test_ins_rlwinm() {
assert_asm!(0x54000423, "rlwinm. r0, r0, 0, 16, 17"); assert_asm!(0x54000423, "rlwinm. r0, r0, 0, 16, 17");
assert_asm!(0x54000432, "rlwinm r0, r0, 0, 16, 25"); assert_asm!(0x54000432, "rlwinm r0, r0, 0, 16, 25");
// mnemonics
assert_asm!(0x57E5103A, "slwi r5, r31, 2");
} }
#[test] #[test]

2
isa.yaml
View File

@ -1976,7 +1976,7 @@ mnemonics:
condition: MB == 0 && ME == 31 condition: MB == 0 && ME == 31
- name: slwi - name: slwi
opcode: rlwinm opcode: rlwinm
args: [ rA, rS, ME ] args: [ rA, rS, SH ]
condition: MB == 0 && 31 - SH == ME condition: MB == 0 && 31 - SH == ME
- name: srwi - name: srwi
opcode: rlwinm opcode: rlwinm