encounter
/
ppc750cl
mirror of https://github.com/encounter/ppc750cl.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Fix clrlslwi decoding

This commit is contained in:
Luke Street 2022-10-16 14:21:50 -04:00
parent 4d8e473331
commit aa631a33de
3 changed files with 32 additions and 29 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

49
disasm/src/generated.rs
View File

@ -7408,30 +7408,6 @@ impl Ins {
ins: self, ins: self,
}; };
} }
if ((self.code >> 11u8) & 0x1f) < 32
&& ((self.code >> 6u8) & 0x1f) >= ((self.code >> 11u8) & 0x1f)
&& ((self.code >> 1u8) & 0x1f) == 31 - ((self.code >> 11u8) & 0x1f)
{
return SimplifiedIns {
mnemonic: "clrlslwi",
suffix: {
{
let mut s = String::with_capacity(4);
if self.bit(31usize) {
s.push('.');
}
s
}
},
args: vec![
Argument::GPR(GPR(((self.code >> 16u8) & 0x1f) as _)),
Argument::GPR(GPR(((self.code >> 21u8) & 0x1f) as _)),
Argument::OpaqueU(OpaqueU((32 - ((self.code >> 11u8) & 0x1f)) as _)),
Argument::OpaqueU(OpaqueU(((self.code >> 11u8) & 0x1f) as _)),
],
ins: self,
};
}
if ((self.code >> 6u8) & 0x1f) == 0 if ((self.code >> 6u8) & 0x1f) == 0
&& ((self.code >> 1u8) & 0x1f) == 31 && ((self.code >> 1u8) & 0x1f) == 31
&& ((self.code >> 11u8) & 0x1f) <= 16 && ((self.code >> 11u8) & 0x1f) <= 16
@ -7522,6 +7498,31 @@ impl Ins {
ins: self, ins: self,
}; };
} }
if ((self.code >> 11u8) & 0x1f) < 32
&& ((self.code >> 1u8) & 0x1f) == 31 - ((self.code >> 11u8) & 0x1f)
{
return SimplifiedIns {
mnemonic: "clrlslwi",
suffix: {
{
let mut s = String::with_capacity(4);
if self.bit(31usize) {
s.push('.');
}
s
}
},
args: vec![
Argument::GPR(GPR(((self.code >> 16u8) & 0x1f) as _)),
Argument::GPR(GPR(((self.code >> 21u8) & 0x1f) as _)),
Argument::OpaqueU(OpaqueU(
(((self.code >> 6u8) & 0x1f) + ((self.code >> 11u8) & 0x1f)) as _,
)),
Argument::OpaqueU(OpaqueU(((self.code >> 11u8) & 0x1f) as _)),
],
ins: self,
};
}
if ((self.code >> 6u8) & 0x1f) == 0 { if ((self.code >> 6u8) & 0x1f) == 0 {
return SimplifiedIns { return SimplifiedIns {
mnemonic: "extlwi", mnemonic: "extlwi",

4
disasm/tests/test_disasm.rs
View File

@ -861,7 +861,9 @@ fn test_ins_rlwinm() {
assert_asm!(0x5483E03E, "rotrwi r3, r4, 4"); assert_asm!(0x5483E03E, "rotrwi r3, r4, 4");
assert_asm!(0x5464043E, "clrlwi r4, r3, 16"); assert_asm!(0x5464043E, "clrlwi r4, r3, 16");
assert_asm!(0x54830036, "clrrwi r3, r4, 4"); assert_asm!(0x54830036, "clrrwi r3, r4, 4");
assert_asm!(0x54640fbc, "clrlslwi r4, r3, 31, 1"); assert_asm!(0x54640FBC, "clrlslwi r4, r3, 31, 1");
assert_asm!(0x54092DB4, "clrlslwi r9, r0, 27, 5");
assert_asm!(0x54096226, "clrlslwi r9, r0, 20, 12");
} }
#[test] #[test]

8
isa.yaml
View File

@ -2002,10 +2002,6 @@ mnemonics:
opcode: rlwinm opcode: rlwinm
args: [ rA, rS, MB ] args: [ rA, rS, MB ]
condition: SH == 0 && ME == 31 condition: SH == 0 && ME == 31
- name: clrlslwi
opcode: rlwinm
args: [ rA, rS, MB=32-SH, SH ]
condition: SH < 32 && MB >= SH && ME == 31 - SH
- name: rotlwi - name: rotlwi
opcode: rlwinm opcode: rlwinm
args: [ rA, rS, SH ] args: [ rA, rS, SH ]
@ -2022,6 +2018,10 @@ mnemonics:
opcode: rlwinm opcode: rlwinm
args: [ rA, rS, MB ] args: [ rA, rS, MB ]
condition: ME == 31 && 32 - MB == SH condition: ME == 31 && 32 - MB == SH
- name: clrlslwi
opcode: rlwinm
args: [ rA, rS, MB=MB+SH, SH ]
condition: SH < 32 && ME == 31 - SH
- name: extlwi - name: extlwi
opcode: rlwinm opcode: rlwinm
args: [ rA, rS, ME=ME+1, SH ] args: [ rA, rS, ME=ME+1, SH ]