2015-07-25 22:59:39 +00:00
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#ifndef _DNACOMMON_GX_HPP_
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#define _DNACOMMON_GX_HPP_
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#include <Athena/DNA.hpp>
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namespace GX
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{
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/* RGBA8 structure (GXColor) */
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struct Color : Athena::io::DNA<Athena::BigEndian>
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{
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Value<atUint8> r;
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Value<atUint8> g;
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Value<atUint8> b;
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Value<atUint8> a;
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Delete expl;
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void read(Athena::io::IStreamReader& reader)
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{reader.readUBytesToBuf(&r, 4);}
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void write(Athena::io::IStreamWriter& writer) const
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{writer.writeUBytes(&r, 4);}
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};
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/* GX enums */
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enum AttrType
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{
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NONE,
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DIRECT,
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INDEX8,
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INDEX16
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};
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enum TevColorArg {
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CC_CPREV = 0, /*!< Use the color value from previous TEV stage */
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CC_APREV = 1, /*!< Use the alpha value from previous TEV stage */
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CC_C0 = 2, /*!< Use the color value from the color/output register 0 */
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CC_A0 = 3, /*!< Use the alpha value from the color/output register 0 */
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CC_C1 = 4, /*!< Use the color value from the color/output register 1 */
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CC_A1 = 5, /*!< Use the alpha value from the color/output register 1 */
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CC_C2 = 6, /*!< Use the color value from the color/output register 2 */
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CC_A2 = 7, /*!< Use the alpha value from the color/output register 2 */
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CC_TEXC = 8, /*!< Use the color value from texture */
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CC_TEXA = 9, /*!< Use the alpha value from texture */
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CC_RASC = 10, /*!< Use the color value from rasterizer */
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CC_RASA = 11, /*!< Use the alpha value from rasterizer */
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CC_ONE = 12,
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CC_HALF = 13,
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CC_KONST = 14,
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CC_ZERO = 15 /*!< Use to pass zero value */
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};
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enum TevAlphaArg {
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CA_APREV = 0, /*!< Use the alpha value from previous TEV stage */
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CA_A0 = 1, /*!< Use the alpha value from the color/output register 0 */
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CA_A1 = 2, /*!< Use the alpha value from the color/output register 1 */
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CA_A2 = 3, /*!< Use the alpha value from the color/output register 2 */
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CA_TEXA = 4, /*!< Use the alpha value from texture */
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CA_RASA = 5, /*!< Use the alpha value from rasterizer */
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CA_KONST = 6,
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CA_ZERO = 7 /*!< Use to pass zero value */
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};
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enum TevKColorSel
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{
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TEV_KCSEL_8_8 = 0x00,
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TEV_KCSEL_7_8 = 0x01,
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TEV_KCSEL_6_8 = 0x02,
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TEV_KCSEL_5_8 = 0x03,
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TEV_KCSEL_4_8 = 0x04,
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TEV_KCSEL_3_8 = 0x05,
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TEV_KCSEL_2_8 = 0x06,
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TEV_KCSEL_1_8 = 0x07,
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TEV_KCSEL_1 = TEV_KCSEL_8_8,
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TEV_KCSEL_3_4 = TEV_KCSEL_6_8,
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TEV_KCSEL_1_2 = TEV_KCSEL_4_8,
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TEV_KCSEL_1_4 = TEV_KCSEL_2_8,
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TEV_KCSEL_K0 = 0x0C,
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TEV_KCSEL_K1 = 0x0D,
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TEV_KCSEL_K2 = 0x0E,
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TEV_KCSEL_K3 = 0x0F,
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TEV_KCSEL_K0_R = 0x10,
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TEV_KCSEL_K1_R = 0x11,
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TEV_KCSEL_K2_R = 0x12,
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TEV_KCSEL_K3_R = 0x13,
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TEV_KCSEL_K0_G = 0x14,
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TEV_KCSEL_K1_G = 0x15,
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TEV_KCSEL_K2_G = 0x16,
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TEV_KCSEL_K3_G = 0x17,
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TEV_KCSEL_K0_B = 0x18,
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TEV_KCSEL_K1_B = 0x19,
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TEV_KCSEL_K2_B = 0x1A,
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TEV_KCSEL_K3_B = 0x1B,
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TEV_KCSEL_K0_A = 0x1C,
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TEV_KCSEL_K1_A = 0x1D,
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TEV_KCSEL_K2_A = 0x1E,
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TEV_KCSEL_K3_A = 0x1F
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};
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enum TevKAlphaSel
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{
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TEV_KASEL_8_8 = 0x00,
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TEV_KASEL_7_8 = 0x01,
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TEV_KASEL_6_8 = 0x02,
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TEV_KASEL_5_8 = 0x03,
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TEV_KASEL_4_8 = 0x04,
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TEV_KASEL_3_8 = 0x05,
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TEV_KASEL_2_8 = 0x06,
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TEV_KASEL_1_8 = 0x07,
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TEV_KASEL_1 = TEV_KASEL_8_8,
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TEV_KASEL_3_4 = TEV_KASEL_6_8,
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TEV_KASEL_1_2 = TEV_KASEL_4_8,
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TEV_KASEL_1_4 = TEV_KASEL_2_8,
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TEV_KASEL_K0_R = 0x10,
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TEV_KASEL_K1_R = 0x11,
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TEV_KASEL_K2_R = 0x12,
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TEV_KASEL_K3_R = 0x13,
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TEV_KASEL_K0_G = 0x14,
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TEV_KASEL_K1_G = 0x15,
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TEV_KASEL_K2_G = 0x16,
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TEV_KASEL_K3_G = 0x17,
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TEV_KASEL_K0_B = 0x18,
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TEV_KASEL_K1_B = 0x19,
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TEV_KASEL_K2_B = 0x1A,
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TEV_KASEL_K3_B = 0x1B,
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TEV_KASEL_K0_A = 0x1C,
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TEV_KASEL_K1_A = 0x1D,
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TEV_KASEL_K2_A = 0x1E,
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TEV_KASEL_K3_A = 0x1F
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};
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enum TevOp {
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TEV_ADD = 0,
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TEV_SUB = 1,
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TEV_COMP_R8_GT = 8,
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TEV_COMP_R8_EQ = 9,
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TEV_COMP_GR16_GT = 10,
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TEV_COMP_GR16_EQ = 11,
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TEV_COMP_BGR24_GT = 12,
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TEV_COMP_BGR24_EQ = 13,
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TEV_COMP_RGB8_GT = 14,
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TEV_COMP_RGB8_EQ = 15,
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TEV_COMP_A8_GT = TEV_COMP_RGB8_GT, // for alpha channel
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TEV_COMP_A8_EQ = TEV_COMP_RGB8_EQ // for alpha channel
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};
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enum TevBias {
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TB_ZERO = 0,
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TB_ADDHALF = 1,
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TB_SUBHALF = 2,
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};
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enum TevScale {
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CS_SCALE_1 = 0,
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CS_SCALE_2 = 1,
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CS_SCALE_4 = 2,
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CS_DIVIDE_2 = 3
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};
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enum TevRegID {
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TEVPREV = 0,
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TEVREG0 = 1,
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TEVREG1 = 2,
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TEVREG2 = 3
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};
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enum TexGenType
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{
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TG_MTX3x4 = 0,
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TG_MTX2x4,
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TG_BUMP0,
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TG_BUMP1,
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TG_BUMP2,
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TG_BUMP3,
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TG_BUMP4,
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TG_BUMP5,
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TG_BUMP6,
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TG_BUMP7,
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TG_SRTG
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};
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enum TexGenSrc
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{
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TG_POS = 0,
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TG_NRM,
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TG_BINRM,
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TG_TANGENT,
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TG_TEX0,
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TG_TEX1,
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TG_TEX2,
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TG_TEX3,
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TG_TEX4,
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TG_TEX5,
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TG_TEX6,
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TG_TEX7,
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TG_TEXCOORD0,
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TG_TEXCOORD1,
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TG_TEXCOORD2,
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TG_TEXCOORD3,
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TG_TEXCOORD4,
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TG_TEXCOORD5,
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TG_TEXCOORD6,
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TG_COLOR0,
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TG_COLOR1
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};
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enum TexMtx
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{
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TEXMTX0 = 30,
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TEXMTX1 = 33,
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TEXMTX2 = 36,
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TEXMTX3 = 39,
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TEXMTX4 = 42,
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TEXMTX5 = 45,
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TEXMTX6 = 48,
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TEXMTX7 = 51,
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TEXMTX8 = 54,
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TEXMTX9 = 57,
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IDENTITY = 60
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};
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enum PTTexMtx
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{
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PTTEXMTX0 = 64,
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PTTEXMTX1 = 67,
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PTTEXMTX2 = 70,
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PTTEXMTX3 = 73,
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PTTEXMTX4 = 76,
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PTTEXMTX5 = 79,
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PTTEXMTX6 = 82,
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PTTEXMTX7 = 85,
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PTTEXMTX8 = 88,
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PTTEXMTX9 = 91,
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PTTEXMTX10 = 94,
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PTTEXMTX11 = 97,
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PTTEXMTX12 = 100,
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PTTEXMTX13 = 103,
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PTTEXMTX14 = 106,
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PTTEXMTX15 = 109,
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PTTEXMTX16 = 112,
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PTTEXMTX17 = 115,
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PTTEXMTX18 = 118,
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PTTEXMTX19 = 121,
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PTIDENTITY = 125
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};
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}
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2015-08-02 23:51:30 +00:00
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#endif // _DNACOMMON_GX_HPP_
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