86e081fdb2
isa: fix `rlwinm`'s mnemonic `slwi` using `ME` instead of `SH` as arg
2022-05-31 20:25:19 -04:00
a9ae0cb8a1
isa: add `RC` modifier to the `xor` instruction
2022-05-31 20:25:15 -04:00
49673468fc
isa: fix `srw` argument order
2022-05-31 20:25:08 -04:00
7167807402
isa: fix `mfcr` argument
2022-05-31 20:24:54 -04:00
65b0966a97
isa: `b` and `bc` change modifiers order
...
Previously they were `modifiers: [ AA, LK ]` and this caused problems,
because the modifiers add a char to the instruction mnemonics, but this
char is position dependant.
2022-05-31 20:24:54 -04:00
ad1ec7aaa9
isa: fix paired single instruction arguments
...
Argument specific to this instruction were re/named to a more dolphin
aligned name
2022-05-31 20:24:29 -04:00
9d5b73c0dc
fix condition register logical instructions
2022-04-09 15:33:40 +02:00
70192c75a4
fix psq_st disasm
2022-04-09 02:09:44 +02:00
99c7f252f8
fix bcctr and bclr
2022-04-07 04:44:38 +02:00
16f955947e
fix bc opcode
2022-04-07 04:23:12 +02:00
b8199e678c
fix signed fields
2022-04-07 04:07:15 +02:00
8a57bd9eb2
more tests
2022-04-07 02:36:49 +02:00
40142dcd9b
support mnemonic suffixes
2021-08-29 09:02:31 +02:00
f04c68578b
re-implement formatting
2021-08-29 06:06:08 +02:00
5833e81236
generate def/use information
2021-08-29 04:25:39 +02:00
7a6b4df8d4
big rewrite, everything half broken
2021-08-25 03:23:57 +02:00
InusualZ
Richard Patel