Luke Street
c4af15ddc2
Rewrite the entire crate, add assembler
...
- 10x faster disassembly performance
- Nearly feature-complete assembler
- `no_std` compatible
- Relicense to MIT/Apache-2.0
- Remove old crates (dol, flow-graph, etc)
- Remove Python bindings (for now, at least)
2024-03-14 00:55:08 -06:00
Luke Street
f6e15052b1
Various bitmask and modifier fixes
2024-03-08 22:50:42 -07:00
Luke Street
87fe934548
Add subi mnemonics & use capstone-style CR bits
2023-10-06 01:06:50 -04:00
Luke Street
3a9be32f66
Fix mcrf, mcrfs, mcrxr, twi, twui
2023-01-14 13:25:40 -05:00
Luke Street
aa631a33de
Fix clrlslwi decoding
2022-10-16 14:21:50 -04:00
Luke Street
4d8e473331
Support branch prediction bits, more bd mnemonics, more rlwinm mnemonics
2022-10-10 17:53:24 -04:00
Luke Street
20abce13e4
SPR names & mfspr/mtspr simplified mnemonics
2022-10-09 22:57:13 -04:00
d1c809b3f6
isa: fix `ps_mr` having `frA` as argument
2022-05-31 20:25:19 -04:00
3c0656ee3c
isa: remove `mfspr`'s `mftdu` and `mttdu` mnemonics since there are not recognized by the metrowerks assembler
2022-05-31 20:25:19 -04:00
86e081fdb2
isa: fix `rlwinm`'s mnemonic `slwi` using `ME` instead of `SH` as arg
2022-05-31 20:25:19 -04:00
a9ae0cb8a1
isa: add `RC` modifier to the `xor` instruction
2022-05-31 20:25:15 -04:00
49673468fc
isa: fix `srw` argument order
2022-05-31 20:25:08 -04:00
2364d17751
isa: remove `RC` modifier from a bunch of instruction
...
This modifier is not part of those instruction
2022-05-31 20:25:01 -04:00
7167807402
isa: fix `mfcr` argument
2022-05-31 20:24:54 -04:00
65b0966a97
isa: `b` and `bc` change modifiers order
...
Previously they were `modifiers: [ AA, LK ]` and this caused problems,
because the modifiers add a char to the instruction mnemonics, but this
char is position dependant.
2022-05-31 20:24:54 -04:00
f4389e5edd
isa: add missing `L` arg to the `cmp` instruction family
...
Also fix the mnemonics for said instruction family
2022-05-31 20:24:36 -04:00
ad1ec7aaa9
isa: fix paired single instruction arguments
...
Argument specific to this instruction were re/named to a more dolphin
aligned name
2022-05-31 20:24:29 -04:00
b90b46ef8e
isa: Add missing argument to `bcctr` and `bclr`
2022-05-31 20:24:29 -04:00
a80372c1b6
disasm: branch helpers, fix split fields
2022-04-11 00:08:39 +02:00
9d5b73c0dc
fix condition register logical instructions
2022-04-09 15:33:40 +02:00
70192c75a4
fix psq_st disasm
2022-04-09 02:09:44 +02:00
4c5735e403
more flexible modifier handling
2022-04-07 05:33:38 +02:00
99c7f252f8
fix bcctr and bclr
2022-04-07 04:44:38 +02:00
16f955947e
fix bc opcode
2022-04-07 04:23:12 +02:00
b8199e678c
fix signed fields
2022-04-07 04:07:15 +02:00
8a57bd9eb2
more tests
2022-04-07 02:36:49 +02:00
82970d166b
isa.yaml: use condition expressions instead of matchers
2022-04-07 01:25:20 +02:00
ea364a52d8
isa.yaml: unquote everything
2022-04-07 01:20:28 +02:00
e9041072e9
support simplified mnemonic conditions
2022-04-07 01:17:31 +02:00
c8c1daaa64
progress mnemonics
2022-04-06 17:41:13 +02:00
5431836376
switch from macro to ahead-of-time generated code
2022-04-06 15:13:55 +02:00
Luke Street
InusualZ
Richard Patel