Commit Graph

28 Commits

Author SHA1 Message Date
Luke Street d63c94c3e2 Add InsIter 2024-04-30 19:44:46 -06:00
Luke Street d31bf75009 API updates and cleanup 2024-03-21 21:32:06 -06:00
Luke Street c4af15ddc2 Rewrite the entire crate, add assembler
- 10x faster disassembly performance
- Nearly feature-complete assembler
- `no_std` compatible
- Relicense to MIT/Apache-2.0
- Remove old crates (dol, flow-graph, etc)
- Remove Python bindings (for now, at least)
2024-03-14 00:55:08 -06:00
Luke Street f6e15052b1 Various bitmask and modifier fixes 2024-03-08 22:50:42 -07:00
Luke Street 87fe934548 Add subi mnemonics & use capstone-style CR bits 2023-10-06 01:06:50 -04:00
Luke Street 3a9be32f66 Fix mcrf, mcrfs, mcrxr, twi, twui 2023-01-14 13:25:40 -05:00
Luke Street aa631a33de Fix clrlslwi decoding 2022-10-16 14:21:50 -04:00
Luke Street 4d8e473331 Support branch prediction bits, more bd mnemonics, more rlwinm mnemonics 2022-10-10 17:53:24 -04:00
Luke Street 20abce13e4 SPR names & mfspr/mtspr simplified mnemonics 2022-10-09 22:57:13 -04:00
Luke Street ca92a30920 Improve CRBit display 2022-10-09 21:41:34 -04:00
InusualZ d23fb912b8 disasm: fix failing tests 2022-06-08 21:33:36 -04:00
InusualZ d1c809b3f6 isa: fix `ps_mr` having `frA` as argument 2022-05-31 20:25:19 -04:00
InusualZ 86e081fdb2 isa: fix `rlwinm`'s mnemonic `slwi` using `ME` instead of `SH` as arg 2022-05-31 20:25:19 -04:00
InusualZ a9ae0cb8a1 isa: add `RC` modifier to the `xor` instruction 2022-05-31 20:25:15 -04:00
InusualZ 49673468fc isa: fix `srw` argument order 2022-05-31 20:25:08 -04:00
InusualZ 7167807402 isa: fix `mfcr` argument 2022-05-31 20:24:54 -04:00
InusualZ 65b0966a97 isa: `b` and `bc` change modifiers order
Previously they were `modifiers: [ AA, LK ]` and this caused problems,
because the modifiers add a char to the instruction mnemonics, but this
char is position dependant.
2022-05-31 20:24:54 -04:00
InusualZ ad1ec7aaa9 isa: fix paired single instruction arguments
Argument specific to this instruction were re/named to a more dolphin
aligned name
2022-05-31 20:24:29 -04:00
Richard Patel 9d5b73c0dc fix condition register logical instructions 2022-04-09 15:33:40 +02:00
Richard Patel 70192c75a4 fix psq_st disasm 2022-04-09 02:09:44 +02:00
Richard Patel 99c7f252f8 fix bcctr and bclr 2022-04-07 04:44:38 +02:00
Richard Patel 16f955947e fix bc opcode 2022-04-07 04:23:12 +02:00
Richard Patel b8199e678c fix signed fields 2022-04-07 04:07:15 +02:00
Richard Patel 8a57bd9eb2 more tests 2022-04-07 02:36:49 +02:00
Richard Patel 40142dcd9b support mnemonic suffixes 2021-08-29 09:02:31 +02:00
Richard Patel f04c68578b re-implement formatting 2021-08-29 06:06:08 +02:00
Richard Patel 5833e81236 generate def/use information 2021-08-29 04:25:39 +02:00
Richard Patel 7a6b4df8d4 big rewrite, everything half broken 2021-08-25 03:23:57 +02:00